arch/x86/events/intel/core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Per core/cpu state
   4  *
   5  * Used to coordinate shared registers between HT threads or
   6  * among events on a single PMU.
   7  */
   8
   9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10
  11 #include <linux/stddef.h>
  12 #include <linux/types.h>
  13 #include <linux/init.h>
  14 #include <linux/slab.h>
  15 #include <linux/export.h>
  16 #include <linux/nmi.h>
  17
  18 #include <asm/cpufeature.h>
  19 #include <asm/hardirq.h>
  20 #include <asm/intel-family.h>
  21 #include <asm/intel_pt.h>
  22 #include <asm/apic.h>
  23 #include <asm/cpu_device_id.h>
  24
  25 #include "../perf_event.h"
  26
  27 /*
  28  * Intel PerfMon, used on Core and later.
  29  */
  30 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
  31 {
  32         [PERF_COUNT_HW_CPU_CYCLES]              = 0x003c,
  33         [PERF_COUNT_HW_INSTRUCTIONS]            = 0x00c0,
  34         [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x4f2e,
  35         [PERF_COUNT_HW_CACHE_MISSES]            = 0x412e,
  36         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x00c4,
  37         [PERF_COUNT_HW_BRANCH_MISSES]           = 0x00c5,
  38         [PERF_COUNT_HW_BUS_CYCLES]              = 0x013c,
  39         [PERF_COUNT_HW_REF_CPU_CYCLES]          = 0x0300, /* pseudo-encoding */
  40 };
  41
  42 static struct event_constraint intel_core_event_constraints[] __read_mostly =
  43 {
  44         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  45         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  46         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  47         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  48         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  49         INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
  50         EVENT_CONSTRAINT_END
  51 };
  52
  53 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
  54 {
  55         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  56         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  57         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  58         INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
  59         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  60         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  61         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  62         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  63         INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
  64         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  65         INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
  66         INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
  67         INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
  68         EVENT_CONSTRAINT_END
  69 };
  70
  71 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
  72 {
  73         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  74         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  75         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  76         INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
  77         INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
  78         INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
  79         INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
  80         INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
  81         INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
  82         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  83         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  84         EVENT_CONSTRAINT_END
  85 };
  86
  87 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
  88 {
  89         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
  90         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
  91         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
  92         EVENT_EXTRA_END
  93 };
  94
  95 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
  96 {
  97         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  98         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  99         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 100         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
 101         INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
 102         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
 103         INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
 104         EVENT_CONSTRAINT_END
 105 };
 106
 107 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 108 {
 109         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 110         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 111         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 112         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 113         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 114         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 115         INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 116         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
 117         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 118         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 119         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 120         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 121
 122         /*
 123          * When HT is off these events can only run on the bottom 4 counters
 124          * When HT is on, they are impacted by the HT bug and require EXCL access
 125          */
 126         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 127         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 128         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 129         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 130
 131         EVENT_CONSTRAINT_END
 132 };
 133
 134 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
 135 {
 136         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 137         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 138         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 139         INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
 140         INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
 141         INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
 142         INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
 143         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 144         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 145         INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
 146         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 147         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 148         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 149
 150         /*
 151          * When HT is off these events can only run on the bottom 4 counters
 152          * When HT is on, they are impacted by the HT bug and require EXCL access
 153          */
 154         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 155         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 156         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 157         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 158
 159         EVENT_CONSTRAINT_END
 160 };
 161
 162 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
 163 {
 164         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 165         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
 166         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
 167         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
 168         EVENT_EXTRA_END
 169 };
 170
 171 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
 172 {
 173         EVENT_CONSTRAINT_END
 174 };
 175
 176 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
 177 {
 178         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 179         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 180         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 181         EVENT_CONSTRAINT_END
 182 };
 183
 184 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
 185 {
 186         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 187         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 188         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
 189         EVENT_CONSTRAINT_END
 190 };
 191
 192 static struct event_constraint intel_skl_event_constraints[] = {
 193         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 194         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 195         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 196         INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2),    /* INST_RETIRED.PREC_DIST */
 197
 198         /*
 199          * when HT is off, these can only run on the bottom 4 counters
 200          */
 201         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),      /* MEM_INST_RETIRED.* */
 202         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),      /* MEM_LOAD_RETIRED.* */
 203         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),      /* MEM_LOAD_L3_HIT_RETIRED.* */
 204         INTEL_EVENT_CONSTRAINT(0xcd, 0xf),      /* MEM_TRANS_RETIRED.* */
 205         INTEL_EVENT_CONSTRAINT(0xc6, 0xf),      /* FRONTEND_RETIRED.* */
 206
 207         EVENT_CONSTRAINT_END
 208 };
 209
 210 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
 211         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
 212         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
 213         EVENT_EXTRA_END
 214 };
 215
 216 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
 217         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 218         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
 219         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
 220         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 221         EVENT_EXTRA_END
 222 };
 223
 224 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
 225         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 226         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 227         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 228         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 229         EVENT_EXTRA_END
 230 };
 231
 232 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
 233         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 234         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 235         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 236         /*
 237          * Note the low 8 bits eventsel code is not a continuous field, containing
 238          * some #GPing bits. These are masked out.
 239          */
 240         INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
 241         EVENT_EXTRA_END
 242 };
 243
 244 static struct event_constraint intel_icl_event_constraints[] = {
 245         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 246         FIXED_EVENT_CONSTRAINT(0x01c0, 0),      /* INST_RETIRED.PREC_DIST */
 247         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 248         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 249         FIXED_EVENT_CONSTRAINT(0x0400, 3),      /* SLOTS */
 250         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
 251         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
 252         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
 253         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
 254         INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
 255         INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
 256         INTEL_EVENT_CONSTRAINT(0x32, 0xf),      /* SW_PREFETCH_ACCESS.* */
 257         INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf),
 258         INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
 259         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff),  /* CYCLE_ACTIVITY.STALLS_TOTAL */
 260         INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff),  /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
 261         INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff),  /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
 262         INTEL_EVENT_CONSTRAINT(0xa3, 0xf),      /* CYCLE_ACTIVITY.* */
 263         INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
 264         INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
 265         INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
 266         INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
 267         EVENT_CONSTRAINT_END
 268 };
 269
 270 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
 271         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
 272         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
 273         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 274         INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
 275         EVENT_EXTRA_END
 276 };
 277
 278 static struct extra_reg intel_spr_extra_regs[] __read_mostly = {
 279         INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
 280         INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
 281         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 282         INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
 283         EVENT_EXTRA_END
 284 };
 285
 286 static struct event_constraint intel_spr_event_constraints[] = {
 287         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 288         FIXED_EVENT_CONSTRAINT(0x01c0, 0),      /* INST_RETIRED.PREC_DIST */
 289         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 290         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 291         FIXED_EVENT_CONSTRAINT(0x0400, 3),      /* SLOTS */
 292         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
 293         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
 294         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
 295         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
 296         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
 297         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
 298         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
 299         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
 300
 301         INTEL_EVENT_CONSTRAINT(0x2e, 0xff),
 302         INTEL_EVENT_CONSTRAINT(0x3c, 0xff),
 303         /*
 304          * Generally event codes < 0x90 are restricted to counters 0-3.
 305          * The 0x2E and 0x3C are exception, which has no restriction.
 306          */
 307         INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
 308
 309         INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
 310         INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
 311         INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
 312         INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
 313         INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
 314         INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
 315         INTEL_EVENT_CONSTRAINT(0xce, 0x1),
 316         INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
 317         /*
 318          * Generally event codes >= 0x90 are likely to have no restrictions.
 319          * The exception are defined as above.
 320          */
 321         INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff),
 322
 323         EVENT_CONSTRAINT_END
 324 };
 325
 326
 327 EVENT_ATTR_STR(mem-loads,       mem_ld_nhm,     "event=0x0b,umask=0x10,ldlat=3");
 328 EVENT_ATTR_STR(mem-loads,       mem_ld_snb,     "event=0xcd,umask=0x1,ldlat=3");
 329 EVENT_ATTR_STR(mem-stores,      mem_st_snb,     "event=0xcd,umask=0x2");
 330
 331 static struct attribute *nhm_mem_events_attrs[] = {
 332         EVENT_PTR(mem_ld_nhm),
 333         NULL,
 334 };
 335
 336 /*
 337  * topdown events for Intel Core CPUs.
 338  *
 339  * The events are all in slots, which is a free slot in a 4 wide
 340  * pipeline. Some events are already reported in slots, for cycle
 341  * events we multiply by the pipeline width (4).
 342  *
 343  * With Hyper Threading on, topdown metrics are either summed or averaged
 344  * between the threads of a core: (count_t0 + count_t1).
 345  *
 346  * For the average case the metric is always scaled to pipeline width,
 347  * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
 348  */
 349
 350 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
 351         "event=0x3c,umask=0x0",                 /* cpu_clk_unhalted.thread */
 352         "event=0x3c,umask=0x0,any=1");          /* cpu_clk_unhalted.thread_any */
 353 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
 354 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
 355         "event=0xe,umask=0x1");                 /* uops_issued.any */
 356 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
 357         "event=0xc2,umask=0x2");                /* uops_retired.retire_slots */
 358 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
 359         "event=0x9c,umask=0x1");                /* idq_uops_not_delivered_core */
 360 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
 361         "event=0xd,umask=0x3,cmask=1",          /* int_misc.recovery_cycles */
 362         "event=0xd,umask=0x3,cmask=1,any=1");   /* int_misc.recovery_cycles_any */
 363 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
 364         "4", "2");
 365
 366 EVENT_ATTR_STR(slots,                   slots,                  "event=0x00,umask=0x4");
 367 EVENT_ATTR_STR(topdown-retiring,        td_retiring,            "event=0x00,umask=0x80");
 368 EVENT_ATTR_STR(topdown-bad-spec,        td_bad_spec,            "event=0x00,umask=0x81");
 369 EVENT_ATTR_STR(topdown-fe-bound,        td_fe_bound,            "event=0x00,umask=0x82");
 370 EVENT_ATTR_STR(topdown-be-bound,        td_be_bound,            "event=0x00,umask=0x83");
 371 EVENT_ATTR_STR(topdown-heavy-ops,       td_heavy_ops,           "event=0x00,umask=0x84");
 372 EVENT_ATTR_STR(topdown-br-mispredict,   td_br_mispredict,       "event=0x00,umask=0x85");
 373 EVENT_ATTR_STR(topdown-fetch-lat,       td_fetch_lat,           "event=0x00,umask=0x86");
 374 EVENT_ATTR_STR(topdown-mem-bound,       td_mem_bound,           "event=0x00,umask=0x87");
 375
 376 static struct attribute *snb_events_attrs[] = {
 377         EVENT_PTR(td_slots_issued),
 378         EVENT_PTR(td_slots_retired),
 379         EVENT_PTR(td_fetch_bubbles),
 380         EVENT_PTR(td_total_slots),
 381         EVENT_PTR(td_total_slots_scale),
 382         EVENT_PTR(td_recovery_bubbles),
 383         EVENT_PTR(td_recovery_bubbles_scale),
 384         NULL,
 385 };
 386
 387 static struct attribute *snb_mem_events_attrs[] = {
 388         EVENT_PTR(mem_ld_snb),
 389         EVENT_PTR(mem_st_snb),
 390         NULL,
 391 };
 392
 393 static struct event_constraint intel_hsw_event_constraints[] = {
 394         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 395         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 396         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 397         INTEL_UEVENT_CONSTRAINT(0x148, 0x4),    /* L1D_PEND_MISS.PENDING */
 398         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 399         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 400         /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 401         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
 402         /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 403         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
 404         /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 405         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
 406
 407         /*
 408          * When HT is off these events can only run on the bottom 4 counters
 409          * When HT is on, they are impacted by the HT bug and require EXCL access
 410          */
 411         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 412         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 413         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 414         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 415
 416         EVENT_CONSTRAINT_END
 417 };
 418
 419 static struct event_constraint intel_bdw_event_constraints[] = {
 420         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 421         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 422         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 423         INTEL_UEVENT_CONSTRAINT(0x148, 0x4),    /* L1D_PEND_MISS.PENDING */
 424         INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4),        /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
 425         /*
 426          * when HT is off, these can only run on the bottom 4 counters
 427          */
 428         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),      /* MEM_INST_RETIRED.* */
 429         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),      /* MEM_LOAD_RETIRED.* */
 430         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),      /* MEM_LOAD_L3_HIT_RETIRED.* */
 431         INTEL_EVENT_CONSTRAINT(0xcd, 0xf),      /* MEM_TRANS_RETIRED.* */
 432         EVENT_CONSTRAINT_END
 433 };
 434
 435 static u64 intel_pmu_event_map(int hw_event)
 436 {
 437         return intel_perfmon_event_map[hw_event];
 438 }
 439
 440 static __initconst const u64 spr_hw_cache_event_ids
 441                                 [PERF_COUNT_HW_CACHE_MAX]
 442                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 443                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 444 {
 445  [ C(L1D ) ] = {
 446         [ C(OP_READ) ] = {
 447                 [ C(RESULT_ACCESS) ] = 0x81d0,
 448                 [ C(RESULT_MISS)   ] = 0xe124,
 449         },
 450         [ C(OP_WRITE) ] = {
 451                 [ C(RESULT_ACCESS) ] = 0x82d0,
 452         },
 453  },
 454  [ C(L1I ) ] = {
 455         [ C(OP_READ) ] = {
 456                 [ C(RESULT_MISS)   ] = 0xe424,
 457         },
 458         [ C(OP_WRITE) ] = {
 459                 [ C(RESULT_ACCESS) ] = -1,
 460                 [ C(RESULT_MISS)   ] = -1,
 461         },
 462  },
 463  [ C(LL  ) ] = {
 464         [ C(OP_READ) ] = {
 465                 [ C(RESULT_ACCESS) ] = 0x12a,
 466                 [ C(RESULT_MISS)   ] = 0x12a,
 467         },
 468         [ C(OP_WRITE) ] = {
 469                 [ C(RESULT_ACCESS) ] = 0x12a,
 470                 [ C(RESULT_MISS)   ] = 0x12a,
 471         },
 472  },
 473  [ C(DTLB) ] = {
 474         [ C(OP_READ) ] = {
 475                 [ C(RESULT_ACCESS) ] = 0x81d0,
 476                 [ C(RESULT_MISS)   ] = 0xe12,
 477         },
 478         [ C(OP_WRITE) ] = {
 479                 [ C(RESULT_ACCESS) ] = 0x82d0,
 480                 [ C(RESULT_MISS)   ] = 0xe13,
 481         },
 482  },
 483  [ C(ITLB) ] = {
 484         [ C(OP_READ) ] = {
 485                 [ C(RESULT_ACCESS) ] = -1,
 486                 [ C(RESULT_MISS)   ] = 0xe11,
 487         },
 488         [ C(OP_WRITE) ] = {
 489                 [ C(RESULT_ACCESS) ] = -1,
 490                 [ C(RESULT_MISS)   ] = -1,
 491         },
 492         [ C(OP_PREFETCH) ] = {
 493                 [ C(RESULT_ACCESS) ] = -1,
 494                 [ C(RESULT_MISS)   ] = -1,
 495         },
 496  },
 497  [ C(BPU ) ] = {
 498         [ C(OP_READ) ] = {
 499                 [ C(RESULT_ACCESS) ] = 0x4c4,
 500                 [ C(RESULT_MISS)   ] = 0x4c5,
 501         },
 502         [ C(OP_WRITE) ] = {
 503                 [ C(RESULT_ACCESS) ] = -1,
 504                 [ C(RESULT_MISS)   ] = -1,
 505         },
 506         [ C(OP_PREFETCH) ] = {
 507                 [ C(RESULT_ACCESS) ] = -1,
 508                 [ C(RESULT_MISS)   ] = -1,
 509         },
 510  },
 511  [ C(NODE) ] = {
 512         [ C(OP_READ) ] = {
 513                 [ C(RESULT_ACCESS) ] = 0x12a,
 514                 [ C(RESULT_MISS)   ] = 0x12a,
 515         },
 516  },
 517 };
 518
 519 static __initconst const u64 spr_hw_cache_extra_regs
 520                                 [PERF_COUNT_HW_CACHE_MAX]
 521                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 522                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 523 {
 524  [ C(LL  ) ] = {
 525         [ C(OP_READ) ] = {
 526                 [ C(RESULT_ACCESS) ] = 0x10001,
 527                 [ C(RESULT_MISS)   ] = 0x3fbfc00001,
 528         },
 529         [ C(OP_WRITE) ] = {
 530                 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
 531                 [ C(RESULT_MISS)   ] = 0x3f3fc00002,
 532         },
 533  },
 534  [ C(NODE) ] = {
 535         [ C(OP_READ) ] = {
 536                 [ C(RESULT_ACCESS) ] = 0x10c000001,
 537                 [ C(RESULT_MISS)   ] = 0x3fb3000001,
 538         },
 539  },
 540 };
 541
 542 /*
 543  * Notes on the events:
 544  * - data reads do not include code reads (comparable to earlier tables)
 545  * - data counts include speculative execution (except L1 write, dtlb, bpu)
 546  * - remote node access includes remote memory, remote cache, remote mmio.
 547  * - prefetches are not included in the counts.
 548  * - icache miss does not include decoded icache
 549  */
 550
 551 #define SKL_DEMAND_DATA_RD              BIT_ULL(0)
 552 #define SKL_DEMAND_RFO                  BIT_ULL(1)
 553 #define SKL_ANY_RESPONSE                BIT_ULL(16)
 554 #define SKL_SUPPLIER_NONE               BIT_ULL(17)
 555 #define SKL_L3_MISS_LOCAL_DRAM          BIT_ULL(26)
 556 #define SKL_L3_MISS_REMOTE_HOP0_DRAM    BIT_ULL(27)
 557 #define SKL_L3_MISS_REMOTE_HOP1_DRAM    BIT_ULL(28)
 558 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM   BIT_ULL(29)
 559 #define SKL_L3_MISS                     (SKL_L3_MISS_LOCAL_DRAM| \
 560                                          SKL_L3_MISS_REMOTE_HOP0_DRAM| \
 561                                          SKL_L3_MISS_REMOTE_HOP1_DRAM| \
 562                                          SKL_L3_MISS_REMOTE_HOP2P_DRAM)
 563 #define SKL_SPL_HIT                     BIT_ULL(30)
 564 #define SKL_SNOOP_NONE                  BIT_ULL(31)
 565 #define SKL_SNOOP_NOT_NEEDED            BIT_ULL(32)
 566 #define SKL_SNOOP_MISS                  BIT_ULL(33)
 567 #define SKL_SNOOP_HIT_NO_FWD            BIT_ULL(34)
 568 #define SKL_SNOOP_HIT_WITH_FWD          BIT_ULL(35)
 569 #define SKL_SNOOP_HITM                  BIT_ULL(36)
 570 #define SKL_SNOOP_NON_DRAM              BIT_ULL(37)
 571 #define SKL_ANY_SNOOP                   (SKL_SPL_HIT|SKL_SNOOP_NONE| \
 572                                          SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
 573                                          SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
 574                                          SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
 575 #define SKL_DEMAND_READ                 SKL_DEMAND_DATA_RD
 576 #define SKL_SNOOP_DRAM                  (SKL_SNOOP_NONE| \
 577                                          SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
 578                                          SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
 579                                          SKL_SNOOP_HITM|SKL_SPL_HIT)
 580 #define SKL_DEMAND_WRITE                SKL_DEMAND_RFO
 581 #define SKL_LLC_ACCESS                  SKL_ANY_RESPONSE
 582 #define SKL_L3_MISS_REMOTE              (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
 583                                          SKL_L3_MISS_REMOTE_HOP1_DRAM| \
 584                                          SKL_L3_MISS_REMOTE_HOP2P_DRAM)
 585
 586 static __initconst const u64 skl_hw_cache_event_ids
 587                                 [PERF_COUNT_HW_CACHE_MAX]
 588                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 589                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 590 {
 591  [ C(L1D ) ] = {
 592         [ C(OP_READ) ] = {
 593                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_INST_RETIRED.ALL_LOADS */
 594                 [ C(RESULT_MISS)   ] = 0x151,   /* L1D.REPLACEMENT */
 595         },
 596         [ C(OP_WRITE) ] = {
 597                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_INST_RETIRED.ALL_STORES */
 598                 [ C(RESULT_MISS)   ] = 0x0,
 599         },
 600         [ C(OP_PREFETCH) ] = {
 601                 [ C(RESULT_ACCESS) ] = 0x0,
 602                 [ C(RESULT_MISS)   ] = 0x0,
 603         },
 604  },
 605  [ C(L1I ) ] = {
 606         [ C(OP_READ) ] = {
 607                 [ C(RESULT_ACCESS) ] = 0x0,
 608                 [ C(RESULT_MISS)   ] = 0x283,   /* ICACHE_64B.MISS */
 609         },
 610         [ C(OP_WRITE) ] = {
 611                 [ C(RESULT_ACCESS) ] = -1,
 612                 [ C(RESULT_MISS)   ] = -1,
 613         },
 614         [ C(OP_PREFETCH) ] = {
 615                 [ C(RESULT_ACCESS) ] = 0x0,
 616                 [ C(RESULT_MISS)   ] = 0x0,
 617         },
 618  },
 619  [ C(LL  ) ] = {
 620         [ C(OP_READ) ] = {
 621                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 622                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 623         },
 624         [ C(OP_WRITE) ] = {
 625                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 626                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 627         },
 628         [ C(OP_PREFETCH) ] = {
 629                 [ C(RESULT_ACCESS) ] = 0x0,
 630                 [ C(RESULT_MISS)   ] = 0x0,
 631         },
 632  },
 633  [ C(DTLB) ] = {
 634         [ C(OP_READ) ] = {
 635                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_INST_RETIRED.ALL_LOADS */
 636                 [ C(RESULT_MISS)   ] = 0xe08,   /* DTLB_LOAD_MISSES.WALK_COMPLETED */
 637         },
 638         [ C(OP_WRITE) ] = {
 639                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_INST_RETIRED.ALL_STORES */
 640                 [ C(RESULT_MISS)   ] = 0xe49,   /* DTLB_STORE_MISSES.WALK_COMPLETED */
 641         },
 642         [ C(OP_PREFETCH) ] = {
 643                 [ C(RESULT_ACCESS) ] = 0x0,
 644                 [ C(RESULT_MISS)   ] = 0x0,
 645         },
 646  },
 647  [ C(ITLB) ] = {
 648         [ C(OP_READ) ] = {
 649                 [ C(RESULT_ACCESS) ] = 0x2085,  /* ITLB_MISSES.STLB_HIT */
 650                 [ C(RESULT_MISS)   ] = 0xe85,   /* ITLB_MISSES.WALK_COMPLETED */
 651         },
 652         [ C(OP_WRITE) ] = {
 653                 [ C(RESULT_ACCESS) ] = -1,
 654                 [ C(RESULT_MISS)   ] = -1,
 655         },
 656         [ C(OP_PREFETCH) ] = {
 657                 [ C(RESULT_ACCESS) ] = -1,
 658                 [ C(RESULT_MISS)   ] = -1,
 659         },
 660  },
 661  [ C(BPU ) ] = {
 662         [ C(OP_READ) ] = {
 663                 [ C(RESULT_ACCESS) ] = 0xc4,    /* BR_INST_RETIRED.ALL_BRANCHES */
 664                 [ C(RESULT_MISS)   ] = 0xc5,    /* BR_MISP_RETIRED.ALL_BRANCHES */
 665         },
 666         [ C(OP_WRITE) ] = {
 667                 [ C(RESULT_ACCESS) ] = -1,
 668                 [ C(RESULT_MISS)   ] = -1,
 669         },
 670         [ C(OP_PREFETCH) ] = {
 671                 [ C(RESULT_ACCESS) ] = -1,
 672                 [ C(RESULT_MISS)   ] = -1,
 673         },
 674  },
 675  [ C(NODE) ] = {
 676         [ C(OP_READ) ] = {
 677                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 678                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 679         },
 680         [ C(OP_WRITE) ] = {
 681                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 682                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 683         },
 684         [ C(OP_PREFETCH) ] = {
 685                 [ C(RESULT_ACCESS) ] = 0x0,
 686                 [ C(RESULT_MISS)   ] = 0x0,
 687         },
 688  },
 689 };
 690
 691 static __initconst const u64 skl_hw_cache_extra_regs
 692                                 [PERF_COUNT_HW_CACHE_MAX]
 693                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 694                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 695 {
 696  [ C(LL  ) ] = {
 697         [ C(OP_READ) ] = {
 698                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
 699                                        SKL_LLC_ACCESS|SKL_ANY_SNOOP,
 700                 [ C(RESULT_MISS)   ] = SKL_DEMAND_READ|
 701                                        SKL_L3_MISS|SKL_ANY_SNOOP|
 702                                        SKL_SUPPLIER_NONE,
 703         },
 704         [ C(OP_WRITE) ] = {
 705                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
 706                                        SKL_LLC_ACCESS|SKL_ANY_SNOOP,
 707                 [ C(RESULT_MISS)   ] = SKL_DEMAND_WRITE|
 708                                        SKL_L3_MISS|SKL_ANY_SNOOP|
 709                                        SKL_SUPPLIER_NONE,
 710         },
 711         [ C(OP_PREFETCH) ] = {
 712                 [ C(RESULT_ACCESS) ] = 0x0,
 713                 [ C(RESULT_MISS)   ] = 0x0,
 714         },
 715  },
 716  [ C(NODE) ] = {
 717         [ C(OP_READ) ] = {
 718                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
 719                                        SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
 720                 [ C(RESULT_MISS)   ] = SKL_DEMAND_READ|
 721                                        SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
 722         },
 723         [ C(OP_WRITE) ] = {
 724                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
 725                                        SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
 726                 [ C(RESULT_MISS)   ] = SKL_DEMAND_WRITE|
 727                                        SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
 728         },
 729         [ C(OP_PREFETCH) ] = {
 730                 [ C(RESULT_ACCESS) ] = 0x0,
 731                 [ C(RESULT_MISS)   ] = 0x0,
 732         },
 733  },
 734 };
 735
 736 #define SNB_DMND_DATA_RD        (1ULL << 0)
 737 #define SNB_DMND_RFO            (1ULL << 1)
 738 #define SNB_DMND_IFETCH         (1ULL << 2)
 739 #define SNB_DMND_WB             (1ULL << 3)
 740 #define SNB_PF_DATA_RD          (1ULL << 4)
 741 #define SNB_PF_RFO              (1ULL << 5)
 742 #define SNB_PF_IFETCH           (1ULL << 6)
 743 #define SNB_LLC_DATA_RD         (1ULL << 7)
 744 #define SNB_LLC_RFO             (1ULL << 8)
 745 #define SNB_LLC_IFETCH          (1ULL << 9)
 746 #define SNB_BUS_LOCKS           (1ULL << 10)
 747 #define SNB_STRM_ST             (1ULL << 11)
 748 #define SNB_OTHER               (1ULL << 15)
 749 #define SNB_RESP_ANY            (1ULL << 16)
 750 #define SNB_NO_SUPP             (1ULL << 17)
 751 #define SNB_LLC_HITM            (1ULL << 18)
 752 #define SNB_LLC_HITE            (1ULL << 19)
 753 #define SNB_LLC_HITS            (1ULL << 20)
 754 #define SNB_LLC_HITF            (1ULL << 21)
 755 #define SNB_LOCAL               (1ULL << 22)
 756 #define SNB_REMOTE              (0xffULL << 23)
 757 #define SNB_SNP_NONE            (1ULL << 31)
 758 #define SNB_SNP_NOT_NEEDED      (1ULL << 32)
 759 #define SNB_SNP_MISS            (1ULL << 33)
 760 #define SNB_NO_FWD              (1ULL << 34)
 761 #define SNB_SNP_FWD             (1ULL << 35)
 762 #define SNB_HITM                (1ULL << 36)
 763 #define SNB_NON_DRAM            (1ULL << 37)
 764
 765 #define SNB_DMND_READ           (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
 766 #define SNB_DMND_WRITE          (SNB_DMND_RFO|SNB_LLC_RFO)
 767 #define SNB_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
 768
 769 #define SNB_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
 770                                  SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
 771                                  SNB_HITM)
 772
 773 #define SNB_DRAM_ANY            (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
 774 #define SNB_DRAM_REMOTE         (SNB_REMOTE|SNB_SNP_ANY)
 775
 776 #define SNB_L3_ACCESS           SNB_RESP_ANY
 777 #define SNB_L3_MISS             (SNB_DRAM_ANY|SNB_NON_DRAM)
 778
 779 static __initconst const u64 snb_hw_cache_extra_regs
 780                                 [PERF_COUNT_HW_CACHE_MAX]
 781                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 782                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 783 {
 784  [ C(LL  ) ] = {
 785         [ C(OP_READ) ] = {
 786                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
 787                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_L3_MISS,
 788         },
 789         [ C(OP_WRITE) ] = {
 790                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
 791                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_L3_MISS,
 792         },
 793         [ C(OP_PREFETCH) ] = {
 794                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
 795                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
 796         },
 797  },
 798  [ C(NODE) ] = {
 799         [ C(OP_READ) ] = {
 800                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
 801                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
 802         },
 803         [ C(OP_WRITE) ] = {
 804                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
 805                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
 806         },
 807         [ C(OP_PREFETCH) ] = {
 808                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
 809                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
 810         },
 811  },
 812 };
 813
 814 static __initconst const u64 snb_hw_cache_event_ids
 815                                 [PERF_COUNT_HW_CACHE_MAX]
 816                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 817                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 818 {
 819  [ C(L1D) ] = {
 820         [ C(OP_READ) ] = {
 821                 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS        */
 822                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPLACEMENT              */
 823         },
 824         [ C(OP_WRITE) ] = {
 825                 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES       */
 826                 [ C(RESULT_MISS)   ] = 0x0851, /* L1D.ALL_M_REPLACEMENT        */
 827         },
 828         [ C(OP_PREFETCH) ] = {
 829                 [ C(RESULT_ACCESS) ] = 0x0,
 830                 [ C(RESULT_MISS)   ] = 0x024e, /* HW_PRE_REQ.DL1_MISS          */
 831         },
 832  },
 833  [ C(L1I ) ] = {
 834         [ C(OP_READ) ] = {
 835                 [ C(RESULT_ACCESS) ] = 0x0,
 836                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACHE.MISSES */
 837         },
 838         [ C(OP_WRITE) ] = {
 839                 [ C(RESULT_ACCESS) ] = -1,
 840                 [ C(RESULT_MISS)   ] = -1,
 841         },
 842         [ C(OP_PREFETCH) ] = {
 843                 [ C(RESULT_ACCESS) ] = 0x0,
 844                 [ C(RESULT_MISS)   ] = 0x0,
 845         },
 846  },
 847  [ C(LL  ) ] = {
 848         [ C(OP_READ) ] = {
 849                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 850                 [ C(RESULT_ACCESS) ] = 0x01b7,
 851                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 852                 [ C(RESULT_MISS)   ] = 0x01b7,
 853         },
 854         [ C(OP_WRITE) ] = {
 855                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 856                 [ C(RESULT_ACCESS) ] = 0x01b7,
 857                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 858                 [ C(RESULT_MISS)   ] = 0x01b7,
 859         },
 860         [ C(OP_PREFETCH) ] = {
 861                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 862                 [ C(RESULT_ACCESS) ] = 0x01b7,
 863                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 864                 [ C(RESULT_MISS)   ] = 0x01b7,
 865         },
 866  },
 867  [ C(DTLB) ] = {
 868         [ C(OP_READ) ] = {
 869                 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
 870                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
 871         },
 872         [ C(OP_WRITE) ] = {
 873                 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
 874                 [ C(RESULT_MISS)   ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
 875         },
 876         [ C(OP_PREFETCH) ] = {
 877                 [ C(RESULT_ACCESS) ] = 0x0,
 878                 [ C(RESULT_MISS)   ] = 0x0,
 879         },
 880  },
 881  [ C(ITLB) ] = {
 882         [ C(OP_READ) ] = {
 883                 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT         */
 884                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK    */
 885         },
 886         [ C(OP_WRITE) ] = {
 887                 [ C(RESULT_ACCESS) ] = -1,
 888                 [ C(RESULT_MISS)   ] = -1,
 889         },
 890         [ C(OP_PREFETCH) ] = {
 891                 [ C(RESULT_ACCESS) ] = -1,
 892                 [ C(RESULT_MISS)   ] = -1,
 893         },
 894  },
 895  [ C(BPU ) ] = {
 896         [ C(OP_READ) ] = {
 897                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 898                 [ C(RESULT_MISS)   ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
 899         },
 900         [ C(OP_WRITE) ] = {
 901                 [ C(RESULT_ACCESS) ] = -1,
 902                 [ C(RESULT_MISS)   ] = -1,
 903         },
 904         [ C(OP_PREFETCH) ] = {
 905                 [ C(RESULT_ACCESS) ] = -1,
 906                 [ C(RESULT_MISS)   ] = -1,
 907         },
 908  },
 909  [ C(NODE) ] = {
 910         [ C(OP_READ) ] = {
 911                 [ C(RESULT_ACCESS) ] = 0x01b7,
 912                 [ C(RESULT_MISS)   ] = 0x01b7,
 913         },
 914         [ C(OP_WRITE) ] = {
 915                 [ C(RESULT_ACCESS) ] = 0x01b7,
 916                 [ C(RESULT_MISS)   ] = 0x01b7,
 917         },
 918         [ C(OP_PREFETCH) ] = {
 919                 [ C(RESULT_ACCESS) ] = 0x01b7,
 920                 [ C(RESULT_MISS)   ] = 0x01b7,
 921         },
 922  },
 923
 924 };
 925
 926 /*
 927  * Notes on the events:
 928  * - data reads do not include code reads (comparable to earlier tables)
 929  * - data counts include speculative execution (except L1 write, dtlb, bpu)
 930  * - remote node access includes remote memory, remote cache, remote mmio.
 931  * - prefetches are not included in the counts because they are not
 932  *   reliably counted.
 933  */
 934
 935 #define HSW_DEMAND_DATA_RD              BIT_ULL(0)
 936 #define HSW_DEMAND_RFO                  BIT_ULL(1)
 937 #define HSW_ANY_RESPONSE                BIT_ULL(16)
 938 #define HSW_SUPPLIER_NONE               BIT_ULL(17)
 939 #define HSW_L3_MISS_LOCAL_DRAM          BIT_ULL(22)
 940 #define HSW_L3_MISS_REMOTE_HOP0         BIT_ULL(27)
 941 #define HSW_L3_MISS_REMOTE_HOP1         BIT_ULL(28)
 942 #define HSW_L3_MISS_REMOTE_HOP2P        BIT_ULL(29)
 943 #define HSW_L3_MISS                     (HSW_L3_MISS_LOCAL_DRAM| \
 944                                          HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
 945                                          HSW_L3_MISS_REMOTE_HOP2P)
 946 #define HSW_SNOOP_NONE                  BIT_ULL(31)
 947 #define HSW_SNOOP_NOT_NEEDED            BIT_ULL(32)
 948 #define HSW_SNOOP_MISS                  BIT_ULL(33)
 949 #define HSW_SNOOP_HIT_NO_FWD            BIT_ULL(34)
 950 #define HSW_SNOOP_HIT_WITH_FWD          BIT_ULL(35)
 951 #define HSW_SNOOP_HITM                  BIT_ULL(36)
 952 #define HSW_SNOOP_NON_DRAM              BIT_ULL(37)
 953 #define HSW_ANY_SNOOP                   (HSW_SNOOP_NONE| \
 954                                          HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
 955                                          HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
 956                                          HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
 957 #define HSW_SNOOP_DRAM                  (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
 958 #define HSW_DEMAND_READ                 HSW_DEMAND_DATA_RD
 959 #define HSW_DEMAND_WRITE                HSW_DEMAND_RFO
 960 #define HSW_L3_MISS_REMOTE              (HSW_L3_MISS_REMOTE_HOP0|\
 961                                          HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
 962 #define HSW_LLC_ACCESS                  HSW_ANY_RESPONSE
 963
 964 #define BDW_L3_MISS_LOCAL               BIT(26)
 965 #define BDW_L3_MISS                     (BDW_L3_MISS_LOCAL| \
 966                                          HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
 967                                          HSW_L3_MISS_REMOTE_HOP2P)
 968
 969
 970 static __initconst const u64 hsw_hw_cache_event_ids
 971                                 [PERF_COUNT_HW_CACHE_MAX]
 972                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 973                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 974 {
 975  [ C(L1D ) ] = {
 976         [ C(OP_READ) ] = {
 977                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
 978                 [ C(RESULT_MISS)   ] = 0x151,   /* L1D.REPLACEMENT */
 979         },
 980         [ C(OP_WRITE) ] = {
 981                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
 982                 [ C(RESULT_MISS)   ] = 0x0,
 983         },
 984         [ C(OP_PREFETCH) ] = {
 985                 [ C(RESULT_ACCESS) ] = 0x0,
 986                 [ C(RESULT_MISS)   ] = 0x0,
 987         },
 988  },
 989  [ C(L1I ) ] = {
 990         [ C(OP_READ) ] = {
 991                 [ C(RESULT_ACCESS) ] = 0x0,
 992                 [ C(RESULT_MISS)   ] = 0x280,   /* ICACHE.MISSES */
 993         },
 994         [ C(OP_WRITE) ] = {
 995                 [ C(RESULT_ACCESS) ] = -1,
 996                 [ C(RESULT_MISS)   ] = -1,
 997         },
 998         [ C(OP_PREFETCH) ] = {
 999                 [ C(RESULT_ACCESS) ] = 0x0,
1000                 [ C(RESULT_MISS)   ] = 0x0,
1001         },
1002  },
1003  [ C(LL  ) ] = {
1004         [ C(OP_READ) ] = {
1005                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
1006                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
1007         },
1008         [ C(OP_WRITE) ] = {
1009                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
1010                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
1011         },
1012         [ C(OP_PREFETCH) ] = {
1013                 [ C(RESULT_ACCESS) ] = 0x0,
1014                 [ C(RESULT_MISS)   ] = 0x0,
1015         },
1016  },
1017  [ C(DTLB) ] = {
1018         [ C(OP_READ) ] = {
1019                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
1020                 [ C(RESULT_MISS)   ] = 0x108,   /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1021         },
1022         [ C(OP_WRITE) ] = {
1023                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
1024                 [ C(RESULT_MISS)   ] = 0x149,   /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1025         },
1026         [ C(OP_PREFETCH) ] = {
1027                 [ C(RESULT_ACCESS) ] = 0x0,
1028                 [ C(RESULT_MISS)   ] = 0x0,
1029         },
1030  },
1031  [ C(ITLB) ] = {
1032         [ C(OP_READ) ] = {
1033                 [ C(RESULT_ACCESS) ] = 0x6085,  /* ITLB_MISSES.STLB_HIT */
1034                 [ C(RESULT_MISS)   ] = 0x185,   /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1035         },
1036         [ C(OP_WRITE) ] = {
1037                 [ C(RESULT_ACCESS) ] = -1,
1038                 [ C(RESULT_MISS)   ] = -1,
1039         },
1040         [ C(OP_PREFETCH) ] = {
1041                 [ C(RESULT_ACCESS) ] = -1,
1042                 [ C(RESULT_MISS)   ] = -1,
1043         },
1044  },
1045  [ C(BPU ) ] = {
1046         [ C(OP_READ) ] = {
1047                 [ C(RESULT_ACCESS) ] = 0xc4,    /* BR_INST_RETIRED.ALL_BRANCHES */
1048                 [ C(RESULT_MISS)   ] = 0xc5,    /* BR_MISP_RETIRED.ALL_BRANCHES */
1049         },
1050         [ C(OP_WRITE) ] = {
1051                 [ C(RESULT_ACCESS) ] = -1,
1052                 [ C(RESULT_MISS)   ] = -1,
1053         },
1054         [ C(OP_PREFETCH) ] = {
1055                 [ C(RESULT_ACCESS) ] = -1,
1056                 [ C(RESULT_MISS)   ] = -1,
1057         },
1058  },
1059  [ C(NODE) ] = {
1060         [ C(OP_READ) ] = {
1061                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
1062                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
1063         },
1064         [ C(OP_WRITE) ] = {
1065                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
1066                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
1067         },
1068         [ C(OP_PREFETCH) ] = {
1069                 [ C(RESULT_ACCESS) ] = 0x0,
1070                 [ C(RESULT_MISS)   ] = 0x0,
1071         },
1072  },
1073 };
1074
1075 static __initconst const u64 hsw_hw_cache_extra_regs
1076                                 [PERF_COUNT_HW_CACHE_MAX]
1077                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1078                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1079 {
1080  [ C(LL  ) ] = {
1081         [ C(OP_READ) ] = {
1082                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1083                                        HSW_LLC_ACCESS,
1084                 [ C(RESULT_MISS)   ] = HSW_DEMAND_READ|
1085                                        HSW_L3_MISS|HSW_ANY_SNOOP,
1086         },
1087         [ C(OP_WRITE) ] = {
1088                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1089                                        HSW_LLC_ACCESS,
1090                 [ C(RESULT_MISS)   ] = HSW_DEMAND_WRITE|
1091                                        HSW_L3_MISS|HSW_ANY_SNOOP,
1092         },
1093         [ C(OP_PREFETCH) ] = {
1094                 [ C(RESULT_ACCESS) ] = 0x0,
1095                 [ C(RESULT_MISS)   ] = 0x0,
1096         },
1097  },
1098  [ C(NODE) ] = {
1099         [ C(OP_READ) ] = {
1100                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1101                                        HSW_L3_MISS_LOCAL_DRAM|
1102                                        HSW_SNOOP_DRAM,
1103                 [ C(RESULT_MISS)   ] = HSW_DEMAND_READ|
1104                                        HSW_L3_MISS_REMOTE|
1105                                        HSW_SNOOP_DRAM,
1106         },
1107         [ C(OP_WRITE) ] = {
1108                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1109                                        HSW_L3_MISS_LOCAL_DRAM|
1110                                        HSW_SNOOP_DRAM,
1111                 [ C(RESULT_MISS)   ] = HSW_DEMAND_WRITE|
1112                                        HSW_L3_MISS_REMOTE|
1113                                        HSW_SNOOP_DRAM,
1114         },
1115         [ C(OP_PREFETCH) ] = {
1116                 [ C(RESULT_ACCESS) ] = 0x0,
1117                 [ C(RESULT_MISS)   ] = 0x0,
1118         },
1119  },
1120 };
1121
1122 static __initconst const u64 westmere_hw_cache_event_ids
1123                                 [PERF_COUNT_HW_CACHE_MAX]
1124                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1125                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1126 {
1127  [ C(L1D) ] = {
1128         [ C(OP_READ) ] = {
1129                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
1130                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
1131         },
1132         [ C(OP_WRITE) ] = {
1133                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
1134                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
1135         },
1136         [ C(OP_PREFETCH) ] = {
1137                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
1138                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
1139         },
1140  },
1141  [ C(L1I ) ] = {
1142         [ C(OP_READ) ] = {
1143                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
1144                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
1145         },
1146         [ C(OP_WRITE) ] = {
1147                 [ C(RESULT_ACCESS) ] = -1,
1148                 [ C(RESULT_MISS)   ] = -1,
1149         },
1150         [ C(OP_PREFETCH) ] = {
1151                 [ C(RESULT_ACCESS) ] = 0x0,
1152                 [ C(RESULT_MISS)   ] = 0x0,
1153         },
1154  },
1155  [ C(LL  ) ] = {
1156         [ C(OP_READ) ] = {
1157                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1158                 [ C(RESULT_ACCESS) ] = 0x01b7,
1159                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1160                 [ C(RESULT_MISS)   ] = 0x01b7,
1161         },
1162         /*
1163          * Use RFO, not WRITEBACK, because a write miss would typically occur
1164          * on RFO.
1165          */
1166         [ C(OP_WRITE) ] = {
1167                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1168                 [ C(RESULT_ACCESS) ] = 0x01b7,
1169                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1170                 [ C(RESULT_MISS)   ] = 0x01b7,
1171         },
1172         [ C(OP_PREFETCH) ] = {
1173                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1174                 [ C(RESULT_ACCESS) ] = 0x01b7,
1175                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1176                 [ C(RESULT_MISS)   ] = 0x01b7,
1177         },
1178  },
1179  [ C(DTLB) ] = {
1180         [ C(OP_READ) ] = {
1181                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
1182                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
1183         },
1184         [ C(OP_WRITE) ] = {
1185                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
1186                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
1187         },
1188         [ C(OP_PREFETCH) ] = {
1189                 [ C(RESULT_ACCESS) ] = 0x0,
1190                 [ C(RESULT_MISS)   ] = 0x0,
1191         },
1192  },
1193  [ C(ITLB) ] = {
1194         [ C(OP_READ) ] = {
1195                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
1196                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.ANY              */
1197         },
1198         [ C(OP_WRITE) ] = {
1199                 [ C(RESULT_ACCESS) ] = -1,
1200                 [ C(RESULT_MISS)   ] = -1,
1201         },
1202         [ C(OP_PREFETCH) ] = {
1203                 [ C(RESULT_ACCESS) ] = -1,
1204                 [ C(RESULT_MISS)   ] = -1,
1205         },
1206  },
1207  [ C(BPU ) ] = {
1208         [ C(OP_READ) ] = {
1209                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1210                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
1211         },
1212         [ C(OP_WRITE) ] = {
1213                 [ C(RESULT_ACCESS) ] = -1,
1214                 [ C(RESULT_MISS)   ] = -1,
1215         },
1216         [ C(OP_PREFETCH) ] = {
1217                 [ C(RESULT_ACCESS) ] = -1,
1218                 [ C(RESULT_MISS)   ] = -1,
1219         },
1220  },
1221  [ C(NODE) ] = {
1222         [ C(OP_READ) ] = {
1223                 [ C(RESULT_ACCESS) ] = 0x01b7,
1224                 [ C(RESULT_MISS)   ] = 0x01b7,
1225         },
1226         [ C(OP_WRITE) ] = {
1227                 [ C(RESULT_ACCESS) ] = 0x01b7,
1228                 [ C(RESULT_MISS)   ] = 0x01b7,
1229         },
1230         [ C(OP_PREFETCH) ] = {
1231                 [ C(RESULT_ACCESS) ] = 0x01b7,
1232                 [ C(RESULT_MISS)   ] = 0x01b7,
1233         },
1234  },
1235 };
1236
1237 /*
1238  * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1239  * See IA32 SDM Vol 3B 30.6.1.3
1240  */
1241
1242 #define NHM_DMND_DATA_RD        (1 << 0)
1243 #define NHM_DMND_RFO            (1 << 1)
1244 #define NHM_DMND_IFETCH         (1 << 2)
1245 #define NHM_DMND_WB             (1 << 3)
1246 #define NHM_PF_DATA_RD          (1 << 4)
1247 #define NHM_PF_DATA_RFO         (1 << 5)
1248 #define NHM_PF_IFETCH           (1 << 6)
1249 #define NHM_OFFCORE_OTHER       (1 << 7)
1250 #define NHM_UNCORE_HIT          (1 << 8)
1251 #define NHM_OTHER_CORE_HIT_SNP  (1 << 9)
1252 #define NHM_OTHER_CORE_HITM     (1 << 10)
1253                                 /* reserved */
1254 #define NHM_REMOTE_CACHE_FWD    (1 << 12)
1255 #define NHM_REMOTE_DRAM         (1 << 13)
1256 #define NHM_LOCAL_DRAM          (1 << 14)
1257 #define NHM_NON_DRAM            (1 << 15)
1258
1259 #define NHM_LOCAL               (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1260 #define NHM_REMOTE              (NHM_REMOTE_DRAM)
1261
1262 #define NHM_DMND_READ           (NHM_DMND_DATA_RD)
1263 #define NHM_DMND_WRITE          (NHM_DMND_RFO|NHM_DMND_WB)
1264 #define NHM_DMND_PREFETCH       (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1265
1266 #define NHM_L3_HIT      (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1267 #define NHM_L3_MISS     (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1268 #define NHM_L3_ACCESS   (NHM_L3_HIT|NHM_L3_MISS)
1269
1270 static __initconst const u64 nehalem_hw_cache_extra_regs
1271                                 [PERF_COUNT_HW_CACHE_MAX]
1272                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1273                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1274 {
1275  [ C(LL  ) ] = {
1276         [ C(OP_READ) ] = {
1277                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1278                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_L3_MISS,
1279         },
1280         [ C(OP_WRITE) ] = {
1281                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1282                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_L3_MISS,
1283         },
1284         [ C(OP_PREFETCH) ] = {
1285                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1286                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1287         },
1288  },
1289  [ C(NODE) ] = {
1290         [ C(OP_READ) ] = {
1291                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1292                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_REMOTE,
1293         },
1294         [ C(OP_WRITE) ] = {
1295                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1296                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_REMOTE,
1297         },
1298         [ C(OP_PREFETCH) ] = {
1299                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1300                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1301         },
1302  },
1303 };
1304
1305 static __initconst const u64 nehalem_hw_cache_event_ids
1306                                 [PERF_COUNT_HW_CACHE_MAX]
1307                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1308                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1309 {
1310  [ C(L1D) ] = {
1311         [ C(OP_READ) ] = {
1312                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
1313                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
1314         },
1315         [ C(OP_WRITE) ] = {
1316                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
1317                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
1318         },
1319         [ C(OP_PREFETCH) ] = {
1320                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
1321                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
1322         },
1323  },
1324  [ C(L1I ) ] = {
1325         [ C(OP_READ) ] = {
1326                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
1327                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
1328         },
1329         [ C(OP_WRITE) ] = {
1330                 [ C(RESULT_ACCESS) ] = -1,
1331                 [ C(RESULT_MISS)   ] = -1,
1332         },
1333         [ C(OP_PREFETCH) ] = {
1334                 [ C(RESULT_ACCESS) ] = 0x0,
1335                 [ C(RESULT_MISS)   ] = 0x0,
1336         },
1337  },
1338  [ C(LL  ) ] = {
1339         [ C(OP_READ) ] = {
1340                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1341                 [ C(RESULT_ACCESS) ] = 0x01b7,
1342                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1343                 [ C(RESULT_MISS)   ] = 0x01b7,
1344         },
1345         /*
1346          * Use RFO, not WRITEBACK, because a write miss would typically occur
1347          * on RFO.
1348          */
1349         [ C(OP_WRITE) ] = {
1350                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1351                 [ C(RESULT_ACCESS) ] = 0x01b7,
1352                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1353                 [ C(RESULT_MISS)   ] = 0x01b7,
1354         },
1355         [ C(OP_PREFETCH) ] = {
1356                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1357                 [ C(RESULT_ACCESS) ] = 0x01b7,
1358                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1359                 [ C(RESULT_MISS)   ] = 0x01b7,
1360         },
1361  },
1362  [ C(DTLB) ] = {
1363         [ C(OP_READ) ] = {
1364                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
1365                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
1366         },
1367         [ C(OP_WRITE) ] = {
1368                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
1369                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
1370         },
1371         [ C(OP_PREFETCH) ] = {
1372                 [ C(RESULT_ACCESS) ] = 0x0,
1373                 [ C(RESULT_MISS)   ] = 0x0,
1374         },
1375  },
1376  [ C(ITLB) ] = {
1377         [ C(OP_READ) ] = {
1378                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
1379                 [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
1380         },
1381         [ C(OP_WRITE) ] = {
1382                 [ C(RESULT_ACCESS) ] = -1,
1383                 [ C(RESULT_MISS)   ] = -1,
1384         },
1385         [ C(OP_PREFETCH) ] = {
1386                 [ C(RESULT_ACCESS) ] = -1,
1387                 [ C(RESULT_MISS)   ] = -1,
1388         },
1389  },
1390  [ C(BPU ) ] = {
1391         [ C(OP_READ) ] = {
1392                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1393                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
1394         },
1395         [ C(OP_WRITE) ] = {
1396                 [ C(RESULT_ACCESS) ] = -1,
1397                 [ C(RESULT_MISS)   ] = -1,
1398         },
1399         [ C(OP_PREFETCH) ] = {
1400                 [ C(RESULT_ACCESS) ] = -1,
1401                 [ C(RESULT_MISS)   ] = -1,
1402         },
1403  },
1404  [ C(NODE) ] = {
1405         [ C(OP_READ) ] = {
1406                 [ C(RESULT_ACCESS) ] = 0x01b7,
1407                 [ C(RESULT_MISS)   ] = 0x01b7,
1408         },
1409         [ C(OP_WRITE) ] = {
1410                 [ C(RESULT_ACCESS) ] = 0x01b7,
1411                 [ C(RESULT_MISS)   ] = 0x01b7,
1412         },
1413         [ C(OP_PREFETCH) ] = {
1414                 [ C(RESULT_ACCESS) ] = 0x01b7,
1415                 [ C(RESULT_MISS)   ] = 0x01b7,
1416         },
1417  },
1418 };
1419
1420 static __initconst const u64 core2_hw_cache_event_ids
1421                                 [PERF_COUNT_HW_CACHE_MAX]
1422                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1423                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1424 {
1425  [ C(L1D) ] = {
1426         [ C(OP_READ) ] = {
1427                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
1428                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
1429         },
1430         [ C(OP_WRITE) ] = {
1431                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
1432                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
1433         },
1434         [ C(OP_PREFETCH) ] = {
1435                 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
1436                 [ C(RESULT_MISS)   ] = 0,
1437         },
1438  },
1439  [ C(L1I ) ] = {
1440         [ C(OP_READ) ] = {
1441                 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
1442                 [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
1443         },
1444         [ C(OP_WRITE) ] = {
1445                 [ C(RESULT_ACCESS) ] = -1,
1446                 [ C(RESULT_MISS)   ] = -1,
1447         },
1448         [ C(OP_PREFETCH) ] = {
1449                 [ C(RESULT_ACCESS) ] = 0,
1450                 [ C(RESULT_MISS)   ] = 0,
1451         },
1452  },
1453  [ C(LL  ) ] = {
1454         [ C(OP_READ) ] = {
1455                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
1456                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
1457         },
1458         [ C(OP_WRITE) ] = {
1459                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
1460                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
1461         },
1462         [ C(OP_PREFETCH) ] = {
1463                 [ C(RESULT_ACCESS) ] = 0,
1464                 [ C(RESULT_MISS)   ] = 0,
1465         },
1466  },
1467  [ C(DTLB) ] = {
1468         [ C(OP_READ) ] = {
1469                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
1470                 [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
1471         },
1472         [ C(OP_WRITE) ] = {
1473                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
1474                 [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
1475         },
1476         [ C(OP_PREFETCH) ] = {
1477                 [ C(RESULT_ACCESS) ] = 0,
1478                 [ C(RESULT_MISS)   ] = 0,
1479         },
1480  },
1481  [ C(ITLB) ] = {
1482         [ C(OP_READ) ] = {
1483                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
1484                 [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
1485         },
1486         [ C(OP_WRITE) ] = {
1487                 [ C(RESULT_ACCESS) ] = -1,
1488                 [ C(RESULT_MISS)   ] = -1,
1489         },
1490         [ C(OP_PREFETCH) ] = {
1491                 [ C(RESULT_ACCESS) ] = -1,
1492                 [ C(RESULT_MISS)   ] = -1,
1493         },
1494  },
1495  [ C(BPU ) ] = {
1496         [ C(OP_READ) ] = {
1497                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
1498                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
1499         },
1500         [ C(OP_WRITE) ] = {
1501                 [ C(RESULT_ACCESS) ] = -1,
1502                 [ C(RESULT_MISS)   ] = -1,
1503         },
1504         [ C(OP_PREFETCH) ] = {
1505                 [ C(RESULT_ACCESS) ] = -1,
1506                 [ C(RESULT_MISS)   ] = -1,
1507         },
1508  },
1509 };
1510
1511 static __initconst const u64 atom_hw_cache_event_ids
1512                                 [PERF_COUNT_HW_CACHE_MAX]
1513                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1514                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1515 {
1516  [ C(L1D) ] = {
1517         [ C(OP_READ) ] = {
1518                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
1519                 [ C(RESULT_MISS)   ] = 0,
1520         },
1521         [ C(OP_WRITE) ] = {
1522                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
1523                 [ C(RESULT_MISS)   ] = 0,
1524         },
1525         [ C(OP_PREFETCH) ] = {
1526                 [ C(RESULT_ACCESS) ] = 0x0,
1527                 [ C(RESULT_MISS)   ] = 0,
1528         },
1529  },
1530  [ C(L1I ) ] = {
1531         [ C(OP_READ) ] = {
1532                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
1533                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
1534         },
1535         [ C(OP_WRITE) ] = {
1536                 [ C(RESULT_ACCESS) ] = -1,
1537                 [ C(RESULT_MISS)   ] = -1,
1538         },
1539         [ C(OP_PREFETCH) ] = {
1540                 [ C(RESULT_ACCESS) ] = 0,
1541                 [ C(RESULT_MISS)   ] = 0,
1542         },
1543  },
1544  [ C(LL  ) ] = {
1545         [ C(OP_READ) ] = {
1546                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
1547                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
1548         },
1549         [ C(OP_WRITE) ] = {
1550                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
1551                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
1552         },
1553         [ C(OP_PREFETCH) ] = {
1554                 [ C(RESULT_ACCESS) ] = 0,
1555                 [ C(RESULT_MISS)   ] = 0,
1556         },
1557  },
1558  [ C(DTLB) ] = {
1559         [ C(OP_READ) ] = {
1560                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
1561                 [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
1562         },
1563         [ C(OP_WRITE) ] = {
1564                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
1565                 [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
1566         },
1567         [ C(OP_PREFETCH) ] = {
1568                 [ C(RESULT_ACCESS) ] = 0,
1569                 [ C(RESULT_MISS)   ] = 0,
1570         },
1571  },
1572  [ C(ITLB) ] = {
1573         [ C(OP_READ) ] = {
1574                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
1575                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
1576         },
1577         [ C(OP_WRITE) ] = {
1578                 [ C(RESULT_ACCESS) ] = -1,
1579                 [ C(RESULT_MISS)   ] = -1,
1580         },
1581         [ C(OP_PREFETCH) ] = {
1582                 [ C(RESULT_ACCESS) ] = -1,
1583                 [ C(RESULT_MISS)   ] = -1,
1584         },
1585  },
1586  [ C(BPU ) ] = {
1587         [ C(OP_READ) ] = {
1588                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
1589                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
1590         },
1591         [ C(OP_WRITE) ] = {
1592                 [ C(RESULT_ACCESS) ] = -1,
1593                 [ C(RESULT_MISS)   ] = -1,
1594         },
1595         [ C(OP_PREFETCH) ] = {
1596                 [ C(RESULT_ACCESS) ] = -1,
1597                 [ C(RESULT_MISS)   ] = -1,
1598         },
1599  },
1600 };
1601
1602 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1603 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1604 /* no_alloc_cycles.not_delivered */
1605 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1606                "event=0xca,umask=0x50");
1607 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1608 /* uops_retired.all */
1609 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1610                "event=0xc2,umask=0x10");
1611 /* uops_retired.all */
1612 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1613                "event=0xc2,umask=0x10");
1614
1615 static struct attribute *slm_events_attrs[] = {
1616         EVENT_PTR(td_total_slots_slm),
1617         EVENT_PTR(td_total_slots_scale_slm),
1618         EVENT_PTR(td_fetch_bubbles_slm),
1619         EVENT_PTR(td_fetch_bubbles_scale_slm),
1620         EVENT_PTR(td_slots_issued_slm),
1621         EVENT_PTR(td_slots_retired_slm),
1622         NULL
1623 };
1624
1625 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1626 {
1627         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1628         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1629         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1630         EVENT_EXTRA_END
1631 };
1632
1633 #define SLM_DMND_READ           SNB_DMND_DATA_RD
1634 #define SLM_DMND_WRITE          SNB_DMND_RFO
1635 #define SLM_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
1636
1637 #define SLM_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1638 #define SLM_LLC_ACCESS          SNB_RESP_ANY
1639 #define SLM_LLC_MISS            (SLM_SNP_ANY|SNB_NON_DRAM)
1640
1641 static __initconst const u64 slm_hw_cache_extra_regs
1642                                 [PERF_COUNT_HW_CACHE_MAX]
1643                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1644                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1645 {
1646  [ C(LL  ) ] = {
1647         [ C(OP_READ) ] = {
1648                 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1649                 [ C(RESULT_MISS)   ] = 0,
1650         },
1651         [ C(OP_WRITE) ] = {
1652                 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1653                 [ C(RESULT_MISS)   ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1654         },
1655         [ C(OP_PREFETCH) ] = {
1656                 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1657                 [ C(RESULT_MISS)   ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1658         },
1659  },
1660 };
1661
1662 static __initconst const u64 slm_hw_cache_event_ids
1663                                 [PERF_COUNT_HW_CACHE_MAX]
1664                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1665                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1666 {
1667  [ C(L1D) ] = {
1668         [ C(OP_READ) ] = {
1669                 [ C(RESULT_ACCESS) ] = 0,
1670                 [ C(RESULT_MISS)   ] = 0x0104, /* LD_DCU_MISS */
1671         },
1672         [ C(OP_WRITE) ] = {
1673                 [ C(RESULT_ACCESS) ] = 0,
1674                 [ C(RESULT_MISS)   ] = 0,
1675         },
1676         [ C(OP_PREFETCH) ] = {
1677                 [ C(RESULT_ACCESS) ] = 0,
1678                 [ C(RESULT_MISS)   ] = 0,
1679         },
1680  },
1681  [ C(L1I ) ] = {
1682         [ C(OP_READ) ] = {
1683                 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1684                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACGE.MISSES */
1685         },
1686         [ C(OP_WRITE) ] = {
1687                 [ C(RESULT_ACCESS) ] = -1,
1688                 [ C(RESULT_MISS)   ] = -1,
1689         },
1690         [ C(OP_PREFETCH) ] = {
1691                 [ C(RESULT_ACCESS) ] = 0,
1692                 [ C(RESULT_MISS)   ] = 0,
1693         },
1694  },
1695  [ C(LL  ) ] = {
1696         [ C(OP_READ) ] = {
1697                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1698                 [ C(RESULT_ACCESS) ] = 0x01b7,
1699                 [ C(RESULT_MISS)   ] = 0,
1700         },
1701         [ C(OP_WRITE) ] = {
1702                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1703                 [ C(RESULT_ACCESS) ] = 0x01b7,
1704                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1705                 [ C(RESULT_MISS)   ] = 0x01b7,
1706         },
1707         [ C(OP_PREFETCH) ] = {
1708                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1709                 [ C(RESULT_ACCESS) ] = 0x01b7,
1710                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1711                 [ C(RESULT_MISS)   ] = 0x01b7,
1712         },
1713  },
1714  [ C(DTLB) ] = {
1715         [ C(OP_READ) ] = {
1716                 [ C(RESULT_ACCESS) ] = 0,
1717                 [ C(RESULT_MISS)   ] = 0x0804, /* LD_DTLB_MISS */
1718         },
1719         [ C(OP_WRITE) ] = {
1720                 [ C(RESULT_ACCESS) ] = 0,
1721                 [ C(RESULT_MISS)   ] = 0,
1722         },
1723         [ C(OP_PREFETCH) ] = {
1724                 [ C(RESULT_ACCESS) ] = 0,
1725                 [ C(RESULT_MISS)   ] = 0,
1726         },
1727  },
1728  [ C(ITLB) ] = {
1729         [ C(OP_READ) ] = {
1730                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1731                 [ C(RESULT_MISS)   ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1732         },
1733         [ C(OP_WRITE) ] = {
1734                 [ C(RESULT_ACCESS) ] = -1,
1735                 [ C(RESULT_MISS)   ] = -1,
1736         },
1737         [ C(OP_PREFETCH) ] = {
1738                 [ C(RESULT_ACCESS) ] = -1,
1739                 [ C(RESULT_MISS)   ] = -1,
1740         },
1741  },
1742  [ C(BPU ) ] = {
1743         [ C(OP_READ) ] = {
1744                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1745                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1746         },
1747         [ C(OP_WRITE) ] = {
1748                 [ C(RESULT_ACCESS) ] = -1,
1749                 [ C(RESULT_MISS)   ] = -1,
1750         },
1751         [ C(OP_PREFETCH) ] = {
1752                 [ C(RESULT_ACCESS) ] = -1,
1753                 [ C(RESULT_MISS)   ] = -1,
1754         },
1755  },
1756 };
1757
1758 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1759 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1760 /* UOPS_NOT_DELIVERED.ANY */
1761 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1762 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1763 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1764 /* UOPS_RETIRED.ANY */
1765 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1766 /* UOPS_ISSUED.ANY */
1767 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1768
1769 static struct attribute *glm_events_attrs[] = {
1770         EVENT_PTR(td_total_slots_glm),
1771         EVENT_PTR(td_total_slots_scale_glm),
1772         EVENT_PTR(td_fetch_bubbles_glm),
1773         EVENT_PTR(td_recovery_bubbles_glm),
1774         EVENT_PTR(td_slots_issued_glm),
1775         EVENT_PTR(td_slots_retired_glm),
1776         NULL
1777 };
1778
1779 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1780         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1781         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1782         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1783         EVENT_EXTRA_END
1784 };
1785
1786 #define GLM_DEMAND_DATA_RD              BIT_ULL(0)
1787 #define GLM_DEMAND_RFO                  BIT_ULL(1)
1788 #define GLM_ANY_RESPONSE                BIT_ULL(16)
1789 #define GLM_SNP_NONE_OR_MISS            BIT_ULL(33)
1790 #define GLM_DEMAND_READ                 GLM_DEMAND_DATA_RD
1791 #define GLM_DEMAND_WRITE                GLM_DEMAND_RFO
1792 #define GLM_DEMAND_PREFETCH             (SNB_PF_DATA_RD|SNB_PF_RFO)
1793 #define GLM_LLC_ACCESS                  GLM_ANY_RESPONSE
1794 #define GLM_SNP_ANY                     (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1795 #define GLM_LLC_MISS                    (GLM_SNP_ANY|SNB_NON_DRAM)
1796
1797 static __initconst const u64 glm_hw_cache_event_ids
1798                                 [PERF_COUNT_HW_CACHE_MAX]
1799                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1800                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1801         [C(L1D)] = {
1802                 [C(OP_READ)] = {
1803                         [C(RESULT_ACCESS)]      = 0x81d0,       /* MEM_UOPS_RETIRED.ALL_LOADS */
1804                         [C(RESULT_MISS)]        = 0x0,
1805                 },
1806                 [C(OP_WRITE)] = {
1807                         [C(RESULT_ACCESS)]      = 0x82d0,       /* MEM_UOPS_RETIRED.ALL_STORES */
1808                         [C(RESULT_MISS)]        = 0x0,
1809                 },
1810                 [C(OP_PREFETCH)] = {
1811                         [C(RESULT_ACCESS)]      = 0x0,
1812                         [C(RESULT_MISS)]        = 0x0,
1813                 },
1814         },
1815         [C(L1I)] = {
1816                 [C(OP_READ)] = {
1817                         [C(RESULT_ACCESS)]      = 0x0380,       /* ICACHE.ACCESSES */
1818                         [C(RESULT_MISS)]        = 0x0280,       /* ICACHE.MISSES */
1819                 },
1820                 [C(OP_WRITE)] = {
1821                         [C(RESULT_ACCESS)]      = -1,
1822                         [C(RESULT_MISS)]        = -1,
1823                 },
1824                 [C(OP_PREFETCH)] = {
1825                         [C(RESULT_ACCESS)]      = 0x0,
1826                         [C(RESULT_MISS)]        = 0x0,
1827                 },
1828         },
1829         [C(LL)] = {
1830                 [C(OP_READ)] = {
1831                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1832                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1833                 },
1834                 [C(OP_WRITE)] = {
1835                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1836                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1837                 },
1838                 [C(OP_PREFETCH)] = {
1839                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1840                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1841                 },
1842         },
1843         [C(DTLB)] = {
1844                 [C(OP_READ)] = {
1845                         [C(RESULT_ACCESS)]      = 0x81d0,       /* MEM_UOPS_RETIRED.ALL_LOADS */
1846                         [C(RESULT_MISS)]        = 0x0,
1847                 },
1848                 [C(OP_WRITE)] = {
1849                         [C(RESULT_ACCESS)]      = 0x82d0,       /* MEM_UOPS_RETIRED.ALL_STORES */
1850                         [C(RESULT_MISS)]        = 0x0,
1851                 },
1852                 [C(OP_PREFETCH)] = {
1853                         [C(RESULT_ACCESS)]      = 0x0,
1854                         [C(RESULT_MISS)]        = 0x0,
1855                 },
1856         },
1857         [C(ITLB)] = {
1858                 [C(OP_READ)] = {
1859                         [C(RESULT_ACCESS)]      = 0x00c0,       /* INST_RETIRED.ANY_P */
1860                         [C(RESULT_MISS)]        = 0x0481,       /* ITLB.MISS */
1861                 },
1862                 [C(OP_WRITE)] = {
1863                         [C(RESULT_ACCESS)]      = -1,
1864                         [C(RESULT_MISS)]        = -1,
1865                 },
1866                 [C(OP_PREFETCH)] = {
1867                         [C(RESULT_ACCESS)]      = -1,
1868                         [C(RESULT_MISS)]        = -1,
1869                 },
1870         },
1871         [C(BPU)] = {
1872                 [C(OP_READ)] = {
1873                         [C(RESULT_ACCESS)]      = 0x00c4,       /* BR_INST_RETIRED.ALL_BRANCHES */
1874                         [C(RESULT_MISS)]        = 0x00c5,       /* BR_MISP_RETIRED.ALL_BRANCHES */
1875                 },
1876                 [C(OP_WRITE)] = {
1877                         [C(RESULT_ACCESS)]      = -1,
1878                         [C(RESULT_MISS)]        = -1,
1879                 },
1880                 [C(OP_PREFETCH)] = {
1881                         [C(RESULT_ACCESS)]      = -1,
1882                         [C(RESULT_MISS)]        = -1,
1883                 },
1884         },
1885 };
1886
1887 static __initconst const u64 glm_hw_cache_extra_regs
1888                                 [PERF_COUNT_HW_CACHE_MAX]
1889                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1890                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1891         [C(LL)] = {
1892                 [C(OP_READ)] = {
1893                         [C(RESULT_ACCESS)]      = GLM_DEMAND_READ|
1894                                                   GLM_LLC_ACCESS,
1895                         [C(RESULT_MISS)]        = GLM_DEMAND_READ|
1896                                                   GLM_LLC_MISS,
1897                 },
1898                 [C(OP_WRITE)] = {
1899                         [C(RESULT_ACCESS)]      = GLM_DEMAND_WRITE|
1900                                                   GLM_LLC_ACCESS,
1901                         [C(RESULT_MISS)]        = GLM_DEMAND_WRITE|
1902                                                   GLM_LLC_MISS,
1903                 },
1904                 [C(OP_PREFETCH)] = {
1905                         [C(RESULT_ACCESS)]      = GLM_DEMAND_PREFETCH|
1906                                                   GLM_LLC_ACCESS,
1907                         [C(RESULT_MISS)]        = GLM_DEMAND_PREFETCH|
1908                                                   GLM_LLC_MISS,
1909                 },
1910         },
1911 };
1912
1913 static __initconst const u64 glp_hw_cache_event_ids
1914                                 [PERF_COUNT_HW_CACHE_MAX]
1915                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1916                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1917         [C(L1D)] = {
1918                 [C(OP_READ)] = {
1919                         [C(RESULT_ACCESS)]      = 0x81d0,       /* MEM_UOPS_RETIRED.ALL_LOADS */
1920                         [C(RESULT_MISS)]        = 0x0,
1921                 },
1922                 [C(OP_WRITE)] = {
1923                         [C(RESULT_ACCESS)]      = 0x82d0,       /* MEM_UOPS_RETIRED.ALL_STORES */
1924                         [C(RESULT_MISS)]        = 0x0,
1925                 },
1926                 [C(OP_PREFETCH)] = {
1927                         [C(RESULT_ACCESS)]      = 0x0,
1928                         [C(RESULT_MISS)]        = 0x0,
1929                 },
1930         },
1931         [C(L1I)] = {
1932                 [C(OP_READ)] = {
1933                         [C(RESULT_ACCESS)]      = 0x0380,       /* ICACHE.ACCESSES */
1934                         [C(RESULT_MISS)]        = 0x0280,       /* ICACHE.MISSES */
1935                 },
1936                 [C(OP_WRITE)] = {
1937                         [C(RESULT_ACCESS)]      = -1,
1938                         [C(RESULT_MISS)]        = -1,
1939                 },
1940                 [C(OP_PREFETCH)] = {
1941                         [C(RESULT_ACCESS)]      = 0x0,
1942                         [C(RESULT_MISS)]        = 0x0,
1943                 },
1944         },
1945         [C(LL)] = {
1946                 [C(OP_READ)] = {
1947                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1948                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1949                 },
1950                 [C(OP_WRITE)] = {
1951                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1952                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1953                 },
1954                 [C(OP_PREFETCH)] = {
1955                         [C(RESULT_ACCESS)]      = 0x0,
1956                         [C(RESULT_MISS)]        = 0x0,
1957                 },
1958         },
1959         [C(DTLB)] = {
1960                 [C(OP_READ)] = {
1961                         [C(RESULT_ACCESS)]      = 0x81d0,       /* MEM_UOPS_RETIRED.ALL_LOADS */
1962                         [C(RESULT_MISS)]        = 0xe08,        /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1963                 },
1964                 [C(OP_WRITE)] = {
1965                         [C(RESULT_ACCESS)]      = 0x82d0,       /* MEM_UOPS_RETIRED.ALL_STORES */
1966                         [C(RESULT_MISS)]        = 0xe49,        /* DTLB_STORE_MISSES.WALK_COMPLETED */
1967                 },
1968                 [C(OP_PREFETCH)] = {
1969                         [C(RESULT_ACCESS)]      = 0x0,
1970                         [C(RESULT_MISS)]        = 0x0,
1971                 },
1972         },
1973         [C(ITLB)] = {
1974                 [C(OP_READ)] = {
1975                         [C(RESULT_ACCESS)]      = 0x00c0,       /* INST_RETIRED.ANY_P */
1976                         [C(RESULT_MISS)]        = 0x0481,       /* ITLB.MISS */
1977                 },
1978                 [C(OP_WRITE)] = {
1979                         [C(RESULT_ACCESS)]      = -1,
1980                         [C(RESULT_MISS)]        = -1,
1981                 },
1982                 [C(OP_PREFETCH)] = {
1983                         [C(RESULT_ACCESS)]      = -1,
1984                         [C(RESULT_MISS)]        = -1,
1985                 },
1986         },
1987         [C(BPU)] = {
1988                 [C(OP_READ)] = {
1989                         [C(RESULT_ACCESS)]      = 0x00c4,       /* BR_INST_RETIRED.ALL_BRANCHES */
1990                         [C(RESULT_MISS)]        = 0x00c5,       /* BR_MISP_RETIRED.ALL_BRANCHES */
1991                 },
1992                 [C(OP_WRITE)] = {
1993                         [C(RESULT_ACCESS)]      = -1,
1994                         [C(RESULT_MISS)]        = -1,
1995                 },
1996                 [C(OP_PREFETCH)] = {
1997                         [C(RESULT_ACCESS)]      = -1,
1998                         [C(RESULT_MISS)]        = -1,
1999                 },
2000         },
2001 };
2002
2003 static __initconst const u64 glp_hw_cache_extra_regs
2004                                 [PERF_COUNT_HW_CACHE_MAX]
2005                                 [PERF_COUNT_HW_CACHE_OP_MAX]
2006                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2007         [C(LL)] = {
2008                 [C(OP_READ)] = {
2009                         [C(RESULT_ACCESS)]      = GLM_DEMAND_READ|
2010                                                   GLM_LLC_ACCESS,
2011                         [C(RESULT_MISS)]        = GLM_DEMAND_READ|
2012                                                   GLM_LLC_MISS,
2013                 },
2014                 [C(OP_WRITE)] = {
2015                         [C(RESULT_ACCESS)]      = GLM_DEMAND_WRITE|
2016                                                   GLM_LLC_ACCESS,
2017                         [C(RESULT_MISS)]        = GLM_DEMAND_WRITE|
2018                                                   GLM_LLC_MISS,
2019                 },
2020                 [C(OP_PREFETCH)] = {
2021                         [C(RESULT_ACCESS)]      = 0x0,
2022                         [C(RESULT_MISS)]        = 0x0,
2023                 },
2024         },
2025 };
2026
2027 #define TNT_LOCAL_DRAM                  BIT_ULL(26)
2028 #define TNT_DEMAND_READ                 GLM_DEMAND_DATA_RD
2029 #define TNT_DEMAND_WRITE                GLM_DEMAND_RFO
2030 #define TNT_LLC_ACCESS                  GLM_ANY_RESPONSE
2031 #define TNT_SNP_ANY                     (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
2032                                          SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
2033 #define TNT_LLC_MISS                    (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
2034
2035 static __initconst const u64 tnt_hw_cache_extra_regs
2036                                 [PERF_COUNT_HW_CACHE_MAX]
2037                                 [PERF_COUNT_HW_CACHE_OP_MAX]
2038                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2039         [C(LL)] = {
2040                 [C(OP_READ)] = {
2041                         [C(RESULT_ACCESS)]      = TNT_DEMAND_READ|
2042                                                   TNT_LLC_ACCESS,
2043                         [C(RESULT_MISS)]        = TNT_DEMAND_READ|
2044                                                   TNT_LLC_MISS,
2045                 },
2046                 [C(OP_WRITE)] = {
2047                         [C(RESULT_ACCESS)]      = TNT_DEMAND_WRITE|
2048                                                   TNT_LLC_ACCESS,
2049                         [C(RESULT_MISS)]        = TNT_DEMAND_WRITE|
2050                                                   TNT_LLC_MISS,
2051                 },
2052                 [C(OP_PREFETCH)] = {
2053                         [C(RESULT_ACCESS)]      = 0x0,
2054                         [C(RESULT_MISS)]        = 0x0,
2055                 },
2056         },
2057 };
2058
2059 EVENT_ATTR_STR(topdown-fe-bound,       td_fe_bound_tnt,        "event=0x71,umask=0x0");
2060 EVENT_ATTR_STR(topdown-retiring,       td_retiring_tnt,        "event=0xc2,umask=0x0");
2061 EVENT_ATTR_STR(topdown-bad-spec,       td_bad_spec_tnt,        "event=0x73,umask=0x6");
2062 EVENT_ATTR_STR(topdown-be-bound,       td_be_bound_tnt,        "event=0x74,umask=0x0");
2063
2064 static struct attribute *tnt_events_attrs[] = {
2065         EVENT_PTR(td_fe_bound_tnt),
2066         EVENT_PTR(td_retiring_tnt),
2067         EVENT_PTR(td_bad_spec_tnt),
2068         EVENT_PTR(td_be_bound_tnt),
2069         NULL,
2070 };
2071
2072 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
2073         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2074         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
2075         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
2076         EVENT_EXTRA_END
2077 };
2078
2079 #define KNL_OT_L2_HITE          BIT_ULL(19) /* Other Tile L2 Hit */
2080 #define KNL_OT_L2_HITF          BIT_ULL(20) /* Other Tile L2 Hit */
2081 #define KNL_MCDRAM_LOCAL        BIT_ULL(21)
2082 #define KNL_MCDRAM_FAR          BIT_ULL(22)
2083 #define KNL_DDR_LOCAL           BIT_ULL(23)
2084 #define KNL_DDR_FAR             BIT_ULL(24)
2085 #define KNL_DRAM_ANY            (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
2086                                     KNL_DDR_LOCAL | KNL_DDR_FAR)
2087 #define KNL_L2_READ             SLM_DMND_READ
2088 #define KNL_L2_WRITE            SLM_DMND_WRITE
2089 #define KNL_L2_PREFETCH         SLM_DMND_PREFETCH
2090 #define KNL_L2_ACCESS           SLM_LLC_ACCESS
2091 #define KNL_L2_MISS             (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
2092                                    KNL_DRAM_ANY | SNB_SNP_ANY | \
2093                                                   SNB_NON_DRAM)
2094
2095 static __initconst const u64 knl_hw_cache_extra_regs
2096                                 [PERF_COUNT_HW_CACHE_MAX]
2097                                 [PERF_COUNT_HW_CACHE_OP_MAX]
2098                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2099         [C(LL)] = {
2100                 [C(OP_READ)] = {
2101                         [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2102                         [C(RESULT_MISS)]   = 0,
2103                 },
2104                 [C(OP_WRITE)] = {
2105                         [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2106                         [C(RESULT_MISS)]   = KNL_L2_WRITE | KNL_L2_MISS,
2107                 },
2108                 [C(OP_PREFETCH)] = {
2109                         [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2110                         [C(RESULT_MISS)]   = KNL_L2_PREFETCH | KNL_L2_MISS,
2111                 },
2112         },
2113 };
2114
2115 /*
2116  * Used from PMIs where the LBRs are already disabled.
2117  *
2118  * This function could be called consecutively. It is required to remain in
2119  * disabled state if called consecutively.
2120  *
2121  * During consecutive calls, the same disable value will be written to related
2122  * registers, so the PMU state remains unchanged.
2123  *
2124  * intel_bts events don't coexist with intel PMU's BTS events because of
2125  * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
2126  * disabled around intel PMU's event batching etc, only inside the PMI handler.
2127  *
2128  * Avoid PEBS_ENABLE MSR access in PMIs.
2129  * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
2130  * It doesn't matter if the PEBS is enabled or not.
2131  * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
2132  * access PEBS_ENABLE MSR in disable_all()/enable_all().
2133  * However, there are some cases which may change PEBS status, e.g. PMI
2134  * throttle. The PEBS_ENABLE should be updated where the status changes.
2135  */
2136 static void __intel_pmu_disable_all(void)
2137 {
2138         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2139
2140         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2141
2142         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
2143                 intel_pmu_disable_bts();
2144 }
2145
2146 static void intel_pmu_disable_all(void)
2147 {
2148         __intel_pmu_disable_all();
2149         intel_pmu_pebs_disable_all();
2150         intel_pmu_lbr_disable_all();
2151 }
2152
2153 static void __intel_pmu_enable_all(int added, bool pmi)
2154 {
2155         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2156         u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2157
2158         intel_pmu_lbr_enable_all(pmi);
2159         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
2160                intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
2161
2162         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2163                 struct perf_event *event =
2164                         cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
2165
2166                 if (WARN_ON_ONCE(!event))
2167                         return;
2168
2169                 intel_pmu_enable_bts(event->hw.config);
2170         }
2171 }
2172
2173 static void intel_pmu_enable_all(int added)
2174 {
2175         intel_pmu_pebs_enable_all();
2176         __intel_pmu_enable_all(added, false);
2177 }
2178
2179 /*
2180  * Workaround for:
2181  *   Intel Errata AAK100 (model 26)
2182  *   Intel Errata AAP53  (model 30)
2183  *   Intel Errata BD53   (model 44)
2184  *
2185  * The official story:
2186  *   These chips need to be 'reset' when adding counters by programming the
2187  *   magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2188  *   in sequence on the same PMC or on different PMCs.
2189  *
2190  * In practise it appears some of these events do in fact count, and
2191  * we need to program all 4 events.
2192  */
2193 static void intel_pmu_nhm_workaround(void)
2194 {
2195         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2196         static const unsigned long nhm_magic[4] = {
2197                 0x4300B5,
2198                 0x4300D2,
2199                 0x4300B1,
2200                 0x4300B1
2201         };
2202         struct perf_event *event;
2203         int i;
2204
2205         /*
2206          * The Errata requires below steps:
2207          * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2208          * 2) Configure 4 PERFEVTSELx with the magic events and clear
2209          *    the corresponding PMCx;
2210          * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2211          * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2212          * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2213          */
2214
2215         /*
2216          * The real steps we choose are a little different from above.
2217          * A) To reduce MSR operations, we don't run step 1) as they
2218          *    are already cleared before this function is called;
2219          * B) Call x86_perf_event_update to save PMCx before configuring
2220          *    PERFEVTSELx with magic number;
2221          * C) With step 5), we do clear only when the PERFEVTSELx is
2222          *    not used currently.
2223          * D) Call x86_perf_event_set_period to restore PMCx;
2224          */
2225
2226         /* We always operate 4 pairs of PERF Counters */
2227         for (i = 0; i < 4; i++) {
2228                 event = cpuc->events[i];
2229                 if (event)
2230                         x86_perf_event_update(event);
2231         }
2232
2233         for (i = 0; i < 4; i++) {
2234                 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2235                 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2236         }
2237
2238         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2239         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2240
2241         for (i = 0; i < 4; i++) {
2242                 event = cpuc->events[i];
2243
2244                 if (event) {
2245                         x86_perf_event_set_period(event);
2246                         __x86_pmu_enable_event(&event->hw,
2247                                         ARCH_PERFMON_EVENTSEL_ENABLE);
2248                 } else
2249                         wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2250         }
2251 }
2252
2253 static void intel_pmu_nhm_enable_all(int added)
2254 {
2255         if (added)
2256                 intel_pmu_nhm_workaround();
2257         intel_pmu_enable_all(added);
2258 }
2259
2260 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2261 {
2262         u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2263
2264         if (cpuc->tfa_shadow != val) {
2265                 cpuc->tfa_shadow = val;
2266                 wrmsrl(MSR_TSX_FORCE_ABORT, val);
2267         }
2268 }
2269
2270 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2271 {
2272         /*
2273          * We're going to use PMC3, make sure TFA is set before we touch it.
2274          */
2275         if (cntr == 3)
2276                 intel_set_tfa(cpuc, true);
2277 }
2278
2279 static void intel_tfa_pmu_enable_all(int added)
2280 {
2281         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2282
2283         /*
2284          * If we find PMC3 is no longer used when we enable the PMU, we can
2285          * clear TFA.
2286          */
2287         if (!test_bit(3, cpuc->active_mask))
2288                 intel_set_tfa(cpuc, false);
2289
2290         intel_pmu_enable_all(added);
2291 }
2292
2293 static inline u64 intel_pmu_get_status(void)
2294 {
2295         u64 status;
2296
2297         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2298
2299         return status;
2300 }
2301
2302 static inline void intel_pmu_ack_status(u64 ack)
2303 {
2304         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2305 }
2306
2307 static inline bool event_is_checkpointed(struct perf_event *event)
2308 {
2309         return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2310 }
2311
2312 static inline void intel_set_masks(struct perf_event *event, int idx)
2313 {
2314         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2315
2316         if (event->attr.exclude_host)
2317                 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2318         if (event->attr.exclude_guest)
2319                 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2320         if (event_is_checkpointed(event))
2321                 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2322 }
2323
2324 static inline void intel_clear_masks(struct perf_event *event, int idx)
2325 {
2326         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2327
2328         __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2329         __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2330         __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2331 }
2332
2333 static void intel_pmu_disable_fixed(struct perf_event *event)
2334 {
2335         struct hw_perf_event *hwc = &event->hw;
2336         u64 ctrl_val, mask;
2337         int idx = hwc->idx;
2338
2339         if (is_topdown_idx(idx)) {
2340                 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2341
2342                 /*
2343                  * When there are other active TopDown events,
2344                  * don't disable the fixed counter 3.
2345                  */
2346                 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2347                         return;
2348                 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2349         }
2350
2351         intel_clear_masks(event, idx);
2352
2353         mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4);
2354         rdmsrl(hwc->config_base, ctrl_val);
2355         ctrl_val &= ~mask;
2356         wrmsrl(hwc->config_base, ctrl_val);
2357 }
2358
2359 static void intel_pmu_disable_event(struct perf_event *event)
2360 {
2361         struct hw_perf_event *hwc = &event->hw;
2362         int idx = hwc->idx;
2363
2364         switch (idx) {
2365         case 0 ... INTEL_PMC_IDX_FIXED - 1:
2366                 intel_clear_masks(event, idx);
2367                 x86_pmu_disable_event(event);
2368                 break;
2369         case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2370         case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2371                 intel_pmu_disable_fixed(event);
2372                 break;
2373         case INTEL_PMC_IDX_FIXED_BTS:
2374                 intel_pmu_disable_bts();
2375                 intel_pmu_drain_bts_buffer();
2376                 return;
2377         case INTEL_PMC_IDX_FIXED_VLBR:
2378                 intel_clear_masks(event, idx);
2379                 break;
2380         default:
2381                 intel_clear_masks(event, idx);
2382                 pr_warn("Failed to disable the event with invalid index %d\n",
2383                         idx);
2384                 return;
2385         }
2386
2387         /*
2388          * Needs to be called after x86_pmu_disable_event,
2389          * so we don't trigger the event without PEBS bit set.
2390          */
2391         if (unlikely(event->attr.precise_ip))
2392                 intel_pmu_pebs_disable(event);
2393 }
2394
2395 static void intel_pmu_del_event(struct perf_event *event)
2396 {
2397         if (needs_branch_stack(event))
2398                 intel_pmu_lbr_del(event);
2399         if (event->attr.precise_ip)
2400                 intel_pmu_pebs_del(event);
2401 }
2402
2403 static int icl_set_topdown_event_period(struct perf_event *event)
2404 {
2405         struct hw_perf_event *hwc = &event->hw;
2406         s64 left = local64_read(&hwc->period_left);
2407
2408         /*
2409          * The values in PERF_METRICS MSR are derived from fixed counter 3.
2410          * Software should start both registers, PERF_METRICS and fixed
2411          * counter 3, from zero.
2412          * Clear PERF_METRICS and Fixed counter 3 in initialization.
2413          * After that, both MSRs will be cleared for each read.
2414          * Don't need to clear them again.
2415          */
2416         if (left == x86_pmu.max_period) {
2417                 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2418                 wrmsrl(MSR_PERF_METRICS, 0);
2419                 hwc->saved_slots = 0;
2420                 hwc->saved_metric = 0;
2421         }
2422
2423         if ((hwc->saved_slots) && is_slots_event(event)) {
2424                 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);
2425                 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric);
2426         }
2427
2428         perf_event_update_userpage(event);
2429
2430         return 0;
2431 }
2432
2433 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
2434 {
2435         u32 val;
2436
2437         /*
2438          * The metric is reported as an 8bit integer fraction
2439          * suming up to 0xff.
2440          * slots-in-metric = (Metric / 0xff) * slots
2441          */
2442         val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
2443         return  mul_u64_u32_div(slots, val, 0xff);
2444 }
2445
2446 static u64 icl_get_topdown_value(struct perf_event *event,
2447                                        u64 slots, u64 metrics)
2448 {
2449         int idx = event->hw.idx;
2450         u64 delta;
2451
2452         if (is_metric_idx(idx))
2453                 delta = icl_get_metrics_event_value(metrics, slots, idx);
2454         else
2455                 delta = slots;
2456
2457         return delta;
2458 }
2459
2460 static void __icl_update_topdown_event(struct perf_event *event,
2461                                        u64 slots, u64 metrics,
2462                                        u64 last_slots, u64 last_metrics)
2463 {
2464         u64 delta, last = 0;
2465
2466         delta = icl_get_topdown_value(event, slots, metrics);
2467         if (last_slots)
2468                 last = icl_get_topdown_value(event, last_slots, last_metrics);
2469
2470         /*
2471          * The 8bit integer fraction of metric may be not accurate,
2472          * especially when the changes is very small.
2473          * For example, if only a few bad_spec happens, the fraction
2474          * may be reduced from 1 to 0. If so, the bad_spec event value
2475          * will be 0 which is definitely less than the last value.
2476          * Avoid update event->count for this case.
2477          */
2478         if (delta > last) {
2479                 delta -= last;
2480                 local64_add(delta, &event->count);
2481         }
2482 }
2483
2484 static void update_saved_topdown_regs(struct perf_event *event, u64 slots,
2485                                       u64 metrics, int metric_end)
2486 {
2487         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2488         struct perf_event *other;
2489         int idx;
2490
2491         event->hw.saved_slots = slots;
2492         event->hw.saved_metric = metrics;
2493
2494         for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2495                 if (!is_topdown_idx(idx))
2496                         continue;
2497                 other = cpuc->events[idx];
2498                 other->hw.saved_slots = slots;
2499                 other->hw.saved_metric = metrics;
2500         }
2501 }
2502
2503 /*
2504  * Update all active Topdown events.
2505  *
2506  * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
2507  * modify by a NMI. PMU has to be disabled before calling this function.
2508  */
2509
2510 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end)
2511 {
2512         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2513         struct perf_event *other;
2514         u64 slots, metrics;
2515         bool reset = true;
2516         int idx;
2517
2518         /* read Fixed counter 3 */
2519         rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots);
2520         if (!slots)
2521                 return 0;
2522
2523         /* read PERF_METRICS */
2524         rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics);
2525
2526         for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2527                 if (!is_topdown_idx(idx))
2528                         continue;
2529                 other = cpuc->events[idx];
2530                 __icl_update_topdown_event(other, slots, metrics,
2531                                            event ? event->hw.saved_slots : 0,
2532                                            event ? event->hw.saved_metric : 0);
2533         }
2534
2535         /*
2536          * Check and update this event, which may have been cleared
2537          * in active_mask e.g. x86_pmu_stop()
2538          */
2539         if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
2540                 __icl_update_topdown_event(event, slots, metrics,
2541                                            event->hw.saved_slots,
2542                                            event->hw.saved_metric);
2543
2544                 /*
2545                  * In x86_pmu_stop(), the event is cleared in active_mask first,
2546                  * then drain the delta, which indicates context switch for
2547                  * counting.
2548                  * Save metric and slots for context switch.
2549                  * Don't need to reset the PERF_METRICS and Fixed counter 3.
2550                  * Because the values will be restored in next schedule in.
2551                  */
2552                 update_saved_topdown_regs(event, slots, metrics, metric_end);
2553                 reset = false;
2554         }
2555
2556         if (reset) {
2557                 /* The fixed counter 3 has to be written before the PERF_METRICS. */
2558                 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2559                 wrmsrl(MSR_PERF_METRICS, 0);
2560                 if (event)
2561                         update_saved_topdown_regs(event, 0, 0, metric_end);
2562         }
2563
2564         return slots;
2565 }
2566
2567 static u64 icl_update_topdown_event(struct perf_event *event)
2568 {
2569         return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE +
2570                                                  x86_pmu.num_topdown_events - 1);
2571 }
2572
2573 static void intel_pmu_read_topdown_event(struct perf_event *event)
2574 {
2575         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2576
2577         /* Only need to call update_topdown_event() once for group read. */
2578         if ((cpuc->txn_flags & PERF_PMU_TXN_READ) &&
2579             !is_slots_event(event))
2580                 return;
2581
2582         perf_pmu_disable(event->pmu);
2583         x86_pmu.update_topdown_event(event);
2584         perf_pmu_enable(event->pmu);
2585 }
2586
2587 static void intel_pmu_read_event(struct perf_event *event)
2588 {
2589         if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2590                 intel_pmu_auto_reload_read(event);
2591         else if (is_topdown_count(event) && x86_pmu.update_topdown_event)
2592                 intel_pmu_read_topdown_event(event);
2593         else
2594                 x86_perf_event_update(event);
2595 }
2596
2597 static void intel_pmu_enable_fixed(struct perf_event *event)
2598 {
2599         struct hw_perf_event *hwc = &event->hw;
2600         u64 ctrl_val, mask, bits = 0;
2601         int idx = hwc->idx;
2602
2603         if (is_topdown_idx(idx)) {
2604                 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2605                 /*
2606                  * When there are other active TopDown events,
2607                  * don't enable the fixed counter 3 again.
2608                  */
2609                 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2610                         return;
2611
2612                 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2613         }
2614
2615         intel_set_masks(event, idx);
2616
2617         /*
2618          * Enable IRQ generation (0x8), if not PEBS,
2619          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2620          * if requested:
2621          */
2622         if (!event->attr.precise_ip)
2623                 bits |= 0x8;
2624         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2625                 bits |= 0x2;
2626         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2627                 bits |= 0x1;
2628
2629         /*
2630          * ANY bit is supported in v3 and up
2631          */
2632         if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2633                 bits |= 0x4;
2634
2635         idx -= INTEL_PMC_IDX_FIXED;
2636         bits <<= (idx * 4);
2637         mask = 0xfULL << (idx * 4);
2638
2639         if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
2640                 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2641                 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2642         }
2643
2644         rdmsrl(hwc->config_base, ctrl_val);
2645         ctrl_val &= ~mask;
2646         ctrl_val |= bits;
2647         wrmsrl(hwc->config_base, ctrl_val);
2648 }
2649
2650 static void intel_pmu_enable_event(struct perf_event *event)
2651 {
2652         struct hw_perf_event *hwc = &event->hw;
2653         int idx = hwc->idx;
2654
2655         if (unlikely(event->attr.precise_ip))
2656                 intel_pmu_pebs_enable(event);
2657
2658         switch (idx) {
2659         case 0 ... INTEL_PMC_IDX_FIXED - 1:
2660                 intel_set_masks(event, idx);
2661                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2662                 break;
2663         case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2664         case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2665                 intel_pmu_enable_fixed(event);
2666                 break;
2667         case INTEL_PMC_IDX_FIXED_BTS:
2668                 if (!__this_cpu_read(cpu_hw_events.enabled))
2669                         return;
2670                 intel_pmu_enable_bts(hwc->config);
2671                 break;
2672         case INTEL_PMC_IDX_FIXED_VLBR:
2673                 intel_set_masks(event, idx);
2674                 break;
2675         default:
2676                 pr_warn("Failed to enable the event with invalid index %d\n",
2677                         idx);
2678         }
2679 }
2680
2681 static void intel_pmu_add_event(struct perf_event *event)
2682 {
2683         if (event->attr.precise_ip)
2684                 intel_pmu_pebs_add(event);
2685         if (needs_branch_stack(event))
2686                 intel_pmu_lbr_add(event);
2687 }
2688
2689 /*
2690  * Save and restart an expired event. Called by NMI contexts,
2691  * so it has to be careful about preempting normal event ops:
2692  */
2693 int intel_pmu_save_and_restart(struct perf_event *event)
2694 {
2695         x86_perf_event_update(event);
2696         /*
2697          * For a checkpointed counter always reset back to 0.  This
2698          * avoids a situation where the counter overflows, aborts the
2699          * transaction and is then set back to shortly before the
2700          * overflow, and overflows and aborts again.
2701          */
2702         if (unlikely(event_is_checkpointed(event))) {
2703                 /* No race with NMIs because the counter should not be armed */
2704                 wrmsrl(event->hw.event_base, 0);
2705                 local64_set(&event->hw.prev_count, 0);
2706         }
2707         return x86_perf_event_set_period(event);
2708 }
2709
2710 static void intel_pmu_reset(void)
2711 {
2712         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2713         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2714         int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
2715         int num_counters = hybrid(cpuc->pmu, num_counters);
2716         unsigned long flags;
2717         int idx;
2718
2719         if (!num_counters)
2720                 return;
2721
2722         local_irq_save(flags);
2723
2724         pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2725
2726         for (idx = 0; idx < num_counters; idx++) {
2727                 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2728                 wrmsrl_safe(x86_pmu_event_addr(idx),  0ull);
2729         }
2730         for (idx = 0; idx < num_counters_fixed; idx++) {
2731                 if (fixed_counter_disabled(idx, cpuc->pmu))
2732                         continue;
2733                 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
2734         }
2735
2736         if (ds)
2737                 ds->bts_index = ds->bts_buffer_base;
2738
2739         /* Ack all overflows and disable fixed counters */
2740         if (x86_pmu.version >= 2) {
2741                 intel_pmu_ack_status(intel_pmu_get_status());
2742                 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2743         }
2744
2745         /* Reset LBRs and LBR freezing */
2746         if (x86_pmu.lbr_nr) {
2747                 update_debugctlmsr(get_debugctlmsr() &
2748                         ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2749         }
2750
2751         local_irq_restore(flags);
2752 }
2753
2754 static int handle_pmi_common(struct pt_regs *regs, u64 status)
2755 {
2756         struct perf_sample_data data;
2757         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2758         int bit;
2759         int handled = 0;
2760         u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2761
2762         inc_irq_stat(apic_perf_irqs);
2763
2764         /*
2765          * Ignore a range of extra bits in status that do not indicate
2766          * overflow by themselves.
2767          */
2768         status &= ~(GLOBAL_STATUS_COND_CHG |
2769                     GLOBAL_STATUS_ASIF |
2770                     GLOBAL_STATUS_LBRS_FROZEN);
2771         if (!status)
2772                 return 0;
2773         /*
2774          * In case multiple PEBS events are sampled at the same time,
2775          * it is possible to have GLOBAL_STATUS bit 62 set indicating
2776          * PEBS buffer overflow and also seeing at most 3 PEBS counters
2777          * having their bits set in the status register. This is a sign
2778          * that there was at least one PEBS record pending at the time
2779          * of the PMU interrupt. PEBS counters must only be processed
2780          * via the drain_pebs() calls and not via the regular sample
2781          * processing loop coming after that the function, otherwise
2782          * phony regular samples may be generated in the sampling buffer
2783          * not marked with the EXACT tag. Another possibility is to have
2784          * one PEBS event and at least one non-PEBS event whic hoverflows
2785          * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
2786          * not be set, yet the overflow status bit for the PEBS counter will
2787          * be on Skylake.
2788          *
2789          * To avoid this problem, we systematically ignore the PEBS-enabled
2790          * counters from the GLOBAL_STATUS mask and we always process PEBS
2791          * events via drain_pebs().
2792          */
2793         if (x86_pmu.flags & PMU_FL_PEBS_ALL)
2794                 status &= ~cpuc->pebs_enabled;
2795         else
2796                 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
2797
2798         /*
2799          * PEBS overflow sets bit 62 in the global status register
2800          */
2801         if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
2802                 u64 pebs_enabled = cpuc->pebs_enabled;
2803
2804                 handled++;
2805                 x86_pmu.drain_pebs(regs, &data);
2806                 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
2807
2808                 /*
2809                  * PMI throttle may be triggered, which stops the PEBS event.
2810                  * Although cpuc->pebs_enabled is updated accordingly, the
2811                  * MSR_IA32_PEBS_ENABLE is not updated. Because the
2812                  * cpuc->enabled has been forced to 0 in PMI.
2813                  * Update the MSR if pebs_enabled is changed.
2814                  */
2815                 if (pebs_enabled != cpuc->pebs_enabled)
2816                         wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
2817         }
2818
2819         /*
2820          * Intel PT
2821          */
2822         if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
2823                 handled++;
2824                 if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() &&
2825                         perf_guest_cbs->handle_intel_pt_intr))
2826                         perf_guest_cbs->handle_intel_pt_intr();
2827                 else
2828                         intel_pt_interrupt();
2829         }
2830
2831         /*
2832          * Intel Perf mertrics
2833          */
2834         if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
2835                 handled++;
2836                 if (x86_pmu.update_topdown_event)
2837                         x86_pmu.update_topdown_event(NULL);
2838         }
2839
2840         /*
2841          * Checkpointed counters can lead to 'spurious' PMIs because the
2842          * rollback caused by the PMI will have cleared the overflow status
2843          * bit. Therefore always force probe these counters.
2844          */
2845         status |= cpuc->intel_cp_status;
2846
2847         for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
2848                 struct perf_event *event = cpuc->events[bit];
2849
2850                 handled++;
2851
2852                 if (!test_bit(bit, cpuc->active_mask))
2853                         continue;
2854
2855                 if (!intel_pmu_save_and_restart(event))
2856                         continue;
2857
2858                 perf_sample_data_init(&data, 0, event->hw.last_period);
2859
2860                 if (has_branch_stack(event))
2861                         data.br_stack = &cpuc->lbr_stack;
2862
2863                 if (perf_event_overflow(event, &data, regs))
2864                         x86_pmu_stop(event, 0);
2865         }
2866
2867         return handled;
2868 }
2869
2870 /*
2871  * This handler is triggered by the local APIC, so the APIC IRQ handling
2872  * rules apply:
2873  */
2874 static int intel_pmu_handle_irq(struct pt_regs *regs)
2875 {
2876         struct cpu_hw_events *cpuc;
2877         int loops;
2878         u64 status;
2879         int handled;
2880         int pmu_enabled;
2881
2882         cpuc = this_cpu_ptr(&cpu_hw_events);
2883
2884         /*
2885          * Save the PMU state.
2886          * It needs to be restored when leaving the handler.
2887          */
2888         pmu_enabled = cpuc->enabled;
2889         /*
2890          * No known reason to not always do late ACK,
2891          * but just in case do it opt-in.
2892          */
2893         if (!x86_pmu.late_ack)
2894                 apic_write(APIC_LVTPC, APIC_DM_NMI);
2895         intel_bts_disable_local();
2896         cpuc->enabled = 0;
2897         __intel_pmu_disable_all();
2898         handled = intel_pmu_drain_bts_buffer();
2899         handled += intel_bts_interrupt();
2900         status = intel_pmu_get_status();
2901         if (!status)
2902                 goto done;
2903
2904         loops = 0;
2905 again:
2906         intel_pmu_lbr_read();
2907         intel_pmu_ack_status(status);
2908         if (++loops > 100) {
2909                 static bool warned;
2910
2911                 if (!warned) {
2912                         WARN(1, "perfevents: irq loop stuck!\n");
2913                         perf_event_print_debug();
2914                         warned = true;
2915                 }
2916                 intel_pmu_reset();
2917                 goto done;
2918         }
2919
2920         handled += handle_pmi_common(regs, status);
2921
2922         /*
2923          * Repeat if there is more work to be done:
2924          */
2925         status = intel_pmu_get_status();
2926         if (status)
2927                 goto again;
2928
2929 done:
2930         /* Only restore PMU state when it's active. See x86_pmu_disable(). */
2931         cpuc->enabled = pmu_enabled;
2932         if (pmu_enabled)
2933                 __intel_pmu_enable_all(0, true);
2934         intel_bts_enable_local();
2935
2936         /*
2937          * Only unmask the NMI after the overflow counters
2938          * have been reset. This avoids spurious NMIs on
2939          * Haswell CPUs.
2940          */
2941         if (x86_pmu.late_ack)
2942                 apic_write(APIC_LVTPC, APIC_DM_NMI);
2943         return handled;
2944 }
2945
2946 static struct event_constraint *
2947 intel_bts_constraints(struct perf_event *event)
2948 {
2949         if (unlikely(intel_pmu_has_bts(event)))
2950                 return &bts_constraint;
2951
2952         return NULL;
2953 }
2954
2955 /*
2956  * Note: matches a fake event, like Fixed2.
2957  */
2958 static struct event_constraint *
2959 intel_vlbr_constraints(struct perf_event *event)
2960 {
2961         struct event_constraint *c = &vlbr_constraint;
2962
2963         if (unlikely(constraint_match(c, event->hw.config)))
2964                 return c;
2965
2966         return NULL;
2967 }
2968
2969 static int intel_alt_er(struct cpu_hw_events *cpuc,
2970                         int idx, u64 config)
2971 {
2972         struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);
2973         int alt_idx = idx;
2974
2975         if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
2976                 return idx;
2977
2978         if (idx == EXTRA_REG_RSP_0)
2979                 alt_idx = EXTRA_REG_RSP_1;
2980
2981         if (idx == EXTRA_REG_RSP_1)
2982                 alt_idx = EXTRA_REG_RSP_0;
2983
2984         if (config & ~extra_regs[alt_idx].valid_mask)
2985                 return idx;
2986
2987         return alt_idx;
2988 }
2989
2990 static void intel_fixup_er(struct perf_event *event, int idx)
2991 {
2992         struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
2993         event->hw.extra_reg.idx = idx;
2994
2995         if (idx == EXTRA_REG_RSP_0) {
2996                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2997                 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event;
2998                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
2999         } else if (idx == EXTRA_REG_RSP_1) {
3000                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3001                 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event;
3002                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
3003         }
3004 }
3005
3006 /*
3007  * manage allocation of shared extra msr for certain events
3008  *
3009  * sharing can be:
3010  * per-cpu: to be shared between the various events on a single PMU
3011  * per-core: per-cpu + shared by HT threads
3012  */
3013 static struct event_constraint *
3014 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
3015                                    struct perf_event *event,
3016                                    struct hw_perf_event_extra *reg)
3017 {
3018         struct event_constraint *c = &emptyconstraint;
3019         struct er_account *era;
3020         unsigned long flags;
3021         int idx = reg->idx;
3022
3023         /*
3024          * reg->alloc can be set due to existing state, so for fake cpuc we
3025          * need to ignore this, otherwise we might fail to allocate proper fake
3026          * state for this extra reg constraint. Also see the comment below.
3027          */
3028         if (reg->alloc && !cpuc->is_fake)
3029                 return NULL; /* call x86_get_event_constraint() */
3030
3031 again:
3032         era = &cpuc->shared_regs->regs[idx];
3033         /*
3034          * we use spin_lock_irqsave() to avoid lockdep issues when
3035          * passing a fake cpuc
3036          */
3037         raw_spin_lock_irqsave(&era->lock, flags);
3038
3039         if (!atomic_read(&era->ref) || era->config == reg->config) {
3040
3041                 /*
3042                  * If its a fake cpuc -- as per validate_{group,event}() we
3043                  * shouldn't touch event state and we can avoid doing so
3044                  * since both will only call get_event_constraints() once
3045                  * on each event, this avoids the need for reg->alloc.
3046                  *
3047                  * Not doing the ER fixup will only result in era->reg being
3048                  * wrong, but since we won't actually try and program hardware
3049                  * this isn't a problem either.
3050                  */
3051                 if (!cpuc->is_fake) {
3052                         if (idx != reg->idx)
3053                                 intel_fixup_er(event, idx);
3054
3055                         /*
3056                          * x86_schedule_events() can call get_event_constraints()
3057                          * multiple times on events in the case of incremental
3058                          * scheduling(). reg->alloc ensures we only do the ER
3059                          * allocation once.
3060                          */
3061                         reg->alloc = 1;
3062                 }
3063
3064                 /* lock in msr value */
3065                 era->config = reg->config;
3066                 era->reg = reg->reg;
3067
3068                 /* one more user */
3069                 atomic_inc(&era->ref);
3070
3071                 /*
3072                  * need to call x86_get_event_constraint()
3073                  * to check if associated event has constraints
3074                  */
3075                 c = NULL;
3076         } else {
3077                 idx = intel_alt_er(cpuc, idx, reg->config);
3078                 if (idx != reg->idx) {
3079                         raw_spin_unlock_irqrestore(&era->lock, flags);
3080                         goto again;
3081                 }
3082         }
3083         raw_spin_unlock_irqrestore(&era->lock, flags);
3084
3085         return c;
3086 }
3087
3088 static void
3089 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
3090                                    struct hw_perf_event_extra *reg)
3091 {
3092         struct er_account *era;
3093
3094         /*
3095          * Only put constraint if extra reg was actually allocated. Also takes
3096          * care of event which do not use an extra shared reg.
3097          *
3098          * Also, if this is a fake cpuc we shouldn't touch any event state
3099          * (reg->alloc) and we don't care about leaving inconsistent cpuc state
3100          * either since it'll be thrown out.
3101          */
3102         if (!reg->alloc || cpuc->is_fake)
3103                 return;
3104
3105         era = &cpuc->shared_regs->regs[reg->idx];
3106
3107         /* one fewer user */
3108         atomic_dec(&era->ref);
3109
3110         /* allocate again next time */
3111         reg->alloc = 0;
3112 }
3113
3114 static struct event_constraint *
3115 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
3116                               struct perf_event *event)
3117 {
3118         struct event_constraint *c = NULL, *d;
3119         struct hw_perf_event_extra *xreg, *breg;
3120
3121         xreg = &event->hw.extra_reg;
3122         if (xreg->idx != EXTRA_REG_NONE) {
3123                 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
3124                 if (c == &emptyconstraint)
3125                         return c;
3126         }
3127         breg = &event->hw.branch_reg;
3128         if (breg->idx != EXTRA_REG_NONE) {
3129                 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
3130                 if (d == &emptyconstraint) {
3131                         __intel_shared_reg_put_constraints(cpuc, xreg);
3132                         c = d;
3133                 }
3134         }
3135         return c;
3136 }
3137
3138 struct event_constraint *
3139 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3140                           struct perf_event *event)
3141 {
3142         struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints);
3143         struct event_constraint *c;
3144
3145         if (event_constraints) {
3146                 for_each_event_constraint(c, event_constraints) {
3147                         if (constraint_match(c, event->hw.config)) {
3148                                 event->hw.flags |= c->flags;
3149                                 return c;
3150                         }
3151                 }
3152         }
3153
3154         return &hybrid_var(cpuc->pmu, unconstrained);
3155 }
3156
3157 static struct event_constraint *
3158 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3159                             struct perf_event *event)
3160 {
3161         struct event_constraint *c;
3162
3163         c = intel_vlbr_constraints(event);
3164         if (c)
3165                 return c;
3166
3167         c = intel_bts_constraints(event);
3168         if (c)
3169                 return c;
3170
3171         c = intel_shared_regs_constraints(cpuc, event);
3172         if (c)
3173                 return c;
3174
3175         c = intel_pebs_constraints(event);
3176         if (c)
3177                 return c;
3178
3179         return x86_get_event_constraints(cpuc, idx, event);
3180 }
3181
3182 static void
3183 intel_start_scheduling(struct cpu_hw_events *cpuc)
3184 {
3185         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3186         struct intel_excl_states *xl;
3187         int tid = cpuc->excl_thread_id;
3188
3189         /*
3190          * nothing needed if in group validation mode
3191          */
3192         if (cpuc->is_fake || !is_ht_workaround_enabled())
3193                 return;
3194
3195         /*
3196          * no exclusion needed
3197          */
3198         if (WARN_ON_ONCE(!excl_cntrs))
3199                 return;
3200
3201         xl = &excl_cntrs->states[tid];
3202
3203         xl->sched_started = true;
3204         /*
3205          * lock shared state until we are done scheduling
3206          * in stop_event_scheduling()
3207          * makes scheduling appear as a transaction
3208          */
3209         raw_spin_lock(&excl_cntrs->lock);
3210 }
3211
3212 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
3213 {
3214         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3215         struct event_constraint *c = cpuc->event_constraint[idx];
3216         struct intel_excl_states *xl;
3217         int tid = cpuc->excl_thread_id;
3218
3219         if (cpuc->is_fake || !is_ht_workaround_enabled())
3220                 return;
3221
3222         if (WARN_ON_ONCE(!excl_cntrs))
3223                 return;
3224
3225         if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
3226                 return;
3227
3228         xl = &excl_cntrs->states[tid];
3229
3230         lockdep_assert_held(&excl_cntrs->lock);
3231
3232         if (c->flags & PERF_X86_EVENT_EXCL)
3233                 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
3234         else
3235                 xl->state[cntr] = INTEL_EXCL_SHARED;
3236 }
3237
3238 static void
3239 intel_stop_scheduling(struct cpu_hw_events *cpuc)
3240 {
3241         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3242         struct intel_excl_states *xl;
3243         int tid = cpuc->excl_thread_id;
3244
3245         /*
3246          * nothing needed if in group validation mode
3247          */
3248         if (cpuc->is_fake || !is_ht_workaround_enabled())
3249                 return;
3250         /*
3251          * no exclusion needed
3252          */
3253         if (WARN_ON_ONCE(!excl_cntrs))
3254                 return;
3255
3256         xl = &excl_cntrs->states[tid];
3257
3258         xl->sched_started = false;
3259         /*
3260          * release shared state lock (acquired in intel_start_scheduling())
3261          */
3262         raw_spin_unlock(&excl_cntrs->lock);
3263 }
3264
3265 static struct event_constraint *
3266 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
3267 {
3268         WARN_ON_ONCE(!cpuc->constraint_list);
3269
3270         if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
3271                 struct event_constraint *cx;
3272
3273                 /*
3274                  * grab pre-allocated constraint entry
3275                  */
3276                 cx = &cpuc->constraint_list[idx];
3277
3278                 /*
3279                  * initialize dynamic constraint
3280                  * with static constraint
3281                  */
3282                 *cx = *c;
3283
3284                 /*
3285                  * mark constraint as dynamic
3286                  */
3287                 cx->flags |= PERF_X86_EVENT_DYNAMIC;
3288                 c = cx;
3289         }
3290
3291         return c;
3292 }
3293
3294 static struct event_constraint *
3295 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
3296                            int idx, struct event_constraint *c)
3297 {
3298         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3299         struct intel_excl_states *xlo;
3300         int tid = cpuc->excl_thread_id;
3301         int is_excl, i, w;
3302
3303         /*
3304          * validating a group does not require
3305          * enforcing cross-thread  exclusion
3306          */
3307         if (cpuc->is_fake || !is_ht_workaround_enabled())
3308                 return c;
3309
3310         /*
3311          * no exclusion needed
3312          */
3313         if (WARN_ON_ONCE(!excl_cntrs))
3314                 return c;
3315
3316         /*
3317          * because we modify the constraint, we need
3318          * to make a copy. Static constraints come
3319          * from static const tables.
3320          *
3321          * only needed when constraint has not yet
3322          * been cloned (marked dynamic)
3323          */
3324         c = dyn_constraint(cpuc, c, idx);
3325
3326         /*
3327          * From here on, the constraint is dynamic.
3328          * Either it was just allocated above, or it
3329          * was allocated during a earlier invocation
3330          * of this function
3331          */
3332
3333         /*
3334          * state of sibling HT
3335          */
3336         xlo = &excl_cntrs->states[tid ^ 1];
3337
3338         /*
3339          * event requires exclusive counter access
3340          * across HT threads
3341          */
3342         is_excl = c->flags & PERF_X86_EVENT_EXCL;
3343         if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
3344                 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
3345                 if (!cpuc->n_excl++)
3346                         WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
3347         }
3348
3349         /*
3350          * Modify static constraint with current dynamic
3351          * state of thread
3352          *
3353          * EXCLUSIVE: sibling counter measuring exclusive event
3354          * SHARED   : sibling counter measuring non-exclusive event
3355          * UNUSED   : sibling counter unused
3356          */
3357         w = c->weight;
3358         for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
3359                 /*
3360                  * exclusive event in sibling counter
3361                  * our corresponding counter cannot be used
3362                  * regardless of our event
3363                  */
3364                 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
3365                         __clear_bit(i, c->idxmsk);
3366                         w--;
3367                         continue;
3368                 }
3369                 /*
3370                  * if measuring an exclusive event, sibling
3371                  * measuring non-exclusive, then counter cannot
3372                  * be used
3373                  */
3374                 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
3375                         __clear_bit(i, c->idxmsk);
3376                         w--;
3377                         continue;
3378                 }
3379         }
3380
3381         /*
3382          * if we return an empty mask, then switch
3383          * back to static empty constraint to avoid
3384          * the cost of freeing later on
3385          */
3386         if (!w)
3387                 c = &emptyconstraint;
3388
3389         c->weight = w;
3390
3391         return c;
3392 }
3393
3394 static struct event_constraint *
3395 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3396                             struct perf_event *event)
3397 {
3398         struct event_constraint *c1, *c2;
3399
3400         c1 = cpuc->event_constraint[idx];
3401
3402         /*
3403          * first time only
3404          * - static constraint: no change across incremental scheduling calls
3405          * - dynamic constraint: handled by intel_get_excl_constraints()
3406          */
3407         c2 = __intel_get_event_constraints(cpuc, idx, event);
3408         if (c1) {
3409                 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3410                 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
3411                 c1->weight = c2->weight;
3412                 c2 = c1;
3413         }
3414
3415         if (cpuc->excl_cntrs)
3416                 return intel_get_excl_constraints(cpuc, event, idx, c2);
3417
3418         return c2;
3419 }
3420
3421 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3422                 struct perf_event *event)
3423 {
3424         struct hw_perf_event *hwc = &event->hw;
3425         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3426         int tid = cpuc->excl_thread_id;
3427         struct intel_excl_states *xl;
3428
3429         /*
3430          * nothing needed if in group validation mode
3431          */
3432         if (cpuc->is_fake)
3433                 return;
3434
3435         if (WARN_ON_ONCE(!excl_cntrs))
3436                 return;
3437
3438         if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
3439                 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
3440                 if (!--cpuc->n_excl)
3441                         WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
3442         }
3443
3444         /*
3445          * If event was actually assigned, then mark the counter state as
3446          * unused now.
3447          */
3448         if (hwc->idx >= 0) {
3449                 xl = &excl_cntrs->states[tid];
3450
3451                 /*
3452                  * put_constraint may be called from x86_schedule_events()
3453                  * which already has the lock held so here make locking
3454                  * conditional.
3455                  */
3456                 if (!xl->sched_started)
3457                         raw_spin_lock(&excl_cntrs->lock);
3458
3459                 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
3460
3461                 if (!xl->sched_started)
3462                         raw_spin_unlock(&excl_cntrs->lock);
3463         }
3464 }
3465
3466 static void
3467 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
3468                                         struct perf_event *event)
3469 {
3470         struct hw_perf_event_extra *reg;
3471
3472         reg = &event->hw.extra_reg;
3473         if (reg->idx != EXTRA_REG_NONE)
3474                 __intel_shared_reg_put_constraints(cpuc, reg);
3475
3476         reg = &event->hw.branch_reg;
3477         if (reg->idx != EXTRA_REG_NONE)
3478                 __intel_shared_reg_put_constraints(cpuc, reg);
3479 }
3480
3481 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
3482                                         struct perf_event *event)
3483 {
3484         intel_put_shared_regs_event_constraints(cpuc, event);
3485
3486         /*
3487          * is PMU has exclusive counter restrictions, then
3488          * all events are subject to and must call the
3489          * put_excl_constraints() routine
3490          */
3491         if (cpuc->excl_cntrs)
3492                 intel_put_excl_constraints(cpuc, event);
3493 }
3494
3495 static void intel_pebs_aliases_core2(struct perf_event *event)
3496 {
3497         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3498                 /*
3499                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3500                  * (0x003c) so that we can use it with PEBS.
3501                  *
3502                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3503                  * PEBS capable. However we can use INST_RETIRED.ANY_P
3504                  * (0x00c0), which is a PEBS capable event, to get the same
3505                  * count.
3506                  *
3507                  * INST_RETIRED.ANY_P counts the number of cycles that retires
3508                  * CNTMASK instructions. By setting CNTMASK to a value (16)
3509                  * larger than the maximum number of instructions that can be
3510                  * retired per cycle (4) and then inverting the condition, we
3511                  * count all cycles that retire 16 or less instructions, which
3512                  * is every cycle.
3513                  *
3514                  * Thereby we gain a PEBS capable cycle counter.
3515                  */
3516                 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3517
3518                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3519                 event->hw.config = alt_config;
3520         }
3521 }
3522
3523 static void intel_pebs_aliases_snb(struct perf_event *event)
3524 {
3525         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3526                 /*
3527                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3528                  * (0x003c) so that we can use it with PEBS.
3529                  *
3530                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3531                  * PEBS capable. However we can use UOPS_RETIRED.ALL
3532                  * (0x01c2), which is a PEBS capable event, to get the same
3533                  * count.
3534                  *
3535                  * UOPS_RETIRED.ALL counts the number of cycles that retires
3536                  * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3537                  * larger than the maximum number of micro-ops that can be
3538                  * retired per cycle (4) and then inverting the condition, we
3539                  * count all cycles that retire 16 or less micro-ops, which
3540                  * is every cycle.
3541                  *
3542                  * Thereby we gain a PEBS capable cycle counter.
3543                  */
3544                 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3545
3546                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3547                 event->hw.config = alt_config;
3548         }
3549 }
3550
3551 static void intel_pebs_aliases_precdist(struct perf_event *event)
3552 {
3553         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3554                 /*
3555                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3556                  * (0x003c) so that we can use it with PEBS.
3557                  *
3558                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3559                  * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3560                  * (0x01c0), which is a PEBS capable event, to get the same
3561                  * count.
3562                  *
3563                  * The PREC_DIST event has special support to minimize sample
3564                  * shadowing effects. One drawback is that it can be
3565                  * only programmed on counter 1, but that seems like an
3566                  * acceptable trade off.
3567                  */
3568                 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3569
3570                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3571                 event->hw.config = alt_config;
3572         }
3573 }
3574
3575 static void intel_pebs_aliases_ivb(struct perf_event *event)
3576 {
3577         if (event->attr.precise_ip < 3)
3578                 return intel_pebs_aliases_snb(event);
3579         return intel_pebs_aliases_precdist(event);
3580 }
3581
3582 static void intel_pebs_aliases_skl(struct perf_event *event)
3583 {
3584         if (event->attr.precise_ip < 3)
3585                 return intel_pebs_aliases_core2(event);
3586         return intel_pebs_aliases_precdist(event);
3587 }
3588
3589 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3590 {
3591         unsigned long flags = x86_pmu.large_pebs_flags;
3592
3593         if (event->attr.use_clockid)
3594                 flags &= ~PERF_SAMPLE_TIME;
3595         if (!event->attr.exclude_kernel)
3596                 flags &= ~PERF_SAMPLE_REGS_USER;
3597         if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
3598                 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3599         return flags;
3600 }
3601
3602 static int intel_pmu_bts_config(struct perf_event *event)
3603 {
3604         struct perf_event_attr *attr = &event->attr;
3605
3606         if (unlikely(intel_pmu_has_bts(event))) {
3607                 /* BTS is not supported by this architecture. */
3608                 if (!x86_pmu.bts_active)
3609                         return -EOPNOTSUPP;
3610
3611                 /* BTS is currently only allowed for user-mode. */
3612                 if (!attr->exclude_kernel)
3613                         return -EOPNOTSUPP;
3614
3615                 /* BTS is not allowed for precise events. */
3616                 if (attr->precise_ip)
3617                         return -EOPNOTSUPP;
3618
3619                 /* disallow bts if conflicting events are present */
3620                 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3621                         return -EBUSY;
3622
3623                 event->destroy = hw_perf_lbr_event_destroy;
3624         }
3625
3626         return 0;
3627 }
3628
3629 static int core_pmu_hw_config(struct perf_event *event)
3630 {
3631         int ret = x86_pmu_hw_config(event);
3632
3633         if (ret)
3634                 return ret;
3635
3636         return intel_pmu_bts_config(event);
3637 }
3638
3639 #define INTEL_TD_METRIC_AVAILABLE_MAX   (INTEL_TD_METRIC_RETIRING + \
3640                                          ((x86_pmu.num_topdown_events - 1) << 8))
3641
3642 static bool is_available_metric_event(struct perf_event *event)
3643 {
3644         return is_metric_event(event) &&
3645                 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX;
3646 }
3647
3648 static inline bool is_mem_loads_event(struct perf_event *event)
3649 {
3650         return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01);
3651 }
3652
3653 static inline bool is_mem_loads_aux_event(struct perf_event *event)
3654 {
3655         return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82);
3656 }
3657
3658 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx)
3659 {
3660         union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap);
3661
3662         return test_bit(idx, (unsigned long *)&intel_cap->capabilities);
3663 }
3664
3665 static int intel_pmu_hw_config(struct perf_event *event)
3666 {
3667         int ret = x86_pmu_hw_config(event);
3668
3669         if (ret)
3670                 return ret;
3671
3672         ret = intel_pmu_bts_config(event);
3673         if (ret)
3674                 return ret;
3675
3676         if (event->attr.precise_ip) {
3677                 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
3678                         event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
3679                         if (!(event->attr.sample_type &
3680                               ~intel_pmu_large_pebs_flags(event))) {
3681                                 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
3682                                 event->attach_state |= PERF_ATTACH_SCHED_CB;
3683                         }
3684                 }
3685                 if (x86_pmu.pebs_aliases)
3686                         x86_pmu.pebs_aliases(event);
3687
3688                 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN)
3689                         event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY;
3690         }
3691
3692         if (needs_branch_stack(event)) {
3693                 ret = intel_pmu_setup_lbr_filter(event);
3694                 if (ret)
3695                         return ret;
3696                 event->attach_state |= PERF_ATTACH_SCHED_CB;
3697
3698                 /*
3699                  * BTS is set up earlier in this path, so don't account twice
3700                  */
3701                 if (!unlikely(intel_pmu_has_bts(event))) {
3702                         /* disallow lbr if conflicting events are present */
3703                         if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3704                                 return -EBUSY;
3705
3706                         event->destroy = hw_perf_lbr_event_destroy;
3707                 }
3708         }
3709
3710         if (event->attr.aux_output) {
3711                 if (!event->attr.precise_ip)
3712                         return -EINVAL;
3713
3714                 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
3715         }
3716
3717         if (event->attr.type != PERF_TYPE_RAW)
3718                 return 0;
3719
3720         /*
3721          * Config Topdown slots and metric events
3722          *
3723          * The slots event on Fixed Counter 3 can support sampling,
3724          * which will be handled normally in x86_perf_event_update().
3725          *
3726          * Metric events don't support sampling and require being paired
3727          * with a slots event as group leader. When the slots event
3728          * is used in a metrics group, it too cannot support sampling.
3729          */
3730         if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) {
3731                 if (event->attr.config1 || event->attr.config2)
3732                         return -EINVAL;
3733
3734                 /*
3735                  * The TopDown metrics events and slots event don't
3736                  * support any filters.
3737                  */
3738                 if (event->attr.config & X86_ALL_EVENT_FLAGS)
3739                         return -EINVAL;
3740
3741                 if (is_available_metric_event(event)) {
3742                         struct perf_event *leader = event->group_leader;
3743
3744                         /* The metric events don't support sampling. */
3745                         if (is_sampling_event(event))
3746                                 return -EINVAL;
3747
3748                         /* The metric events require a slots group leader. */
3749                         if (!is_slots_event(leader))
3750                                 return -EINVAL;
3751
3752                         /*
3753                          * The leader/SLOTS must not be a sampling event for
3754                          * metric use; hardware requires it starts at 0 when used
3755                          * in conjunction with MSR_PERF_METRICS.
3756                          */
3757                         if (is_sampling_event(leader))
3758                                 return -EINVAL;
3759
3760                         event->event_caps |= PERF_EV_CAP_SIBLING;
3761                         /*
3762                          * Only once we have a METRICs sibling do we
3763                          * need TopDown magic.
3764                          */
3765                         leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
3766                         event->hw.flags  |= PERF_X86_EVENT_TOPDOWN;
3767                 }
3768         }
3769
3770         /*
3771          * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR
3772          * doesn't function quite right. As a work-around it needs to always be
3773          * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82).
3774          * The actual count of this second event is irrelevant it just needs
3775          * to be active to make the first event function correctly.
3776          *
3777          * In a group, the auxiliary event must be in front of the load latency
3778          * event. The rule is to simplify the implementation of the check.
3779          * That's because perf cannot have a complete group at the moment.
3780          */
3781         if (x86_pmu.flags & PMU_FL_MEM_LOADS_AUX &&
3782             (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) &&
3783             is_mem_loads_event(event)) {
3784                 struct perf_event *leader = event->group_leader;
3785                 struct perf_event *sibling = NULL;
3786
3787                 if (!is_mem_loads_aux_event(leader)) {
3788                         for_each_sibling_event(sibling, leader) {
3789                                 if (is_mem_loads_aux_event(sibling))
3790                                         break;
3791                         }
3792                         if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list))
3793                                 return -ENODATA;
3794                 }
3795         }
3796
3797         if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
3798                 return 0;
3799
3800         if (x86_pmu.version < 3)
3801                 return -EINVAL;
3802
3803         ret = perf_allow_cpu(&event->attr);
3804         if (ret)
3805                 return ret;
3806
3807         event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
3808
3809         return 0;
3810 }
3811
3812 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
3813 {
3814         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3815         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3816         u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
3817
3818         arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
3819         arr[0].host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
3820         arr[0].guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask;
3821         if (x86_pmu.flags & PMU_FL_PEBS_ALL)
3822                 arr[0].guest &= ~cpuc->pebs_enabled;
3823         else
3824                 arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
3825         *nr = 1;
3826
3827         if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) {
3828                 /*
3829                  * If PMU counter has PEBS enabled it is not enough to
3830                  * disable counter on a guest entry since PEBS memory
3831                  * write can overshoot guest entry and corrupt guest
3832                  * memory. Disabling PEBS solves the problem.
3833                  *
3834                  * Don't do this if the CPU already enforces it.
3835                  */
3836                 arr[1].msr = MSR_IA32_PEBS_ENABLE;
3837                 arr[1].host = cpuc->pebs_enabled;
3838                 arr[1].guest = 0;
3839                 *nr = 2;
3840         }
3841
3842         return arr;
3843 }
3844
3845 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
3846 {
3847         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3848         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3849         int idx;
3850
3851         for (idx = 0; idx < x86_pmu.num_counters; idx++)  {
3852                 struct perf_event *event = cpuc->events[idx];
3853
3854                 arr[idx].msr = x86_pmu_config_addr(idx);
3855                 arr[idx].host = arr[idx].guest = 0;
3856
3857                 if (!test_bit(idx, cpuc->active_mask))
3858                         continue;
3859
3860                 arr[idx].host = arr[idx].guest =
3861                         event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
3862
3863                 if (event->attr.exclude_host)
3864                         arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3865                 else if (event->attr.exclude_guest)
3866                         arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3867         }
3868
3869         *nr = x86_pmu.num_counters;
3870         return arr;
3871 }
3872
3873 static void core_pmu_enable_event(struct perf_event *event)
3874 {
3875         if (!event->attr.exclude_host)
3876                 x86_pmu_enable_event(event);
3877 }
3878
3879 static void core_pmu_enable_all(int added)
3880 {
3881         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3882         int idx;
3883
3884         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3885                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
3886
3887                 if (!test_bit(idx, cpuc->active_mask) ||
3888                                 cpuc->events[idx]->attr.exclude_host)
3889                         continue;
3890
3891                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
3892         }
3893 }
3894
3895 static int hsw_hw_config(struct perf_event *event)
3896 {
3897         int ret = intel_pmu_hw_config(event);
3898
3899         if (ret)
3900                 return ret;
3901         if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
3902                 return 0;
3903         event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
3904
3905         /*
3906          * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
3907          * PEBS or in ANY thread mode. Since the results are non-sensical forbid
3908          * this combination.
3909          */
3910         if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
3911              ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
3912               event->attr.precise_ip > 0))
3913                 return -EOPNOTSUPP;
3914
3915         if (event_is_checkpointed(event)) {
3916                 /*
3917                  * Sampling of checkpointed events can cause situations where
3918                  * the CPU constantly aborts because of a overflow, which is
3919                  * then checkpointed back and ignored. Forbid checkpointing
3920                  * for sampling.
3921                  *
3922                  * But still allow a long sampling period, so that perf stat
3923                  * from KVM works.
3924                  */
3925                 if (event->attr.sample_period > 0 &&
3926                     event->attr.sample_period < 0x7fffffff)
3927                         return -EOPNOTSUPP;
3928         }
3929         return 0;
3930 }
3931
3932 static struct event_constraint counter0_constraint =
3933                         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
3934
3935 static struct event_constraint counter2_constraint =
3936                         EVENT_CONSTRAINT(0, 0x4, 0);
3937
3938 static struct event_constraint fixed0_constraint =
3939                         FIXED_EVENT_CONSTRAINT(0x00c0, 0);
3940
3941 static struct event_constraint fixed0_counter0_constraint =
3942                         INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
3943
3944 static struct event_constraint *
3945 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3946                           struct perf_event *event)
3947 {
3948         struct event_constraint *c;
3949
3950         c = intel_get_event_constraints(cpuc, idx, event);
3951
3952         /* Handle special quirk on in_tx_checkpointed only in counter 2 */
3953         if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
3954                 if (c->idxmsk64 & (1U << 2))
3955                         return &counter2_constraint;
3956                 return &emptyconstraint;
3957         }
3958
3959         return c;
3960 }
3961
3962 static struct event_constraint *
3963 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3964                           struct perf_event *event)
3965 {
3966         /*
3967          * Fixed counter 0 has less skid.
3968          * Force instruction:ppp in Fixed counter 0
3969          */
3970         if ((event->attr.precise_ip == 3) &&
3971             constraint_match(&fixed0_constraint, event->hw.config))
3972                 return &fixed0_constraint;
3973
3974         return hsw_get_event_constraints(cpuc, idx, event);
3975 }
3976
3977 static struct event_constraint *
3978 spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3979                           struct perf_event *event)
3980 {
3981         struct event_constraint *c;
3982
3983         c = icl_get_event_constraints(cpuc, idx, event);
3984
3985         /*
3986          * The :ppp indicates the Precise Distribution (PDist) facility, which
3987          * is only supported on the GP counter 0. If a :ppp event which is not
3988          * available on the GP counter 0, error out.
3989          */
3990         if (event->attr.precise_ip == 3) {
3991                 if (c->idxmsk64 & BIT_ULL(0))
3992                         return &counter0_constraint;
3993
3994                 return &emptyconstraint;
3995         }
3996
3997         return c;
3998 }
3999
4000 static struct event_constraint *
4001 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4002                           struct perf_event *event)
4003 {
4004         struct event_constraint *c;
4005
4006         /* :ppp means to do reduced skid PEBS which is PMC0 only. */
4007         if (event->attr.precise_ip == 3)
4008                 return &counter0_constraint;
4009
4010         c = intel_get_event_constraints(cpuc, idx, event);
4011
4012         return c;
4013 }
4014
4015 static struct event_constraint *
4016 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4017                           struct perf_event *event)
4018 {
4019         struct event_constraint *c;
4020
4021         /*
4022          * :ppp means to do reduced skid PEBS,
4023          * which is available on PMC0 and fixed counter 0.
4024          */
4025         if (event->attr.precise_ip == 3) {
4026                 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
4027                 if (constraint_match(&fixed0_constraint, event->hw.config))
4028                         return &fixed0_counter0_constraint;
4029
4030                 return &counter0_constraint;
4031         }
4032
4033         c = intel_get_event_constraints(cpuc, idx, event);
4034
4035         return c;
4036 }
4037
4038 static bool allow_tsx_force_abort = true;
4039
4040 static struct event_constraint *
4041 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4042                           struct perf_event *event)
4043 {
4044         struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
4045
4046         /*
4047          * Without TFA we must not use PMC3.
4048          */
4049         if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
4050                 c = dyn_constraint(cpuc, c, idx);
4051                 c->idxmsk64 &= ~(1ULL << 3);
4052                 c->weight--;
4053         }
4054
4055         return c;
4056 }
4057
4058 /*
4059  * Broadwell:
4060  *
4061  * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
4062  * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
4063  * the two to enforce a minimum period of 128 (the smallest value that has bits
4064  * 0-5 cleared and >= 100).
4065  *
4066  * Because of how the code in x86_perf_event_set_period() works, the truncation
4067  * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
4068  * to make up for the 'lost' events due to carrying the 'error' in period_left.
4069  *
4070  * Therefore the effective (average) period matches the requested period,
4071  * despite coarser hardware granularity.
4072  */
4073 static u64 bdw_limit_period(struct perf_event *event, u64 left)
4074 {
4075         if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
4076                         X86_CONFIG(.event=0xc0, .umask=0x01)) {
4077                 if (left < 128)
4078                         left = 128;
4079                 left &= ~0x3fULL;
4080         }
4081         return left;
4082 }
4083
4084 static u64 nhm_limit_period(struct perf_event *event, u64 left)
4085 {
4086         return max(left, 32ULL);
4087 }
4088
4089 static u64 spr_limit_period(struct perf_event *event, u64 left)
4090 {
4091         if (event->attr.precise_ip == 3)
4092                 return max(left, 128ULL);
4093
4094         return left;
4095 }
4096
4097 PMU_FORMAT_ATTR(event,  "config:0-7"    );
4098 PMU_FORMAT_ATTR(umask,  "config:8-15"   );
4099 PMU_FORMAT_ATTR(edge,   "config:18"     );
4100 PMU_FORMAT_ATTR(pc,     "config:19"     );
4101 PMU_FORMAT_ATTR(any,    "config:21"     ); /* v3 + */
4102 PMU_FORMAT_ATTR(inv,    "config:23"     );
4103 PMU_FORMAT_ATTR(cmask,  "config:24-31"  );
4104 PMU_FORMAT_ATTR(in_tx,  "config:32");
4105 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
4106
4107 static struct attribute *intel_arch_formats_attr[] = {
4108         &format_attr_event.attr,
4109         &format_attr_umask.attr,
4110         &format_attr_edge.attr,
4111         &format_attr_pc.attr,
4112         &format_attr_inv.attr,
4113         &format_attr_cmask.attr,
4114         NULL,
4115 };
4116
4117 ssize_t intel_event_sysfs_show(char *page, u64 config)
4118 {
4119         u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
4120
4121         return x86_event_sysfs_show(page, config, event);
4122 }
4123
4124 static struct intel_shared_regs *allocate_shared_regs(int cpu)
4125 {
4126         struct intel_shared_regs *regs;
4127         int i;
4128
4129         regs = kzalloc_node(sizeof(struct intel_shared_regs),
4130                             GFP_KERNEL, cpu_to_node(cpu));
4131         if (regs) {
4132                 /*
4133                  * initialize the locks to keep lockdep happy
4134                  */
4135                 for (i = 0; i < EXTRA_REG_MAX; i++)
4136                         raw_spin_lock_init(&regs->regs[i].lock);
4137
4138                 regs->core_id = -1;
4139         }
4140         return regs;
4141 }
4142
4143 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
4144 {
4145         struct intel_excl_cntrs *c;
4146
4147         c = kzalloc_node(sizeof(struct intel_excl_cntrs),
4148                          GFP_KERNEL, cpu_to_node(cpu));
4149         if (c) {
4150                 raw_spin_lock_init(&c->lock);
4151                 c->core_id = -1;
4152         }
4153         return c;
4154 }
4155
4156
4157 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
4158 {
4159         cpuc->pebs_record_size = x86_pmu.pebs_record_size;
4160
4161         if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
4162                 cpuc->shared_regs = allocate_shared_regs(cpu);
4163                 if (!cpuc->shared_regs)
4164                         goto err;
4165         }
4166
4167         if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) {
4168                 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
4169
4170                 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
4171                 if (!cpuc->constraint_list)
4172                         goto err_shared_regs;
4173         }
4174
4175         if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4176                 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
4177                 if (!cpuc->excl_cntrs)
4178                         goto err_constraint_list;
4179
4180                 cpuc->excl_thread_id = 0;
4181         }
4182
4183         return 0;
4184
4185 err_constraint_list:
4186         kfree(cpuc->constraint_list);
4187         cpuc->constraint_list = NULL;
4188
4189 err_shared_regs:
4190         kfree(cpuc->shared_regs);
4191         cpuc->shared_regs = NULL;
4192
4193 err:
4194         return -ENOMEM;
4195 }
4196
4197 static int intel_pmu_cpu_prepare(int cpu)
4198 {
4199         return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
4200 }
4201
4202 static void flip_smm_bit(void *data)
4203 {
4204         unsigned long set = *(unsigned long *)data;
4205
4206         if (set > 0) {
4207                 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
4208                             DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4209         } else {
4210                 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
4211                               DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4212         }
4213 }
4214
4215 static void intel_pmu_cpu_starting(int cpu)
4216 {
4217         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4218         int core_id = topology_core_id(cpu);
4219         int i;
4220
4221         init_debug_store_on_cpu(cpu);
4222         /*
4223          * Deal with CPUs that don't clear their LBRs on power-up.
4224          */
4225         intel_pmu_lbr_reset();
4226
4227         cpuc->lbr_sel = NULL;
4228
4229         if (x86_pmu.flags & PMU_FL_TFA) {
4230                 WARN_ON_ONCE(cpuc->tfa_shadow);
4231                 cpuc->tfa_shadow = ~0ULL;
4232                 intel_set_tfa(cpuc, false);
4233         }
4234
4235         if (x86_pmu.version > 1)
4236                 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
4237
4238         /*
4239          * Disable perf metrics if any added CPU doesn't support it.
4240          *
4241          * Turn off the check for a hybrid architecture, because the
4242          * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate
4243          * the architecture features. The perf metrics is a model-specific
4244          * feature for now. The corresponding bit should always be 0 on
4245          * a hybrid platform, e.g., Alder Lake.
4246          */
4247         if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) {
4248                 union perf_capabilities perf_cap;
4249
4250                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
4251                 if (!perf_cap.perf_metrics) {
4252                         x86_pmu.intel_cap.perf_metrics = 0;
4253                         x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
4254                 }
4255         }
4256
4257         if (!cpuc->shared_regs)
4258                 return;
4259
4260         if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
4261                 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4262                         struct intel_shared_regs *pc;
4263
4264                         pc = per_cpu(cpu_hw_events, i).shared_regs;
4265                         if (pc && pc->core_id == core_id) {
4266                                 cpuc->kfree_on_online[0] = cpuc->shared_regs;
4267                                 cpuc->shared_regs = pc;
4268                                 break;
4269                         }
4270                 }
4271                 cpuc->shared_regs->core_id = core_id;
4272                 cpuc->shared_regs->refcnt++;
4273         }
4274
4275         if (x86_pmu.lbr_sel_map)
4276                 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
4277
4278         if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4279                 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4280                         struct cpu_hw_events *sibling;
4281                         struct intel_excl_cntrs *c;
4282
4283                         sibling = &per_cpu(cpu_hw_events, i);
4284                         c = sibling->excl_cntrs;
4285                         if (c && c->core_id == core_id) {
4286                                 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
4287                                 cpuc->excl_cntrs = c;
4288                                 if (!sibling->excl_thread_id)
4289                                         cpuc->excl_thread_id = 1;
4290                                 break;
4291                         }
4292                 }
4293                 cpuc->excl_cntrs->core_id = core_id;
4294                 cpuc->excl_cntrs->refcnt++;
4295         }
4296 }
4297
4298 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
4299 {
4300         struct intel_excl_cntrs *c;
4301
4302         c = cpuc->excl_cntrs;
4303         if (c) {
4304                 if (c->core_id == -1 || --c->refcnt == 0)
4305                         kfree(c);
4306                 cpuc->excl_cntrs = NULL;
4307         }
4308
4309         kfree(cpuc->constraint_list);
4310         cpuc->constraint_list = NULL;
4311 }
4312
4313 static void intel_pmu_cpu_dying(int cpu)
4314 {
4315         fini_debug_store_on_cpu(cpu);
4316 }
4317
4318 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
4319 {
4320         struct intel_shared_regs *pc;
4321
4322         pc = cpuc->shared_regs;
4323         if (pc) {
4324                 if (pc->core_id == -1 || --pc->refcnt == 0)
4325                         kfree(pc);
4326                 cpuc->shared_regs = NULL;
4327         }
4328
4329         free_excl_cntrs(cpuc);
4330 }
4331
4332 static void intel_pmu_cpu_dead(int cpu)
4333 {
4334         intel_cpuc_finish(&per_cpu(cpu_hw_events, cpu));
4335 }
4336
4337 static void intel_pmu_sched_task(struct perf_event_context *ctx,
4338                                  bool sched_in)
4339 {
4340         intel_pmu_pebs_sched_task(ctx, sched_in);
4341         intel_pmu_lbr_sched_task(ctx, sched_in);
4342 }
4343
4344 static void intel_pmu_swap_task_ctx(struct perf_event_context *prev,
4345                                     struct perf_event_context *next)
4346 {
4347         intel_pmu_lbr_swap_task_ctx(prev, next);
4348 }
4349
4350 static int intel_pmu_check_period(struct perf_event *event, u64 value)
4351 {
4352         return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
4353 }
4354
4355 static int intel_pmu_aux_output_match(struct perf_event *event)
4356 {
4357         if (!x86_pmu.intel_cap.pebs_output_pt_available)
4358                 return 0;
4359
4360         return is_intel_pt_event(event);
4361 }
4362
4363 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
4364
4365 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
4366
4367 PMU_FORMAT_ATTR(frontend, "config1:0-23");
4368
4369 static struct attribute *intel_arch3_formats_attr[] = {
4370         &format_attr_event.attr,
4371         &format_attr_umask.attr,
4372         &format_attr_edge.attr,
4373         &format_attr_pc.attr,
4374         &format_attr_any.attr,
4375         &format_attr_inv.attr,
4376         &format_attr_cmask.attr,
4377         NULL,
4378 };
4379
4380 static struct attribute *hsw_format_attr[] = {
4381         &format_attr_in_tx.attr,
4382         &format_attr_in_tx_cp.attr,
4383         &format_attr_offcore_rsp.attr,
4384         &format_attr_ldlat.attr,
4385         NULL
4386 };
4387
4388 static struct attribute *nhm_format_attr[] = {
4389         &format_attr_offcore_rsp.attr,
4390         &format_attr_ldlat.attr,
4391         NULL
4392 };
4393
4394 static struct attribute *slm_format_attr[] = {
4395         &format_attr_offcore_rsp.attr,
4396         NULL
4397 };
4398
4399 static struct attribute *skl_format_attr[] = {
4400         &format_attr_frontend.attr,
4401         NULL,
4402 };
4403
4404 static __initconst const struct x86_pmu core_pmu = {
4405         .name                   = "core",
4406         .handle_irq             = x86_pmu_handle_irq,
4407         .disable_all            = x86_pmu_disable_all,
4408         .enable_all             = core_pmu_enable_all,
4409         .enable                 = core_pmu_enable_event,
4410         .disable                = x86_pmu_disable_event,
4411         .hw_config              = core_pmu_hw_config,
4412         .schedule_events        = x86_schedule_events,
4413         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
4414         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
4415         .event_map              = intel_pmu_event_map,
4416         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
4417         .apic                   = 1,
4418         .large_pebs_flags       = LARGE_PEBS_FLAGS,
4419
4420         /*
4421          * Intel PMCs cannot be accessed sanely above 32-bit width,
4422          * so we install an artificial 1<<31 period regardless of
4423          * the generic event period:
4424          */
4425         .max_period             = (1ULL<<31) - 1,
4426         .get_event_constraints  = intel_get_event_constraints,
4427         .put_event_constraints  = intel_put_event_constraints,
4428         .event_constraints      = intel_core_event_constraints,
4429         .guest_get_msrs         = core_guest_get_msrs,
4430         .format_attrs           = intel_arch_formats_attr,
4431         .events_sysfs_show      = intel_event_sysfs_show,
4432
4433         /*
4434          * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
4435          * together with PMU version 1 and thus be using core_pmu with
4436          * shared_regs. We need following callbacks here to allocate
4437          * it properly.
4438          */
4439         .cpu_prepare            = intel_pmu_cpu_prepare,
4440         .cpu_starting           = intel_pmu_cpu_starting,
4441         .cpu_dying              = intel_pmu_cpu_dying,
4442         .cpu_dead               = intel_pmu_cpu_dead,
4443
4444         .check_period           = intel_pmu_check_period,
4445
4446         .lbr_reset              = intel_pmu_lbr_reset_64,
4447         .lbr_read               = intel_pmu_lbr_read_64,
4448         .lbr_save               = intel_pmu_lbr_save,
4449         .lbr_restore            = intel_pmu_lbr_restore,
4450 };
4451
4452 static __initconst const struct x86_pmu intel_pmu = {
4453         .name                   = "Intel",
4454         .handle_irq             = intel_pmu_handle_irq,
4455         .disable_all            = intel_pmu_disable_all,
4456         .enable_all             = intel_pmu_enable_all,
4457         .enable                 = intel_pmu_enable_event,
4458         .disable                = intel_pmu_disable_event,
4459         .add                    = intel_pmu_add_event,
4460         .del                    = intel_pmu_del_event,
4461         .read                   = intel_pmu_read_event,
4462         .hw_config              = intel_pmu_hw_config,
4463         .schedule_events        = x86_schedule_events,
4464         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
4465         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
4466         .event_map              = intel_pmu_event_map,
4467         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
4468         .apic                   = 1,
4469         .large_pebs_flags       = LARGE_PEBS_FLAGS,
4470         /*
4471          * Intel PMCs cannot be accessed sanely above 32 bit width,
4472          * so we install an artificial 1<<31 period regardless of
4473          * the generic event period:
4474          */
4475         .max_period             = (1ULL << 31) - 1,
4476         .get_event_constraints  = intel_get_event_constraints,
4477         .put_event_constraints  = intel_put_event_constraints,
4478         .pebs_aliases           = intel_pebs_aliases_core2,
4479
4480         .format_attrs           = intel_arch3_formats_attr,
4481         .events_sysfs_show      = intel_event_sysfs_show,
4482
4483         .cpu_prepare            = intel_pmu_cpu_prepare,
4484         .cpu_starting           = intel_pmu_cpu_starting,
4485         .cpu_dying              = intel_pmu_cpu_dying,
4486         .cpu_dead               = intel_pmu_cpu_dead,
4487
4488         .guest_get_msrs         = intel_guest_get_msrs,
4489         .sched_task             = intel_pmu_sched_task,
4490         .swap_task_ctx          = intel_pmu_swap_task_ctx,
4491
4492         .check_period           = intel_pmu_check_period,
4493
4494         .aux_output_match       = intel_pmu_aux_output_match,
4495
4496         .lbr_reset              = intel_pmu_lbr_reset_64,
4497         .lbr_read               = intel_pmu_lbr_read_64,
4498         .lbr_save               = intel_pmu_lbr_save,
4499         .lbr_restore            = intel_pmu_lbr_restore,
4500 };
4501
4502 static __init void intel_clovertown_quirk(void)
4503 {
4504         /*
4505          * PEBS is unreliable due to:
4506          *
4507          *   AJ67  - PEBS may experience CPL leaks
4508          *   AJ68  - PEBS PMI may be delayed by one event
4509          *   AJ69  - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
4510          *   AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
4511          *
4512          * AJ67 could be worked around by restricting the OS/USR flags.
4513          * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
4514          *
4515          * AJ106 could possibly be worked around by not allowing LBR
4516          *       usage from PEBS, including the fixup.
4517          * AJ68  could possibly be worked around by always programming
4518          *       a pebs_event_reset[0] value and coping with the lost events.
4519          *
4520          * But taken together it might just make sense to not enable PEBS on
4521          * these chips.
4522          */
4523         pr_warn("PEBS disabled due to CPU errata\n");
4524         x86_pmu.pebs = 0;
4525         x86_pmu.pebs_constraints = NULL;
4526 }
4527
4528 static const struct x86_cpu_desc isolation_ucodes[] = {
4529         INTEL_CPU_DESC(INTEL_FAM6_HASWELL,               3, 0x0000001f),
4530         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L,             1, 0x0000001e),
4531         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G,             1, 0x00000015),
4532         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X,             2, 0x00000037),
4533         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X,             4, 0x0000000a),
4534         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL,             4, 0x00000023),
4535         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G,           1, 0x00000014),
4536         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,           2, 0x00000010),
4537         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,           3, 0x07000009),
4538         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,           4, 0x0f000009),
4539         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,           5, 0x0e000002),
4540         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X,           2, 0x0b000014),
4541         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             3, 0x00000021),
4542         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             4, 0x00000000),
4543         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             5, 0x00000000),
4544         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             6, 0x00000000),
4545         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             7, 0x00000000),
4546         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L,             3, 0x0000007c),
4547         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE,               3, 0x0000007c),
4548         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,              9, 0x0000004e),
4549         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,            9, 0x0000004e),
4550         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,           10, 0x0000004e),
4551         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,           11, 0x0000004e),
4552         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,           12, 0x0000004e),
4553         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,             10, 0x0000004e),
4554         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,             11, 0x0000004e),
4555         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,             12, 0x0000004e),
4556         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,             13, 0x0000004e),
4557         {}
4558 };
4559
4560 static void intel_check_pebs_isolation(void)
4561 {
4562         x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes);
4563 }
4564
4565 static __init void intel_pebs_isolation_quirk(void)
4566 {
4567         WARN_ON_ONCE(x86_pmu.check_microcode);
4568         x86_pmu.check_microcode = intel_check_pebs_isolation;
4569         intel_check_pebs_isolation();
4570 }
4571
4572 static const struct x86_cpu_desc pebs_ucodes[] = {
4573         INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE,          7, 0x00000028),
4574         INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X,        6, 0x00000618),
4575         INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X,        7, 0x0000070c),
4576         {}
4577 };
4578
4579 static bool intel_snb_pebs_broken(void)
4580 {
4581         return !x86_cpu_has_min_microcode_rev(pebs_ucodes);
4582 }
4583
4584 static void intel_snb_check_microcode(void)
4585 {
4586         if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
4587                 return;
4588
4589         /*
4590          * Serialized by the microcode lock..
4591          */
4592         if (x86_pmu.pebs_broken) {
4593                 pr_info("PEBS enabled due to microcode update\n");
4594                 x86_pmu.pebs_broken = 0;
4595         } else {
4596                 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
4597                 x86_pmu.pebs_broken = 1;
4598         }
4599 }
4600
4601 static bool is_lbr_from(unsigned long msr)
4602 {
4603         unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
4604
4605         return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
4606 }
4607
4608 /*
4609  * Under certain circumstances, access certain MSR may cause #GP.
4610  * The function tests if the input MSR can be safely accessed.
4611  */
4612 static bool check_msr(unsigned long msr, u64 mask)
4613 {
4614         u64 val_old, val_new, val_tmp;
4615
4616         /*
4617          * Disable the check for real HW, so we don't
4618          * mess with potentionaly enabled registers:
4619          */
4620         if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
4621                 return true;
4622
4623         /*
4624          * Read the current value, change it and read it back to see if it
4625          * matches, this is needed to detect certain hardware emulators
4626          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
4627          */
4628         if (rdmsrl_safe(msr, &val_old))
4629                 return false;
4630
4631         /*
4632          * Only change the bits which can be updated by wrmsrl.
4633          */
4634         val_tmp = val_old ^ mask;
4635
4636         if (is_lbr_from(msr))
4637                 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
4638
4639         if (wrmsrl_safe(msr, val_tmp) ||
4640             rdmsrl_safe(msr, &val_new))
4641                 return false;
4642
4643         /*
4644          * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
4645          * should equal rdmsrl()'s even with the quirk.
4646          */
4647         if (val_new != val_tmp)
4648                 return false;
4649
4650         if (is_lbr_from(msr))
4651                 val_old = lbr_from_signext_quirk_wr(val_old);
4652
4653         /* Here it's sure that the MSR can be safely accessed.
4654          * Restore the old value and return.
4655          */
4656         wrmsrl(msr, val_old);
4657
4658         return true;
4659 }
4660
4661 static __init void intel_sandybridge_quirk(void)
4662 {
4663         x86_pmu.check_microcode = intel_snb_check_microcode;
4664         cpus_read_lock();
4665         intel_snb_check_microcode();
4666         cpus_read_unlock();
4667 }
4668
4669 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
4670         { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
4671         { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
4672         { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
4673         { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
4674         { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
4675         { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
4676         { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
4677 };
4678
4679 static __init void intel_arch_events_quirk(void)
4680 {
4681         int bit;
4682
4683         /* disable event that reported as not presend by cpuid */
4684         for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
4685                 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
4686                 pr_warn("CPUID marked event: \'%s\' unavailable\n",
4687                         intel_arch_events_map[bit].name);
4688         }
4689 }
4690
4691 static __init void intel_nehalem_quirk(void)
4692 {
4693         union cpuid10_ebx ebx;
4694
4695         ebx.full = x86_pmu.events_maskl;
4696         if (ebx.split.no_branch_misses_retired) {
4697                 /*
4698                  * Erratum AAJ80 detected, we work it around by using
4699                  * the BR_MISP_EXEC.ANY event. This will over-count
4700                  * branch-misses, but it's still much better than the
4701                  * architectural event which is often completely bogus:
4702                  */
4703                 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
4704                 ebx.split.no_branch_misses_retired = 0;
4705                 x86_pmu.events_maskl = ebx.full;
4706                 pr_info("CPU erratum AAJ80 worked around\n");
4707         }
4708 }
4709
4710 /*
4711  * enable software workaround for errata:
4712  * SNB: BJ122
4713  * IVB: BV98
4714  * HSW: HSD29
4715  *
4716  * Only needed when HT is enabled. However detecting
4717  * if HT is enabled is difficult (model specific). So instead,
4718  * we enable the workaround in the early boot, and verify if
4719  * it is needed in a later initcall phase once we have valid
4720  * topology information to check if HT is actually enabled
4721  */
4722 static __init void intel_ht_bug(void)
4723 {
4724         x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
4725
4726         x86_pmu.start_scheduling = intel_start_scheduling;
4727         x86_pmu.commit_scheduling = intel_commit_scheduling;
4728         x86_pmu.stop_scheduling = intel_stop_scheduling;
4729 }
4730
4731 EVENT_ATTR_STR(mem-loads,       mem_ld_hsw,     "event=0xcd,umask=0x1,ldlat=3");
4732 EVENT_ATTR_STR(mem-stores,      mem_st_hsw,     "event=0xd0,umask=0x82")
4733
4734 /* Haswell special events */
4735 EVENT_ATTR_STR(tx-start,        tx_start,       "event=0xc9,umask=0x1");
4736 EVENT_ATTR_STR(tx-commit,       tx_commit,      "event=0xc9,umask=0x2");
4737 EVENT_ATTR_STR(tx-abort,        tx_abort,       "event=0xc9,umask=0x4");
4738 EVENT_ATTR_STR(tx-capacity,     tx_capacity,    "event=0x54,umask=0x2");
4739 EVENT_ATTR_STR(tx-conflict,     tx_conflict,    "event=0x54,umask=0x1");
4740 EVENT_ATTR_STR(el-start,        el_start,       "event=0xc8,umask=0x1");
4741 EVENT_ATTR_STR(el-commit,       el_commit,      "event=0xc8,umask=0x2");
4742 EVENT_ATTR_STR(el-abort,        el_abort,       "event=0xc8,umask=0x4");
4743 EVENT_ATTR_STR(el-capacity,     el_capacity,    "event=0x54,umask=0x2");
4744 EVENT_ATTR_STR(el-conflict,     el_conflict,    "event=0x54,umask=0x1");
4745 EVENT_ATTR_STR(cycles-t,        cycles_t,       "event=0x3c,in_tx=1");
4746 EVENT_ATTR_STR(cycles-ct,       cycles_ct,      "event=0x3c,in_tx=1,in_tx_cp=1");
4747
4748 static struct attribute *hsw_events_attrs[] = {
4749         EVENT_PTR(td_slots_issued),
4750         EVENT_PTR(td_slots_retired),
4751         EVENT_PTR(td_fetch_bubbles),
4752         EVENT_PTR(td_total_slots),
4753         EVENT_PTR(td_total_slots_scale),
4754         EVENT_PTR(td_recovery_bubbles),
4755         EVENT_PTR(td_recovery_bubbles_scale),
4756         NULL
4757 };
4758
4759 static struct attribute *hsw_mem_events_attrs[] = {
4760         EVENT_PTR(mem_ld_hsw),
4761         EVENT_PTR(mem_st_hsw),
4762         NULL,
4763 };
4764
4765 static struct attribute *hsw_tsx_events_attrs[] = {
4766         EVENT_PTR(tx_start),
4767         EVENT_PTR(tx_commit),
4768         EVENT_PTR(tx_abort),
4769         EVENT_PTR(tx_capacity),
4770         EVENT_PTR(tx_conflict),
4771         EVENT_PTR(el_start),
4772         EVENT_PTR(el_commit),
4773         EVENT_PTR(el_abort),
4774         EVENT_PTR(el_capacity),
4775         EVENT_PTR(el_conflict),
4776         EVENT_PTR(cycles_t),
4777         EVENT_PTR(cycles_ct),
4778         NULL
4779 };
4780
4781 EVENT_ATTR_STR(tx-capacity-read,  tx_capacity_read,  "event=0x54,umask=0x80");
4782 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
4783 EVENT_ATTR_STR(el-capacity-read,  el_capacity_read,  "event=0x54,umask=0x80");
4784 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
4785
4786 static struct attribute *icl_events_attrs[] = {
4787         EVENT_PTR(mem_ld_hsw),
4788         EVENT_PTR(mem_st_hsw),
4789         NULL,
4790 };
4791
4792 static struct attribute *icl_td_events_attrs[] = {
4793         EVENT_PTR(slots),
4794         EVENT_PTR(td_retiring),
4795         EVENT_PTR(td_bad_spec),
4796         EVENT_PTR(td_fe_bound),
4797         EVENT_PTR(td_be_bound),
4798         NULL,
4799 };
4800
4801 static struct attribute *icl_tsx_events_attrs[] = {
4802         EVENT_PTR(tx_start),
4803         EVENT_PTR(tx_abort),
4804         EVENT_PTR(tx_commit),
4805         EVENT_PTR(tx_capacity_read),
4806         EVENT_PTR(tx_capacity_write),
4807         EVENT_PTR(tx_conflict),
4808         EVENT_PTR(el_start),
4809         EVENT_PTR(el_abort),
4810         EVENT_PTR(el_commit),
4811         EVENT_PTR(el_capacity_read),
4812         EVENT_PTR(el_capacity_write),
4813         EVENT_PTR(el_conflict),
4814         EVENT_PTR(cycles_t),
4815         EVENT_PTR(cycles_ct),
4816         NULL,
4817 };
4818
4819
4820 EVENT_ATTR_STR(mem-stores,      mem_st_spr,     "event=0xcd,umask=0x2");
4821 EVENT_ATTR_STR(mem-loads-aux,   mem_ld_aux,     "event=0x03,umask=0x82");
4822
4823 static struct attribute *spr_events_attrs[] = {
4824         EVENT_PTR(mem_ld_hsw),
4825         EVENT_PTR(mem_st_spr),
4826         EVENT_PTR(mem_ld_aux),
4827         NULL,
4828 };
4829
4830 static struct attribute *spr_td_events_attrs[] = {
4831         EVENT_PTR(slots),
4832         EVENT_PTR(td_retiring),
4833         EVENT_PTR(td_bad_spec),
4834         EVENT_PTR(td_fe_bound),
4835         EVENT_PTR(td_be_bound),
4836         EVENT_PTR(td_heavy_ops),
4837         EVENT_PTR(td_br_mispredict),
4838         EVENT_PTR(td_fetch_lat),
4839         EVENT_PTR(td_mem_bound),
4840         NULL,
4841 };
4842
4843 static struct attribute *spr_tsx_events_attrs[] = {
4844         EVENT_PTR(tx_start),
4845         EVENT_PTR(tx_abort),
4846         EVENT_PTR(tx_commit),
4847         EVENT_PTR(tx_capacity_read),
4848         EVENT_PTR(tx_capacity_write),
4849         EVENT_PTR(tx_conflict),
4850         EVENT_PTR(cycles_t),
4851         EVENT_PTR(cycles_ct),
4852         NULL,
4853 };
4854
4855 static ssize_t freeze_on_smi_show(struct device *cdev,
4856                                   struct device_attribute *attr,
4857                                   char *buf)
4858 {
4859         return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
4860 }
4861
4862 static DEFINE_MUTEX(freeze_on_smi_mutex);
4863
4864 static ssize_t freeze_on_smi_store(struct device *cdev,
4865                                    struct device_attribute *attr,
4866                                    const char *buf, size_t count)
4867 {
4868         unsigned long val;
4869         ssize_t ret;
4870
4871         ret = kstrtoul(buf, 0, &val);
4872         if (ret)
4873                 return ret;
4874
4875         if (val > 1)
4876                 return -EINVAL;
4877
4878         mutex_lock(&freeze_on_smi_mutex);
4879
4880         if (x86_pmu.attr_freeze_on_smi == val)
4881                 goto done;
4882
4883         x86_pmu.attr_freeze_on_smi = val;
4884
4885         get_online_cpus();
4886         on_each_cpu(flip_smm_bit, &val, 1);
4887         put_online_cpus();
4888 done:
4889         mutex_unlock(&freeze_on_smi_mutex);
4890
4891         return count;
4892 }
4893
4894 static void update_tfa_sched(void *ignored)
4895 {
4896         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4897
4898         /*
4899          * check if PMC3 is used
4900          * and if so force schedule out for all event types all contexts
4901          */
4902         if (test_bit(3, cpuc->active_mask))
4903                 perf_pmu_resched(x86_get_pmu(smp_processor_id()));
4904 }
4905
4906 static ssize_t show_sysctl_tfa(struct device *cdev,
4907                               struct device_attribute *attr,
4908                               char *buf)
4909 {
4910         return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
4911 }
4912
4913 static ssize_t set_sysctl_tfa(struct device *cdev,
4914                               struct device_attribute *attr,
4915                               const char *buf, size_t count)
4916 {
4917         bool val;
4918         ssize_t ret;
4919
4920         ret = kstrtobool(buf, &val);
4921         if (ret)
4922                 return ret;
4923
4924         /* no change */
4925         if (val == allow_tsx_force_abort)
4926                 return count;
4927
4928         allow_tsx_force_abort = val;
4929
4930         get_online_cpus();
4931         on_each_cpu(update_tfa_sched, NULL, 1);
4932         put_online_cpus();
4933
4934         return count;
4935 }
4936
4937
4938 static DEVICE_ATTR_RW(freeze_on_smi);
4939
4940 static ssize_t branches_show(struct device *cdev,
4941                              struct device_attribute *attr,
4942                              char *buf)
4943 {
4944         return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
4945 }
4946
4947 static DEVICE_ATTR_RO(branches);
4948
4949 static struct attribute *lbr_attrs[] = {
4950         &dev_attr_branches.attr,
4951         NULL
4952 };
4953
4954 static char pmu_name_str[30];
4955
4956 static ssize_t pmu_name_show(struct device *cdev,
4957                              struct device_attribute *attr,
4958                              char *buf)
4959 {
4960         return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str);
4961 }
4962
4963 static DEVICE_ATTR_RO(pmu_name);
4964
4965 static struct attribute *intel_pmu_caps_attrs[] = {
4966        &dev_attr_pmu_name.attr,
4967        NULL
4968 };
4969
4970 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
4971                    show_sysctl_tfa,
4972                    set_sysctl_tfa);
4973
4974 static struct attribute *intel_pmu_attrs[] = {
4975         &dev_attr_freeze_on_smi.attr,
4976         &dev_attr_allow_tsx_force_abort.attr,
4977         NULL,
4978 };
4979
4980 static umode_t
4981 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4982 {
4983         return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
4984 }
4985
4986 static umode_t
4987 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4988 {
4989         return x86_pmu.pebs ? attr->mode : 0;
4990 }
4991
4992 static umode_t
4993 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4994 {
4995         return x86_pmu.lbr_nr ? attr->mode : 0;
4996 }
4997
4998 static umode_t
4999 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5000 {
5001         return x86_pmu.version >= 2 ? attr->mode : 0;
5002 }
5003
5004 static umode_t
5005 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5006 {
5007         if (attr == &dev_attr_allow_tsx_force_abort.attr)
5008                 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
5009
5010         return attr->mode;
5011 }
5012
5013 static struct attribute_group group_events_td  = {
5014         .name = "events",
5015 };
5016
5017 static struct attribute_group group_events_mem = {
5018         .name       = "events",
5019         .is_visible = pebs_is_visible,
5020 };
5021
5022 static struct attribute_group group_events_tsx = {
5023         .name       = "events",
5024         .is_visible = tsx_is_visible,
5025 };
5026
5027 static struct attribute_group group_caps_gen = {
5028         .name  = "caps",
5029         .attrs = intel_pmu_caps_attrs,
5030 };
5031
5032 static struct attribute_group group_caps_lbr = {
5033         .name       = "caps",
5034         .attrs      = lbr_attrs,
5035         .is_visible = lbr_is_visible,
5036 };
5037
5038 static struct attribute_group group_format_extra = {
5039         .name       = "format",
5040         .is_visible = exra_is_visible,
5041 };
5042
5043 static struct attribute_group group_format_extra_skl = {
5044         .name       = "format",
5045         .is_visible = exra_is_visible,
5046 };
5047
5048 static struct attribute_group group_default = {
5049         .attrs      = intel_pmu_attrs,
5050         .is_visible = default_is_visible,
5051 };
5052
5053 static const struct attribute_group *attr_update[] = {
5054         &group_events_td,
5055         &group_events_mem,
5056         &group_events_tsx,
5057         &group_caps_gen,
5058         &group_caps_lbr,
5059         &group_format_extra,
5060         &group_format_extra_skl,
5061         &group_default,
5062         NULL,
5063 };
5064
5065 static struct attribute *empty_attrs;
5066
5067 __init int intel_pmu_init(void)
5068 {
5069         struct attribute **extra_skl_attr = &empty_attrs;
5070         struct attribute **extra_attr = &empty_attrs;
5071         struct attribute **td_attr    = &empty_attrs;
5072         struct attribute **mem_attr   = &empty_attrs;
5073         struct attribute **tsx_attr   = &empty_attrs;
5074         union cpuid10_edx edx;
5075         union cpuid10_eax eax;
5076         union cpuid10_ebx ebx;
5077         struct event_constraint *c;
5078         unsigned int fixed_mask;
5079         struct extra_reg *er;
5080         bool pmem = false;
5081         int version, i;
5082         char *name;
5083
5084         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
5085                 switch (boot_cpu_data.x86) {
5086                 case 0x6:
5087                         return p6_pmu_init();
5088                 case 0xb:
5089                         return knc_pmu_init();
5090                 case 0xf:
5091                         return p4_pmu_init();
5092                 }
5093                 return -ENODEV;
5094         }
5095
5096         /*
5097          * Check whether the Architectural PerfMon supports
5098          * Branch Misses Retired hw_event or not.
5099          */
5100         cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
5101         if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
5102                 return -ENODEV;
5103
5104         version = eax.split.version_id;
5105         if (version < 2)
5106                 x86_pmu = core_pmu;
5107         else
5108                 x86_pmu = intel_pmu;
5109
5110         x86_pmu.version                 = version;
5111         x86_pmu.num_counters            = eax.split.num_counters;
5112         x86_pmu.cntval_bits             = eax.split.bit_width;
5113         x86_pmu.cntval_mask             = (1ULL << eax.split.bit_width) - 1;
5114
5115         x86_pmu.events_maskl            = ebx.full;
5116         x86_pmu.events_mask_len         = eax.split.mask_length;
5117
5118         x86_pmu.max_pebs_events         = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
5119
5120         /*
5121          * Quirk: v2 perfmon does not report fixed-purpose events, so
5122          * assume at least 3 events, when not running in a hypervisor:
5123          */
5124         if (version > 1 && version < 5) {
5125                 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
5126
5127                 x86_pmu.num_counters_fixed =
5128                         max((int)edx.split.num_counters_fixed, assume);
5129
5130                 fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1;
5131         } else if (version >= 5)
5132                 x86_pmu.num_counters_fixed = fls(fixed_mask);
5133
5134         if (boot_cpu_has(X86_FEATURE_PDCM)) {
5135                 u64 capabilities;
5136
5137                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
5138                 x86_pmu.intel_cap.capabilities = capabilities;
5139         }
5140
5141         if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
5142                 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
5143                 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
5144         }
5145
5146         if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
5147                 intel_pmu_arch_lbr_init();
5148
5149         intel_ds_init();
5150
5151         x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
5152
5153         if (version >= 5) {
5154                 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated;
5155                 if (x86_pmu.intel_cap.anythread_deprecated)
5156                         pr_cont(" AnyThread deprecated, ");
5157         }
5158
5159         /*
5160          * Install the hw-cache-events table:
5161          */
5162         switch (boot_cpu_data.x86_model) {
5163         case INTEL_FAM6_CORE_YONAH:
5164                 pr_cont("Core events, ");
5165                 name = "core";
5166                 break;
5167
5168         case INTEL_FAM6_CORE2_MEROM:
5169                 x86_add_quirk(intel_clovertown_quirk);
5170                 fallthrough;
5171
5172         case INTEL_FAM6_CORE2_MEROM_L:
5173         case INTEL_FAM6_CORE2_PENRYN:
5174         case INTEL_FAM6_CORE2_DUNNINGTON:
5175                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
5176                        sizeof(hw_cache_event_ids));
5177
5178                 intel_pmu_lbr_init_core();
5179
5180                 x86_pmu.event_constraints = intel_core2_event_constraints;
5181                 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
5182                 pr_cont("Core2 events, ");
5183                 name = "core2";
5184                 break;
5185
5186         case INTEL_FAM6_NEHALEM:
5187         case INTEL_FAM6_NEHALEM_EP:
5188         case INTEL_FAM6_NEHALEM_EX:
5189                 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
5190                        sizeof(hw_cache_event_ids));
5191                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
5192                        sizeof(hw_cache_extra_regs));
5193
5194                 intel_pmu_lbr_init_nhm();
5195
5196                 x86_pmu.event_constraints = intel_nehalem_event_constraints;
5197                 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
5198                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
5199                 x86_pmu.extra_regs = intel_nehalem_extra_regs;
5200                 x86_pmu.limit_period = nhm_limit_period;
5201
5202                 mem_attr = nhm_mem_events_attrs;
5203
5204                 /* UOPS_ISSUED.STALLED_CYCLES */
5205                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5206                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5207                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
5208                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5209                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
5210
5211                 intel_pmu_pebs_data_source_nhm();
5212                 x86_add_quirk(intel_nehalem_quirk);
5213                 x86_pmu.pebs_no_tlb = 1;
5214                 extra_attr = nhm_format_attr;
5215
5216                 pr_cont("Nehalem events, ");
5217                 name = "nehalem";
5218                 break;
5219
5220         case INTEL_FAM6_ATOM_BONNELL:
5221         case INTEL_FAM6_ATOM_BONNELL_MID:
5222         case INTEL_FAM6_ATOM_SALTWELL:
5223         case INTEL_FAM6_ATOM_SALTWELL_MID:
5224         case INTEL_FAM6_ATOM_SALTWELL_TABLET:
5225                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
5226                        sizeof(hw_cache_event_ids));
5227
5228                 intel_pmu_lbr_init_atom();
5229
5230                 x86_pmu.event_constraints = intel_gen_event_constraints;
5231                 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
5232                 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
5233                 pr_cont("Atom events, ");
5234                 name = "bonnell";
5235                 break;
5236
5237         case INTEL_FAM6_ATOM_SILVERMONT:
5238         case INTEL_FAM6_ATOM_SILVERMONT_D:
5239         case INTEL_FAM6_ATOM_SILVERMONT_MID:
5240         case INTEL_FAM6_ATOM_AIRMONT:
5241         case INTEL_FAM6_ATOM_AIRMONT_MID:
5242                 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
5243                         sizeof(hw_cache_event_ids));
5244                 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
5245                        sizeof(hw_cache_extra_regs));
5246
5247                 intel_pmu_lbr_init_slm();
5248
5249                 x86_pmu.event_constraints = intel_slm_event_constraints;
5250                 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
5251                 x86_pmu.extra_regs = intel_slm_extra_regs;
5252                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5253                 td_attr = slm_events_attrs;
5254                 extra_attr = slm_format_attr;
5255                 pr_cont("Silvermont events, ");
5256                 name = "silvermont";
5257                 break;
5258
5259         case INTEL_FAM6_ATOM_GOLDMONT:
5260         case INTEL_FAM6_ATOM_GOLDMONT_D:
5261                 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
5262                        sizeof(hw_cache_event_ids));
5263                 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
5264                        sizeof(hw_cache_extra_regs));
5265
5266                 intel_pmu_lbr_init_skl();
5267
5268                 x86_pmu.event_constraints = intel_slm_event_constraints;
5269                 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
5270                 x86_pmu.extra_regs = intel_glm_extra_regs;
5271                 /*
5272                  * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5273                  * for precise cycles.
5274                  * :pp is identical to :ppp
5275                  */
5276                 x86_pmu.pebs_aliases = NULL;
5277                 x86_pmu.pebs_prec_dist = true;
5278                 x86_pmu.lbr_pt_coexist = true;
5279                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5280                 td_attr = glm_events_attrs;
5281                 extra_attr = slm_format_attr;
5282                 pr_cont("Goldmont events, ");
5283                 name = "goldmont";
5284                 break;
5285
5286         case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5287                 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5288                        sizeof(hw_cache_event_ids));
5289                 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
5290                        sizeof(hw_cache_extra_regs));
5291
5292                 intel_pmu_lbr_init_skl();
5293
5294                 x86_pmu.event_constraints = intel_slm_event_constraints;
5295                 x86_pmu.extra_regs = intel_glm_extra_regs;
5296                 /*
5297                  * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5298                  * for precise cycles.
5299                  */
5300                 x86_pmu.pebs_aliases = NULL;
5301                 x86_pmu.pebs_prec_dist = true;
5302                 x86_pmu.lbr_pt_coexist = true;
5303                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5304                 x86_pmu.flags |= PMU_FL_PEBS_ALL;
5305                 x86_pmu.get_event_constraints = glp_get_event_constraints;
5306                 td_attr = glm_events_attrs;
5307                 /* Goldmont Plus has 4-wide pipeline */
5308                 event_attr_td_total_slots_scale_glm.event_str = "4";
5309                 extra_attr = slm_format_attr;
5310                 pr_cont("Goldmont plus events, ");
5311                 name = "goldmont_plus";
5312                 break;
5313
5314         case INTEL_FAM6_ATOM_TREMONT_D:
5315         case INTEL_FAM6_ATOM_TREMONT:
5316         case INTEL_FAM6_ATOM_TREMONT_L:
5317                 x86_pmu.late_ack = true;
5318                 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5319                        sizeof(hw_cache_event_ids));
5320                 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
5321                        sizeof(hw_cache_extra_regs));
5322                 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
5323
5324                 intel_pmu_lbr_init_skl();
5325
5326                 x86_pmu.event_constraints = intel_slm_event_constraints;
5327                 x86_pmu.extra_regs = intel_tnt_extra_regs;
5328                 /*
5329                  * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5330                  * for precise cycles.
5331                  */
5332                 x86_pmu.pebs_aliases = NULL;
5333                 x86_pmu.pebs_prec_dist = true;
5334                 x86_pmu.lbr_pt_coexist = true;
5335                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5336                 x86_pmu.get_event_constraints = tnt_get_event_constraints;
5337                 td_attr = tnt_events_attrs;
5338                 extra_attr = slm_format_attr;
5339                 pr_cont("Tremont events, ");
5340                 name = "Tremont";
5341                 break;
5342
5343         case INTEL_FAM6_WESTMERE:
5344         case INTEL_FAM6_WESTMERE_EP:
5345         case INTEL_FAM6_WESTMERE_EX:
5346                 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
5347                        sizeof(hw_cache_event_ids));
5348                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
5349                        sizeof(hw_cache_extra_regs));
5350
5351                 intel_pmu_lbr_init_nhm();
5352
5353                 x86_pmu.event_constraints = intel_westmere_event_constraints;
5354                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
5355                 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
5356                 x86_pmu.extra_regs = intel_westmere_extra_regs;
5357                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5358
5359                 mem_attr = nhm_mem_events_attrs;
5360
5361                 /* UOPS_ISSUED.STALLED_CYCLES */
5362                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5363                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5364                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
5365                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5366                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
5367
5368                 intel_pmu_pebs_data_source_nhm();
5369                 extra_attr = nhm_format_attr;
5370                 pr_cont("Westmere events, ");
5371                 name = "westmere";
5372                 break;
5373
5374         case INTEL_FAM6_SANDYBRIDGE:
5375         case INTEL_FAM6_SANDYBRIDGE_X:
5376                 x86_add_quirk(intel_sandybridge_quirk);
5377                 x86_add_quirk(intel_ht_bug);
5378                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
5379                        sizeof(hw_cache_event_ids));
5380                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
5381                        sizeof(hw_cache_extra_regs));
5382
5383                 intel_pmu_lbr_init_snb();
5384
5385                 x86_pmu.event_constraints = intel_snb_event_constraints;
5386                 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
5387                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
5388                 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
5389                         x86_pmu.extra_regs = intel_snbep_extra_regs;
5390                 else
5391                         x86_pmu.extra_regs = intel_snb_extra_regs;
5392
5393
5394                 /* all extra regs are per-cpu when HT is on */
5395                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5396                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5397
5398                 td_attr  = snb_events_attrs;
5399                 mem_attr = snb_mem_events_attrs;
5400
5401                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
5402                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5403                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5404                 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
5405                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5406                         X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
5407
5408                 extra_attr = nhm_format_attr;
5409
5410                 pr_cont("SandyBridge events, ");
5411                 name = "sandybridge";
5412                 break;
5413
5414         case INTEL_FAM6_IVYBRIDGE:
5415         case INTEL_FAM6_IVYBRIDGE_X:
5416                 x86_add_quirk(intel_ht_bug);
5417                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
5418                        sizeof(hw_cache_event_ids));
5419                 /* dTLB-load-misses on IVB is different than SNB */
5420                 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
5421
5422                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
5423                        sizeof(hw_cache_extra_regs));
5424
5425                 intel_pmu_lbr_init_snb();
5426
5427                 x86_pmu.event_constraints = intel_ivb_event_constraints;
5428                 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
5429                 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5430                 x86_pmu.pebs_prec_dist = true;
5431                 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
5432                         x86_pmu.extra_regs = intel_snbep_extra_regs;
5433                 else
5434                         x86_pmu.extra_regs = intel_snb_extra_regs;
5435                 /* all extra regs are per-cpu when HT is on */
5436                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5437                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5438
5439                 td_attr  = snb_events_attrs;
5440                 mem_attr = snb_mem_events_attrs;
5441
5442                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
5443                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5444                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5445
5446                 extra_attr = nhm_format_attr;
5447
5448                 pr_cont("IvyBridge events, ");
5449                 name = "ivybridge";
5450                 break;
5451
5452
5453         case INTEL_FAM6_HASWELL:
5454         case INTEL_FAM6_HASWELL_X:
5455         case INTEL_FAM6_HASWELL_L:
5456         case INTEL_FAM6_HASWELL_G:
5457                 x86_add_quirk(intel_ht_bug);
5458                 x86_add_quirk(intel_pebs_isolation_quirk);
5459                 x86_pmu.late_ack = true;
5460                 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5461                 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5462
5463                 intel_pmu_lbr_init_hsw();
5464
5465                 x86_pmu.event_constraints = intel_hsw_event_constraints;
5466                 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
5467                 x86_pmu.extra_regs = intel_snbep_extra_regs;
5468                 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5469                 x86_pmu.pebs_prec_dist = true;
5470                 /* all extra regs are per-cpu when HT is on */
5471                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5472                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5473
5474                 x86_pmu.hw_config = hsw_hw_config;
5475                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5476                 x86_pmu.lbr_double_abort = true;
5477                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5478                         hsw_format_attr : nhm_format_attr;
5479                 td_attr  = hsw_events_attrs;
5480                 mem_attr = hsw_mem_events_attrs;
5481                 tsx_attr = hsw_tsx_events_attrs;
5482                 pr_cont("Haswell events, ");
5483                 name = "haswell";
5484                 break;
5485
5486         case INTEL_FAM6_BROADWELL:
5487         case INTEL_FAM6_BROADWELL_D:
5488         case INTEL_FAM6_BROADWELL_G:
5489         case INTEL_FAM6_BROADWELL_X:
5490                 x86_add_quirk(intel_pebs_isolation_quirk);
5491                 x86_pmu.late_ack = true;
5492                 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5493                 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5494
5495                 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
5496                 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
5497                                                                          BDW_L3_MISS|HSW_SNOOP_DRAM;
5498                 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
5499                                                                           HSW_SNOOP_DRAM;
5500                 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
5501                                                                              BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
5502                 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
5503                                                                               BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
5504
5505                 intel_pmu_lbr_init_hsw();
5506
5507                 x86_pmu.event_constraints = intel_bdw_event_constraints;
5508                 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
5509                 x86_pmu.extra_regs = intel_snbep_extra_regs;
5510                 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5511                 x86_pmu.pebs_prec_dist = true;
5512                 /* all extra regs are per-cpu when HT is on */
5513                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5514                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5515
5516                 x86_pmu.hw_config = hsw_hw_config;
5517                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5518                 x86_pmu.limit_period = bdw_limit_period;
5519                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5520                         hsw_format_attr : nhm_format_attr;
5521                 td_attr  = hsw_events_attrs;
5522                 mem_attr = hsw_mem_events_attrs;
5523                 tsx_attr = hsw_tsx_events_attrs;
5524                 pr_cont("Broadwell events, ");
5525                 name = "broadwell";
5526                 break;
5527
5528         case INTEL_FAM6_XEON_PHI_KNL:
5529         case INTEL_FAM6_XEON_PHI_KNM:
5530                 memcpy(hw_cache_event_ids,
5531                        slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5532                 memcpy(hw_cache_extra_regs,
5533                        knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5534                 intel_pmu_lbr_init_knl();
5535
5536                 x86_pmu.event_constraints = intel_slm_event_constraints;
5537                 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
5538                 x86_pmu.extra_regs = intel_knl_extra_regs;
5539
5540                 /* all extra regs are per-cpu when HT is on */
5541                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5542                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5543                 extra_attr = slm_format_attr;
5544                 pr_cont("Knights Landing/Mill events, ");
5545                 name = "knights-landing";
5546                 break;
5547
5548         case INTEL_FAM6_SKYLAKE_X:
5549                 pmem = true;
5550                 fallthrough;
5551         case INTEL_FAM6_SKYLAKE_L:
5552         case INTEL_FAM6_SKYLAKE:
5553         case INTEL_FAM6_KABYLAKE_L:
5554         case INTEL_FAM6_KABYLAKE:
5555         case INTEL_FAM6_COMETLAKE_L:
5556         case INTEL_FAM6_COMETLAKE:
5557                 x86_add_quirk(intel_pebs_isolation_quirk);
5558                 x86_pmu.late_ack = true;
5559                 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5560                 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5561                 intel_pmu_lbr_init_skl();
5562
5563                 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
5564                 event_attr_td_recovery_bubbles.event_str_noht =
5565                         "event=0xd,umask=0x1,cmask=1";
5566                 event_attr_td_recovery_bubbles.event_str_ht =
5567                         "event=0xd,umask=0x1,cmask=1,any=1";
5568
5569                 x86_pmu.event_constraints = intel_skl_event_constraints;
5570                 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
5571                 x86_pmu.extra_regs = intel_skl_extra_regs;
5572                 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
5573                 x86_pmu.pebs_prec_dist = true;
5574                 /* all extra regs are per-cpu when HT is on */
5575                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5576                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5577
5578                 x86_pmu.hw_config = hsw_hw_config;
5579                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5580                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5581                         hsw_format_attr : nhm_format_attr;
5582                 extra_skl_attr = skl_format_attr;
5583                 td_attr  = hsw_events_attrs;
5584                 mem_attr = hsw_mem_events_attrs;
5585                 tsx_attr = hsw_tsx_events_attrs;
5586                 intel_pmu_pebs_data_source_skl(pmem);
5587
5588                 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
5589                         x86_pmu.flags |= PMU_FL_TFA;
5590                         x86_pmu.get_event_constraints = tfa_get_event_constraints;
5591                         x86_pmu.enable_all = intel_tfa_pmu_enable_all;
5592                         x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
5593                 }
5594
5595                 pr_cont("Skylake events, ");
5596                 name = "skylake";
5597                 break;
5598
5599         case INTEL_FAM6_ICELAKE_X:
5600         case INTEL_FAM6_ICELAKE_D:
5601                 pmem = true;
5602                 fallthrough;
5603         case INTEL_FAM6_ICELAKE_L:
5604         case INTEL_FAM6_ICELAKE:
5605         case INTEL_FAM6_TIGERLAKE_L:
5606         case INTEL_FAM6_TIGERLAKE:
5607         case INTEL_FAM6_ROCKETLAKE:
5608                 x86_pmu.late_ack = true;
5609                 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5610                 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5611                 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
5612                 intel_pmu_lbr_init_skl();
5613
5614                 x86_pmu.event_constraints = intel_icl_event_constraints;
5615                 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
5616                 x86_pmu.extra_regs = intel_icl_extra_regs;
5617                 x86_pmu.pebs_aliases = NULL;
5618                 x86_pmu.pebs_prec_dist = true;
5619                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5620                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5621
5622                 x86_pmu.hw_config = hsw_hw_config;
5623                 x86_pmu.get_event_constraints = icl_get_event_constraints;
5624                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5625                         hsw_format_attr : nhm_format_attr;
5626                 extra_skl_attr = skl_format_attr;
5627                 mem_attr = icl_events_attrs;
5628                 td_attr = icl_td_events_attrs;
5629                 tsx_attr = icl_tsx_events_attrs;
5630                 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
5631                 x86_pmu.lbr_pt_coexist = true;
5632                 intel_pmu_pebs_data_source_skl(pmem);
5633                 x86_pmu.num_topdown_events = 4;
5634                 x86_pmu.update_topdown_event = icl_update_topdown_event;
5635                 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;
5636                 pr_cont("Icelake events, ");
5637                 name = "icelake";
5638                 break;
5639
5640         case INTEL_FAM6_SAPPHIRERAPIDS_X:
5641                 pmem = true;
5642                 x86_pmu.late_ack = true;
5643                 memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5644                 memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5645
5646                 x86_pmu.event_constraints = intel_spr_event_constraints;
5647                 x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;
5648                 x86_pmu.extra_regs = intel_spr_extra_regs;
5649                 x86_pmu.limit_period = spr_limit_period;
5650                 x86_pmu.pebs_aliases = NULL;
5651                 x86_pmu.pebs_prec_dist = true;
5652                 x86_pmu.pebs_block = true;
5653                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5654                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5655                 x86_pmu.flags |= PMU_FL_PEBS_ALL;
5656                 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
5657                 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
5658
5659                 x86_pmu.hw_config = hsw_hw_config;
5660                 x86_pmu.get_event_constraints = spr_get_event_constraints;
5661                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5662                         hsw_format_attr : nhm_format_attr;
5663                 extra_skl_attr = skl_format_attr;
5664                 mem_attr = spr_events_attrs;
5665                 td_attr = spr_td_events_attrs;
5666                 tsx_attr = spr_tsx_events_attrs;
5667                 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
5668                 x86_pmu.lbr_pt_coexist = true;
5669                 intel_pmu_pebs_data_source_skl(pmem);
5670                 x86_pmu.num_topdown_events = 8;
5671                 x86_pmu.update_topdown_event = icl_update_topdown_event;
5672                 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;
5673                 pr_cont("Sapphire Rapids events, ");
5674                 name = "sapphire_rapids";
5675                 break;
5676
5677         default:
5678                 switch (x86_pmu.version) {
5679                 case 1:
5680                         x86_pmu.event_constraints = intel_v1_event_constraints;
5681                         pr_cont("generic architected perfmon v1, ");
5682                         name = "generic_arch_v1";
5683                         break;
5684                 default:
5685                         /*
5686                          * default constraints for v2 and up
5687                          */
5688                         x86_pmu.event_constraints = intel_gen_event_constraints;
5689                         pr_cont("generic architected perfmon, ");
5690                         name = "generic_arch_v2+";
5691                         break;
5692                 }
5693         }
5694
5695         snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
5696
5697
5698         group_events_td.attrs  = td_attr;
5699         group_events_mem.attrs = mem_attr;
5700         group_events_tsx.attrs = tsx_attr;
5701         group_format_extra.attrs = extra_attr;
5702         group_format_extra_skl.attrs = extra_skl_attr;
5703
5704         x86_pmu.attr_update = attr_update;
5705
5706         if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
5707                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
5708                      x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
5709                 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
5710         }
5711         x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1;
5712
5713         if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
5714                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
5715                      x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
5716                 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
5717         }
5718
5719         x86_pmu.intel_ctrl |= (u64)fixed_mask << INTEL_PMC_IDX_FIXED;
5720
5721         /* AnyThread may be deprecated on arch perfmon v5 or later */
5722         if (x86_pmu.intel_cap.anythread_deprecated)
5723                 x86_pmu.format_attrs = intel_arch_formats_attr;
5724
5725         if (x86_pmu.event_constraints) {
5726                 /*
5727                  * event on fixed counter2 (REF_CYCLES) only works on this
5728                  * counter, so do not extend mask to generic counters
5729                  */
5730                 for_each_event_constraint(c, x86_pmu.event_constraints) {
5731                         /*
5732                          * Don't extend the topdown slots and metrics
5733                          * events to the generic counters.
5734                          */
5735                         if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
5736                                 /*
5737                                  * Disable topdown slots and metrics events,
5738                                  * if slots event is not in CPUID.
5739                                  */
5740                                 if (!(INTEL_PMC_MSK_FIXED_SLOTS & x86_pmu.intel_ctrl))
5741                                         c->idxmsk64 = 0;
5742                                 c->weight = hweight64(c->idxmsk64);
5743                                 continue;
5744                         }
5745
5746                         if (c->cmask == FIXED_EVENT_FLAGS) {
5747                                 /* Disabled fixed counters which are not in CPUID */
5748                                 c->idxmsk64 &= x86_pmu.intel_ctrl;
5749
5750                                 if (c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES)
5751                                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
5752                         }
5753                         c->idxmsk64 &=
5754                                 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
5755                         c->weight = hweight64(c->idxmsk64);
5756                 }
5757         }
5758
5759         /*
5760          * Access LBR MSR may cause #GP under certain circumstances.
5761          * E.g. KVM doesn't support LBR MSR
5762          * Check all LBT MSR here.
5763          * Disable LBR access if any LBR MSRs can not be accessed.
5764          */
5765         if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
5766                 x86_pmu.lbr_nr = 0;
5767         for (i = 0; i < x86_pmu.lbr_nr; i++) {
5768                 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
5769                       check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
5770                         x86_pmu.lbr_nr = 0;
5771         }
5772
5773         if (x86_pmu.lbr_nr)
5774                 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
5775
5776         /*
5777          * Access extra MSR may cause #GP under certain circumstances.
5778          * E.g. KVM doesn't support offcore event
5779          * Check all extra_regs here.
5780          */
5781         if (x86_pmu.extra_regs) {
5782                 for (er = x86_pmu.extra_regs; er->msr; er++) {
5783                         er->extra_msr_access = check_msr(er->msr, 0x11UL);
5784                         /* Disable LBR select mapping */
5785                         if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
5786                                 x86_pmu.lbr_sel_map = NULL;
5787                 }
5788         }
5789
5790         /* Support full width counters using alternative MSR range */
5791         if (x86_pmu.intel_cap.full_width_write) {
5792                 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
5793                 x86_pmu.perfctr = MSR_IA32_PMC0;
5794                 pr_cont("full-width counters, ");
5795         }
5796
5797         if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics)
5798                 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
5799
5800         return 0;
5801 }
5802
5803 /*
5804  * HT bug: phase 2 init
5805  * Called once we have valid topology information to check
5806  * whether or not HT is enabled
5807  * If HT is off, then we disable the workaround
5808  */
5809 static __init int fixup_ht_bug(void)
5810 {
5811         int c;
5812         /*
5813          * problem not present on this CPU model, nothing to do
5814          */
5815         if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
5816                 return 0;
5817
5818         if (topology_max_smt_threads() > 1) {
5819                 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
5820                 return 0;
5821         }
5822
5823         cpus_read_lock();
5824
5825         hardlockup_detector_perf_stop();
5826
5827         x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
5828
5829         x86_pmu.start_scheduling = NULL;
5830         x86_pmu.commit_scheduling = NULL;
5831         x86_pmu.stop_scheduling = NULL;
5832
5833         hardlockup_detector_perf_restart();
5834
5835         for_each_online_cpu(c)
5836                 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
5837
5838         cpus_read_unlock();
5839         pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
5840         return 0;
5841 }
5842 subsys_initcall(fixup_ht_bug)