4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/stddef.h>
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/export.h>
15 #include <linux/nmi.h>
17 #include <asm/cpufeature.h>
18 #include <asm/hardirq.h>
19 #include <asm/intel-family.h>
21 #include <asm/cpu_device_id.h>
23 #include "../perf_event.h"
26 * Intel PerfMon, used on Core and later.
28 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
30 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
31 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
32 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
33 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
34 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
35 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
36 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
37 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
40 static struct event_constraint intel_core_event_constraints[] __read_mostly =
42 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
43 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
44 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
45 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
46 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
47 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
51 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
53 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
54 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
55 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
56 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
57 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
58 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
59 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
60 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
61 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
62 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
63 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
64 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
65 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
69 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
71 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
72 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
73 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
74 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
75 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
76 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
77 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
78 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
79 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
80 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
81 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
85 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
87 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
88 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
89 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
93 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
95 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
96 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
97 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
98 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
99 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
100 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
101 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
105 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
107 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
108 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
109 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
110 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
111 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
112 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
113 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
114 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
115 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
116 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
117 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
118 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
121 * When HT is off these events can only run on the bottom 4 counters
122 * When HT is on, they are impacted by the HT bug and require EXCL access
124 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
125 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
126 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
127 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
132 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
134 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
135 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
136 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
137 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
138 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
139 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
140 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
141 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
142 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
143 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
144 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
146 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
149 * When HT is off these events can only run on the bottom 4 counters
150 * When HT is on, they are impacted by the HT bug and require EXCL access
152 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
153 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
154 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
155 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
160 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
162 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
163 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
164 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
165 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
169 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
174 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
176 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
177 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
178 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
182 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
184 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
185 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
186 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
190 static struct event_constraint intel_skl_event_constraints[] = {
191 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
192 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
193 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
194 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
197 * when HT is off, these can only run on the bottom 4 counters
199 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
200 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
201 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
202 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
203 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
208 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
209 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
210 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
214 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
215 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
216 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
217 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
218 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
222 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
223 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
224 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
225 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
226 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
230 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
231 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
232 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
233 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
235 * Note the low 8 bits eventsel code is not a continuous field, containing
236 * some #GPing bits. These are masked out.
238 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
242 static struct event_constraint intel_icl_event_constraints[] = {
243 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
244 INTEL_UEVENT_CONSTRAINT(0x1c0, 0), /* INST_RETIRED.PREC_DIST */
245 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
246 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
247 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
248 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
249 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
250 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */
251 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf),
252 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
253 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
254 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
255 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
256 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
257 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
258 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
259 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
263 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
264 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff9fffull, RSP_0),
265 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff9fffull, RSP_1),
266 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
267 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
271 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
272 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
273 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
275 static struct attribute *nhm_mem_events_attrs[] = {
276 EVENT_PTR(mem_ld_nhm),
281 * topdown events for Intel Core CPUs.
283 * The events are all in slots, which is a free slot in a 4 wide
284 * pipeline. Some events are already reported in slots, for cycle
285 * events we multiply by the pipeline width (4).
287 * With Hyper Threading on, topdown metrics are either summed or averaged
288 * between the threads of a core: (count_t0 + count_t1).
290 * For the average case the metric is always scaled to pipeline width,
291 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
294 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
295 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
296 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
297 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
298 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
299 "event=0xe,umask=0x1"); /* uops_issued.any */
300 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
301 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
302 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
303 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
304 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
305 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
306 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
307 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
310 static struct attribute *snb_events_attrs[] = {
311 EVENT_PTR(td_slots_issued),
312 EVENT_PTR(td_slots_retired),
313 EVENT_PTR(td_fetch_bubbles),
314 EVENT_PTR(td_total_slots),
315 EVENT_PTR(td_total_slots_scale),
316 EVENT_PTR(td_recovery_bubbles),
317 EVENT_PTR(td_recovery_bubbles_scale),
321 static struct attribute *snb_mem_events_attrs[] = {
322 EVENT_PTR(mem_ld_snb),
323 EVENT_PTR(mem_st_snb),
327 static struct event_constraint intel_hsw_event_constraints[] = {
328 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
329 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
330 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
331 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
332 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
333 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
334 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
335 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
336 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
337 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
338 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
339 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
342 * When HT is off these events can only run on the bottom 4 counters
343 * When HT is on, they are impacted by the HT bug and require EXCL access
345 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
346 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
347 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
348 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
353 static struct event_constraint intel_bdw_event_constraints[] = {
354 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
355 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
356 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
357 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
358 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
360 * when HT is off, these can only run on the bottom 4 counters
362 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
363 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
364 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
365 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
369 static u64 intel_pmu_event_map(int hw_event)
371 return intel_perfmon_event_map[hw_event];
375 * Notes on the events:
376 * - data reads do not include code reads (comparable to earlier tables)
377 * - data counts include speculative execution (except L1 write, dtlb, bpu)
378 * - remote node access includes remote memory, remote cache, remote mmio.
379 * - prefetches are not included in the counts.
380 * - icache miss does not include decoded icache
383 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
384 #define SKL_DEMAND_RFO BIT_ULL(1)
385 #define SKL_ANY_RESPONSE BIT_ULL(16)
386 #define SKL_SUPPLIER_NONE BIT_ULL(17)
387 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
388 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
389 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
390 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
391 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
392 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
393 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
394 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
395 #define SKL_SPL_HIT BIT_ULL(30)
396 #define SKL_SNOOP_NONE BIT_ULL(31)
397 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
398 #define SKL_SNOOP_MISS BIT_ULL(33)
399 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
400 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
401 #define SKL_SNOOP_HITM BIT_ULL(36)
402 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
403 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
404 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
405 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
406 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
407 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
408 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
409 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
410 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
411 SKL_SNOOP_HITM|SKL_SPL_HIT)
412 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
413 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
414 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
415 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
416 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
418 static __initconst const u64 skl_hw_cache_event_ids
419 [PERF_COUNT_HW_CACHE_MAX]
420 [PERF_COUNT_HW_CACHE_OP_MAX]
421 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
425 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
426 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
429 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
430 [ C(RESULT_MISS) ] = 0x0,
432 [ C(OP_PREFETCH) ] = {
433 [ C(RESULT_ACCESS) ] = 0x0,
434 [ C(RESULT_MISS) ] = 0x0,
439 [ C(RESULT_ACCESS) ] = 0x0,
440 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
443 [ C(RESULT_ACCESS) ] = -1,
444 [ C(RESULT_MISS) ] = -1,
446 [ C(OP_PREFETCH) ] = {
447 [ C(RESULT_ACCESS) ] = 0x0,
448 [ C(RESULT_MISS) ] = 0x0,
453 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
454 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
457 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
458 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
460 [ C(OP_PREFETCH) ] = {
461 [ C(RESULT_ACCESS) ] = 0x0,
462 [ C(RESULT_MISS) ] = 0x0,
467 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
468 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
471 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
472 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
474 [ C(OP_PREFETCH) ] = {
475 [ C(RESULT_ACCESS) ] = 0x0,
476 [ C(RESULT_MISS) ] = 0x0,
481 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
482 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
485 [ C(RESULT_ACCESS) ] = -1,
486 [ C(RESULT_MISS) ] = -1,
488 [ C(OP_PREFETCH) ] = {
489 [ C(RESULT_ACCESS) ] = -1,
490 [ C(RESULT_MISS) ] = -1,
495 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
496 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
499 [ C(RESULT_ACCESS) ] = -1,
500 [ C(RESULT_MISS) ] = -1,
502 [ C(OP_PREFETCH) ] = {
503 [ C(RESULT_ACCESS) ] = -1,
504 [ C(RESULT_MISS) ] = -1,
509 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
510 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
513 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
514 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
516 [ C(OP_PREFETCH) ] = {
517 [ C(RESULT_ACCESS) ] = 0x0,
518 [ C(RESULT_MISS) ] = 0x0,
523 static __initconst const u64 skl_hw_cache_extra_regs
524 [PERF_COUNT_HW_CACHE_MAX]
525 [PERF_COUNT_HW_CACHE_OP_MAX]
526 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
530 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
531 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
532 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
533 SKL_L3_MISS|SKL_ANY_SNOOP|
537 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
538 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
539 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
540 SKL_L3_MISS|SKL_ANY_SNOOP|
543 [ C(OP_PREFETCH) ] = {
544 [ C(RESULT_ACCESS) ] = 0x0,
545 [ C(RESULT_MISS) ] = 0x0,
550 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
551 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
552 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
553 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
556 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
557 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
558 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
559 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
561 [ C(OP_PREFETCH) ] = {
562 [ C(RESULT_ACCESS) ] = 0x0,
563 [ C(RESULT_MISS) ] = 0x0,
568 #define SNB_DMND_DATA_RD (1ULL << 0)
569 #define SNB_DMND_RFO (1ULL << 1)
570 #define SNB_DMND_IFETCH (1ULL << 2)
571 #define SNB_DMND_WB (1ULL << 3)
572 #define SNB_PF_DATA_RD (1ULL << 4)
573 #define SNB_PF_RFO (1ULL << 5)
574 #define SNB_PF_IFETCH (1ULL << 6)
575 #define SNB_LLC_DATA_RD (1ULL << 7)
576 #define SNB_LLC_RFO (1ULL << 8)
577 #define SNB_LLC_IFETCH (1ULL << 9)
578 #define SNB_BUS_LOCKS (1ULL << 10)
579 #define SNB_STRM_ST (1ULL << 11)
580 #define SNB_OTHER (1ULL << 15)
581 #define SNB_RESP_ANY (1ULL << 16)
582 #define SNB_NO_SUPP (1ULL << 17)
583 #define SNB_LLC_HITM (1ULL << 18)
584 #define SNB_LLC_HITE (1ULL << 19)
585 #define SNB_LLC_HITS (1ULL << 20)
586 #define SNB_LLC_HITF (1ULL << 21)
587 #define SNB_LOCAL (1ULL << 22)
588 #define SNB_REMOTE (0xffULL << 23)
589 #define SNB_SNP_NONE (1ULL << 31)
590 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
591 #define SNB_SNP_MISS (1ULL << 33)
592 #define SNB_NO_FWD (1ULL << 34)
593 #define SNB_SNP_FWD (1ULL << 35)
594 #define SNB_HITM (1ULL << 36)
595 #define SNB_NON_DRAM (1ULL << 37)
597 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
598 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
599 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
601 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
602 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
605 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
606 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
608 #define SNB_L3_ACCESS SNB_RESP_ANY
609 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
611 static __initconst const u64 snb_hw_cache_extra_regs
612 [PERF_COUNT_HW_CACHE_MAX]
613 [PERF_COUNT_HW_CACHE_OP_MAX]
614 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
618 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
619 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
622 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
623 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
625 [ C(OP_PREFETCH) ] = {
626 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
627 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
632 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
633 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
636 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
637 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
639 [ C(OP_PREFETCH) ] = {
640 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
641 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
646 static __initconst const u64 snb_hw_cache_event_ids
647 [PERF_COUNT_HW_CACHE_MAX]
648 [PERF_COUNT_HW_CACHE_OP_MAX]
649 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
653 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
654 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
657 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
658 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
660 [ C(OP_PREFETCH) ] = {
661 [ C(RESULT_ACCESS) ] = 0x0,
662 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
667 [ C(RESULT_ACCESS) ] = 0x0,
668 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
671 [ C(RESULT_ACCESS) ] = -1,
672 [ C(RESULT_MISS) ] = -1,
674 [ C(OP_PREFETCH) ] = {
675 [ C(RESULT_ACCESS) ] = 0x0,
676 [ C(RESULT_MISS) ] = 0x0,
681 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
682 [ C(RESULT_ACCESS) ] = 0x01b7,
683 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
684 [ C(RESULT_MISS) ] = 0x01b7,
687 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
688 [ C(RESULT_ACCESS) ] = 0x01b7,
689 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
690 [ C(RESULT_MISS) ] = 0x01b7,
692 [ C(OP_PREFETCH) ] = {
693 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
694 [ C(RESULT_ACCESS) ] = 0x01b7,
695 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
696 [ C(RESULT_MISS) ] = 0x01b7,
701 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
702 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
705 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
706 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
708 [ C(OP_PREFETCH) ] = {
709 [ C(RESULT_ACCESS) ] = 0x0,
710 [ C(RESULT_MISS) ] = 0x0,
715 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
716 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
719 [ C(RESULT_ACCESS) ] = -1,
720 [ C(RESULT_MISS) ] = -1,
722 [ C(OP_PREFETCH) ] = {
723 [ C(RESULT_ACCESS) ] = -1,
724 [ C(RESULT_MISS) ] = -1,
729 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
730 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
733 [ C(RESULT_ACCESS) ] = -1,
734 [ C(RESULT_MISS) ] = -1,
736 [ C(OP_PREFETCH) ] = {
737 [ C(RESULT_ACCESS) ] = -1,
738 [ C(RESULT_MISS) ] = -1,
743 [ C(RESULT_ACCESS) ] = 0x01b7,
744 [ C(RESULT_MISS) ] = 0x01b7,
747 [ C(RESULT_ACCESS) ] = 0x01b7,
748 [ C(RESULT_MISS) ] = 0x01b7,
750 [ C(OP_PREFETCH) ] = {
751 [ C(RESULT_ACCESS) ] = 0x01b7,
752 [ C(RESULT_MISS) ] = 0x01b7,
759 * Notes on the events:
760 * - data reads do not include code reads (comparable to earlier tables)
761 * - data counts include speculative execution (except L1 write, dtlb, bpu)
762 * - remote node access includes remote memory, remote cache, remote mmio.
763 * - prefetches are not included in the counts because they are not
767 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
768 #define HSW_DEMAND_RFO BIT_ULL(1)
769 #define HSW_ANY_RESPONSE BIT_ULL(16)
770 #define HSW_SUPPLIER_NONE BIT_ULL(17)
771 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
772 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
773 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
774 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
775 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
776 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
777 HSW_L3_MISS_REMOTE_HOP2P)
778 #define HSW_SNOOP_NONE BIT_ULL(31)
779 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
780 #define HSW_SNOOP_MISS BIT_ULL(33)
781 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
782 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
783 #define HSW_SNOOP_HITM BIT_ULL(36)
784 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
785 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
786 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
787 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
788 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
789 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
790 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
791 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
792 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
793 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
794 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
796 #define BDW_L3_MISS_LOCAL BIT(26)
797 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
798 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
799 HSW_L3_MISS_REMOTE_HOP2P)
802 static __initconst const u64 hsw_hw_cache_event_ids
803 [PERF_COUNT_HW_CACHE_MAX]
804 [PERF_COUNT_HW_CACHE_OP_MAX]
805 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
809 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
810 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
813 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
814 [ C(RESULT_MISS) ] = 0x0,
816 [ C(OP_PREFETCH) ] = {
817 [ C(RESULT_ACCESS) ] = 0x0,
818 [ C(RESULT_MISS) ] = 0x0,
823 [ C(RESULT_ACCESS) ] = 0x0,
824 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
827 [ C(RESULT_ACCESS) ] = -1,
828 [ C(RESULT_MISS) ] = -1,
830 [ C(OP_PREFETCH) ] = {
831 [ C(RESULT_ACCESS) ] = 0x0,
832 [ C(RESULT_MISS) ] = 0x0,
837 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
838 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
841 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
842 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
844 [ C(OP_PREFETCH) ] = {
845 [ C(RESULT_ACCESS) ] = 0x0,
846 [ C(RESULT_MISS) ] = 0x0,
851 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
852 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
855 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
856 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
858 [ C(OP_PREFETCH) ] = {
859 [ C(RESULT_ACCESS) ] = 0x0,
860 [ C(RESULT_MISS) ] = 0x0,
865 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
866 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
869 [ C(RESULT_ACCESS) ] = -1,
870 [ C(RESULT_MISS) ] = -1,
872 [ C(OP_PREFETCH) ] = {
873 [ C(RESULT_ACCESS) ] = -1,
874 [ C(RESULT_MISS) ] = -1,
879 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
880 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
883 [ C(RESULT_ACCESS) ] = -1,
884 [ C(RESULT_MISS) ] = -1,
886 [ C(OP_PREFETCH) ] = {
887 [ C(RESULT_ACCESS) ] = -1,
888 [ C(RESULT_MISS) ] = -1,
893 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
894 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
897 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
898 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
900 [ C(OP_PREFETCH) ] = {
901 [ C(RESULT_ACCESS) ] = 0x0,
902 [ C(RESULT_MISS) ] = 0x0,
907 static __initconst const u64 hsw_hw_cache_extra_regs
908 [PERF_COUNT_HW_CACHE_MAX]
909 [PERF_COUNT_HW_CACHE_OP_MAX]
910 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
914 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
916 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
917 HSW_L3_MISS|HSW_ANY_SNOOP,
920 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
922 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
923 HSW_L3_MISS|HSW_ANY_SNOOP,
925 [ C(OP_PREFETCH) ] = {
926 [ C(RESULT_ACCESS) ] = 0x0,
927 [ C(RESULT_MISS) ] = 0x0,
932 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
933 HSW_L3_MISS_LOCAL_DRAM|
935 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
940 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
941 HSW_L3_MISS_LOCAL_DRAM|
943 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
947 [ C(OP_PREFETCH) ] = {
948 [ C(RESULT_ACCESS) ] = 0x0,
949 [ C(RESULT_MISS) ] = 0x0,
954 static __initconst const u64 westmere_hw_cache_event_ids
955 [PERF_COUNT_HW_CACHE_MAX]
956 [PERF_COUNT_HW_CACHE_OP_MAX]
957 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
961 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
962 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
965 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
966 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
968 [ C(OP_PREFETCH) ] = {
969 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
970 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
975 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
976 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
979 [ C(RESULT_ACCESS) ] = -1,
980 [ C(RESULT_MISS) ] = -1,
982 [ C(OP_PREFETCH) ] = {
983 [ C(RESULT_ACCESS) ] = 0x0,
984 [ C(RESULT_MISS) ] = 0x0,
989 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
990 [ C(RESULT_ACCESS) ] = 0x01b7,
991 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
992 [ C(RESULT_MISS) ] = 0x01b7,
995 * Use RFO, not WRITEBACK, because a write miss would typically occur
999 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1000 [ C(RESULT_ACCESS) ] = 0x01b7,
1001 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1002 [ C(RESULT_MISS) ] = 0x01b7,
1004 [ C(OP_PREFETCH) ] = {
1005 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1006 [ C(RESULT_ACCESS) ] = 0x01b7,
1007 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1008 [ C(RESULT_MISS) ] = 0x01b7,
1013 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1014 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1017 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1018 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1020 [ C(OP_PREFETCH) ] = {
1021 [ C(RESULT_ACCESS) ] = 0x0,
1022 [ C(RESULT_MISS) ] = 0x0,
1027 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1028 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1031 [ C(RESULT_ACCESS) ] = -1,
1032 [ C(RESULT_MISS) ] = -1,
1034 [ C(OP_PREFETCH) ] = {
1035 [ C(RESULT_ACCESS) ] = -1,
1036 [ C(RESULT_MISS) ] = -1,
1041 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1042 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1045 [ C(RESULT_ACCESS) ] = -1,
1046 [ C(RESULT_MISS) ] = -1,
1048 [ C(OP_PREFETCH) ] = {
1049 [ C(RESULT_ACCESS) ] = -1,
1050 [ C(RESULT_MISS) ] = -1,
1055 [ C(RESULT_ACCESS) ] = 0x01b7,
1056 [ C(RESULT_MISS) ] = 0x01b7,
1059 [ C(RESULT_ACCESS) ] = 0x01b7,
1060 [ C(RESULT_MISS) ] = 0x01b7,
1062 [ C(OP_PREFETCH) ] = {
1063 [ C(RESULT_ACCESS) ] = 0x01b7,
1064 [ C(RESULT_MISS) ] = 0x01b7,
1070 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1071 * See IA32 SDM Vol 3B 30.6.1.3
1074 #define NHM_DMND_DATA_RD (1 << 0)
1075 #define NHM_DMND_RFO (1 << 1)
1076 #define NHM_DMND_IFETCH (1 << 2)
1077 #define NHM_DMND_WB (1 << 3)
1078 #define NHM_PF_DATA_RD (1 << 4)
1079 #define NHM_PF_DATA_RFO (1 << 5)
1080 #define NHM_PF_IFETCH (1 << 6)
1081 #define NHM_OFFCORE_OTHER (1 << 7)
1082 #define NHM_UNCORE_HIT (1 << 8)
1083 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1084 #define NHM_OTHER_CORE_HITM (1 << 10)
1086 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1087 #define NHM_REMOTE_DRAM (1 << 13)
1088 #define NHM_LOCAL_DRAM (1 << 14)
1089 #define NHM_NON_DRAM (1 << 15)
1091 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1092 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1094 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1095 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1096 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1098 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1099 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1100 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1102 static __initconst const u64 nehalem_hw_cache_extra_regs
1103 [PERF_COUNT_HW_CACHE_MAX]
1104 [PERF_COUNT_HW_CACHE_OP_MAX]
1105 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1109 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1110 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1113 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1114 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1116 [ C(OP_PREFETCH) ] = {
1117 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1118 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1123 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1124 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1127 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1128 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1130 [ C(OP_PREFETCH) ] = {
1131 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1132 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1137 static __initconst const u64 nehalem_hw_cache_event_ids
1138 [PERF_COUNT_HW_CACHE_MAX]
1139 [PERF_COUNT_HW_CACHE_OP_MAX]
1140 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1144 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1145 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1148 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1149 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1151 [ C(OP_PREFETCH) ] = {
1152 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1153 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1158 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1159 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1162 [ C(RESULT_ACCESS) ] = -1,
1163 [ C(RESULT_MISS) ] = -1,
1165 [ C(OP_PREFETCH) ] = {
1166 [ C(RESULT_ACCESS) ] = 0x0,
1167 [ C(RESULT_MISS) ] = 0x0,
1172 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1173 [ C(RESULT_ACCESS) ] = 0x01b7,
1174 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1175 [ C(RESULT_MISS) ] = 0x01b7,
1178 * Use RFO, not WRITEBACK, because a write miss would typically occur
1182 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1183 [ C(RESULT_ACCESS) ] = 0x01b7,
1184 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1185 [ C(RESULT_MISS) ] = 0x01b7,
1187 [ C(OP_PREFETCH) ] = {
1188 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1189 [ C(RESULT_ACCESS) ] = 0x01b7,
1190 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1191 [ C(RESULT_MISS) ] = 0x01b7,
1196 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1197 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1200 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1201 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1203 [ C(OP_PREFETCH) ] = {
1204 [ C(RESULT_ACCESS) ] = 0x0,
1205 [ C(RESULT_MISS) ] = 0x0,
1210 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1211 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1214 [ C(RESULT_ACCESS) ] = -1,
1215 [ C(RESULT_MISS) ] = -1,
1217 [ C(OP_PREFETCH) ] = {
1218 [ C(RESULT_ACCESS) ] = -1,
1219 [ C(RESULT_MISS) ] = -1,
1224 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1225 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1228 [ C(RESULT_ACCESS) ] = -1,
1229 [ C(RESULT_MISS) ] = -1,
1231 [ C(OP_PREFETCH) ] = {
1232 [ C(RESULT_ACCESS) ] = -1,
1233 [ C(RESULT_MISS) ] = -1,
1238 [ C(RESULT_ACCESS) ] = 0x01b7,
1239 [ C(RESULT_MISS) ] = 0x01b7,
1242 [ C(RESULT_ACCESS) ] = 0x01b7,
1243 [ C(RESULT_MISS) ] = 0x01b7,
1245 [ C(OP_PREFETCH) ] = {
1246 [ C(RESULT_ACCESS) ] = 0x01b7,
1247 [ C(RESULT_MISS) ] = 0x01b7,
1252 static __initconst const u64 core2_hw_cache_event_ids
1253 [PERF_COUNT_HW_CACHE_MAX]
1254 [PERF_COUNT_HW_CACHE_OP_MAX]
1255 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1259 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1260 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1263 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1264 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1266 [ C(OP_PREFETCH) ] = {
1267 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1268 [ C(RESULT_MISS) ] = 0,
1273 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1274 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1277 [ C(RESULT_ACCESS) ] = -1,
1278 [ C(RESULT_MISS) ] = -1,
1280 [ C(OP_PREFETCH) ] = {
1281 [ C(RESULT_ACCESS) ] = 0,
1282 [ C(RESULT_MISS) ] = 0,
1287 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1288 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1291 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1292 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1294 [ C(OP_PREFETCH) ] = {
1295 [ C(RESULT_ACCESS) ] = 0,
1296 [ C(RESULT_MISS) ] = 0,
1301 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1302 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1305 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1306 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1308 [ C(OP_PREFETCH) ] = {
1309 [ C(RESULT_ACCESS) ] = 0,
1310 [ C(RESULT_MISS) ] = 0,
1315 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1316 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1319 [ C(RESULT_ACCESS) ] = -1,
1320 [ C(RESULT_MISS) ] = -1,
1322 [ C(OP_PREFETCH) ] = {
1323 [ C(RESULT_ACCESS) ] = -1,
1324 [ C(RESULT_MISS) ] = -1,
1329 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1330 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1333 [ C(RESULT_ACCESS) ] = -1,
1334 [ C(RESULT_MISS) ] = -1,
1336 [ C(OP_PREFETCH) ] = {
1337 [ C(RESULT_ACCESS) ] = -1,
1338 [ C(RESULT_MISS) ] = -1,
1343 static __initconst const u64 atom_hw_cache_event_ids
1344 [PERF_COUNT_HW_CACHE_MAX]
1345 [PERF_COUNT_HW_CACHE_OP_MAX]
1346 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1350 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1351 [ C(RESULT_MISS) ] = 0,
1354 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1355 [ C(RESULT_MISS) ] = 0,
1357 [ C(OP_PREFETCH) ] = {
1358 [ C(RESULT_ACCESS) ] = 0x0,
1359 [ C(RESULT_MISS) ] = 0,
1364 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1365 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1368 [ C(RESULT_ACCESS) ] = -1,
1369 [ C(RESULT_MISS) ] = -1,
1371 [ C(OP_PREFETCH) ] = {
1372 [ C(RESULT_ACCESS) ] = 0,
1373 [ C(RESULT_MISS) ] = 0,
1378 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1379 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1382 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1383 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1385 [ C(OP_PREFETCH) ] = {
1386 [ C(RESULT_ACCESS) ] = 0,
1387 [ C(RESULT_MISS) ] = 0,
1392 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1393 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1396 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1397 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1399 [ C(OP_PREFETCH) ] = {
1400 [ C(RESULT_ACCESS) ] = 0,
1401 [ C(RESULT_MISS) ] = 0,
1406 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1407 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1410 [ C(RESULT_ACCESS) ] = -1,
1411 [ C(RESULT_MISS) ] = -1,
1413 [ C(OP_PREFETCH) ] = {
1414 [ C(RESULT_ACCESS) ] = -1,
1415 [ C(RESULT_MISS) ] = -1,
1420 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1421 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1424 [ C(RESULT_ACCESS) ] = -1,
1425 [ C(RESULT_MISS) ] = -1,
1427 [ C(OP_PREFETCH) ] = {
1428 [ C(RESULT_ACCESS) ] = -1,
1429 [ C(RESULT_MISS) ] = -1,
1434 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1435 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1436 /* no_alloc_cycles.not_delivered */
1437 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1438 "event=0xca,umask=0x50");
1439 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1440 /* uops_retired.all */
1441 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1442 "event=0xc2,umask=0x10");
1443 /* uops_retired.all */
1444 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1445 "event=0xc2,umask=0x10");
1447 static struct attribute *slm_events_attrs[] = {
1448 EVENT_PTR(td_total_slots_slm),
1449 EVENT_PTR(td_total_slots_scale_slm),
1450 EVENT_PTR(td_fetch_bubbles_slm),
1451 EVENT_PTR(td_fetch_bubbles_scale_slm),
1452 EVENT_PTR(td_slots_issued_slm),
1453 EVENT_PTR(td_slots_retired_slm),
1457 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1459 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1460 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1461 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1465 #define SLM_DMND_READ SNB_DMND_DATA_RD
1466 #define SLM_DMND_WRITE SNB_DMND_RFO
1467 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1469 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1470 #define SLM_LLC_ACCESS SNB_RESP_ANY
1471 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1473 static __initconst const u64 slm_hw_cache_extra_regs
1474 [PERF_COUNT_HW_CACHE_MAX]
1475 [PERF_COUNT_HW_CACHE_OP_MAX]
1476 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1480 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1481 [ C(RESULT_MISS) ] = 0,
1484 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1485 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1487 [ C(OP_PREFETCH) ] = {
1488 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1489 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1494 static __initconst const u64 slm_hw_cache_event_ids
1495 [PERF_COUNT_HW_CACHE_MAX]
1496 [PERF_COUNT_HW_CACHE_OP_MAX]
1497 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1501 [ C(RESULT_ACCESS) ] = 0,
1502 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1505 [ C(RESULT_ACCESS) ] = 0,
1506 [ C(RESULT_MISS) ] = 0,
1508 [ C(OP_PREFETCH) ] = {
1509 [ C(RESULT_ACCESS) ] = 0,
1510 [ C(RESULT_MISS) ] = 0,
1515 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1516 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1519 [ C(RESULT_ACCESS) ] = -1,
1520 [ C(RESULT_MISS) ] = -1,
1522 [ C(OP_PREFETCH) ] = {
1523 [ C(RESULT_ACCESS) ] = 0,
1524 [ C(RESULT_MISS) ] = 0,
1529 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1530 [ C(RESULT_ACCESS) ] = 0x01b7,
1531 [ C(RESULT_MISS) ] = 0,
1534 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1535 [ C(RESULT_ACCESS) ] = 0x01b7,
1536 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1537 [ C(RESULT_MISS) ] = 0x01b7,
1539 [ C(OP_PREFETCH) ] = {
1540 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1541 [ C(RESULT_ACCESS) ] = 0x01b7,
1542 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1543 [ C(RESULT_MISS) ] = 0x01b7,
1548 [ C(RESULT_ACCESS) ] = 0,
1549 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1552 [ C(RESULT_ACCESS) ] = 0,
1553 [ C(RESULT_MISS) ] = 0,
1555 [ C(OP_PREFETCH) ] = {
1556 [ C(RESULT_ACCESS) ] = 0,
1557 [ C(RESULT_MISS) ] = 0,
1562 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1563 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1566 [ C(RESULT_ACCESS) ] = -1,
1567 [ C(RESULT_MISS) ] = -1,
1569 [ C(OP_PREFETCH) ] = {
1570 [ C(RESULT_ACCESS) ] = -1,
1571 [ C(RESULT_MISS) ] = -1,
1576 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1577 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1580 [ C(RESULT_ACCESS) ] = -1,
1581 [ C(RESULT_MISS) ] = -1,
1583 [ C(OP_PREFETCH) ] = {
1584 [ C(RESULT_ACCESS) ] = -1,
1585 [ C(RESULT_MISS) ] = -1,
1590 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1591 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1592 /* UOPS_NOT_DELIVERED.ANY */
1593 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1594 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1595 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1596 /* UOPS_RETIRED.ANY */
1597 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1598 /* UOPS_ISSUED.ANY */
1599 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1601 static struct attribute *glm_events_attrs[] = {
1602 EVENT_PTR(td_total_slots_glm),
1603 EVENT_PTR(td_total_slots_scale_glm),
1604 EVENT_PTR(td_fetch_bubbles_glm),
1605 EVENT_PTR(td_recovery_bubbles_glm),
1606 EVENT_PTR(td_slots_issued_glm),
1607 EVENT_PTR(td_slots_retired_glm),
1611 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1612 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1613 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1614 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1618 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
1619 #define GLM_DEMAND_RFO BIT_ULL(1)
1620 #define GLM_ANY_RESPONSE BIT_ULL(16)
1621 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1622 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1623 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1624 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1625 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1626 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1627 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1629 static __initconst const u64 glm_hw_cache_event_ids
1630 [PERF_COUNT_HW_CACHE_MAX]
1631 [PERF_COUNT_HW_CACHE_OP_MAX]
1632 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1635 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1636 [C(RESULT_MISS)] = 0x0,
1639 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1640 [C(RESULT_MISS)] = 0x0,
1642 [C(OP_PREFETCH)] = {
1643 [C(RESULT_ACCESS)] = 0x0,
1644 [C(RESULT_MISS)] = 0x0,
1649 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1650 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1653 [C(RESULT_ACCESS)] = -1,
1654 [C(RESULT_MISS)] = -1,
1656 [C(OP_PREFETCH)] = {
1657 [C(RESULT_ACCESS)] = 0x0,
1658 [C(RESULT_MISS)] = 0x0,
1663 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1664 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1667 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1668 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1670 [C(OP_PREFETCH)] = {
1671 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1672 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1677 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1678 [C(RESULT_MISS)] = 0x0,
1681 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1682 [C(RESULT_MISS)] = 0x0,
1684 [C(OP_PREFETCH)] = {
1685 [C(RESULT_ACCESS)] = 0x0,
1686 [C(RESULT_MISS)] = 0x0,
1691 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1692 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1695 [C(RESULT_ACCESS)] = -1,
1696 [C(RESULT_MISS)] = -1,
1698 [C(OP_PREFETCH)] = {
1699 [C(RESULT_ACCESS)] = -1,
1700 [C(RESULT_MISS)] = -1,
1705 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1706 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1709 [C(RESULT_ACCESS)] = -1,
1710 [C(RESULT_MISS)] = -1,
1712 [C(OP_PREFETCH)] = {
1713 [C(RESULT_ACCESS)] = -1,
1714 [C(RESULT_MISS)] = -1,
1719 static __initconst const u64 glm_hw_cache_extra_regs
1720 [PERF_COUNT_HW_CACHE_MAX]
1721 [PERF_COUNT_HW_CACHE_OP_MAX]
1722 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1725 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1727 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1731 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1733 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1736 [C(OP_PREFETCH)] = {
1737 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1739 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1745 static __initconst const u64 glp_hw_cache_event_ids
1746 [PERF_COUNT_HW_CACHE_MAX]
1747 [PERF_COUNT_HW_CACHE_OP_MAX]
1748 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1751 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1752 [C(RESULT_MISS)] = 0x0,
1755 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1756 [C(RESULT_MISS)] = 0x0,
1758 [C(OP_PREFETCH)] = {
1759 [C(RESULT_ACCESS)] = 0x0,
1760 [C(RESULT_MISS)] = 0x0,
1765 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1766 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1769 [C(RESULT_ACCESS)] = -1,
1770 [C(RESULT_MISS)] = -1,
1772 [C(OP_PREFETCH)] = {
1773 [C(RESULT_ACCESS)] = 0x0,
1774 [C(RESULT_MISS)] = 0x0,
1779 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1780 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1783 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1784 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1786 [C(OP_PREFETCH)] = {
1787 [C(RESULT_ACCESS)] = 0x0,
1788 [C(RESULT_MISS)] = 0x0,
1793 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1794 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1797 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1798 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
1800 [C(OP_PREFETCH)] = {
1801 [C(RESULT_ACCESS)] = 0x0,
1802 [C(RESULT_MISS)] = 0x0,
1807 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1808 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1811 [C(RESULT_ACCESS)] = -1,
1812 [C(RESULT_MISS)] = -1,
1814 [C(OP_PREFETCH)] = {
1815 [C(RESULT_ACCESS)] = -1,
1816 [C(RESULT_MISS)] = -1,
1821 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1822 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1825 [C(RESULT_ACCESS)] = -1,
1826 [C(RESULT_MISS)] = -1,
1828 [C(OP_PREFETCH)] = {
1829 [C(RESULT_ACCESS)] = -1,
1830 [C(RESULT_MISS)] = -1,
1835 static __initconst const u64 glp_hw_cache_extra_regs
1836 [PERF_COUNT_HW_CACHE_MAX]
1837 [PERF_COUNT_HW_CACHE_OP_MAX]
1838 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1841 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1843 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1847 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1849 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1852 [C(OP_PREFETCH)] = {
1853 [C(RESULT_ACCESS)] = 0x0,
1854 [C(RESULT_MISS)] = 0x0,
1859 #define TNT_LOCAL_DRAM BIT_ULL(26)
1860 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD
1861 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO
1862 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE
1863 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
1864 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
1865 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
1867 static __initconst const u64 tnt_hw_cache_extra_regs
1868 [PERF_COUNT_HW_CACHE_MAX]
1869 [PERF_COUNT_HW_CACHE_OP_MAX]
1870 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1873 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
1875 [C(RESULT_MISS)] = TNT_DEMAND_READ|
1879 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
1881 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
1884 [C(OP_PREFETCH)] = {
1885 [C(RESULT_ACCESS)] = 0x0,
1886 [C(RESULT_MISS)] = 0x0,
1891 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
1892 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1893 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffffff9fffull, RSP_0),
1894 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xffffff9fffull, RSP_1),
1898 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
1899 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
1900 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
1901 #define KNL_MCDRAM_FAR BIT_ULL(22)
1902 #define KNL_DDR_LOCAL BIT_ULL(23)
1903 #define KNL_DDR_FAR BIT_ULL(24)
1904 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
1905 KNL_DDR_LOCAL | KNL_DDR_FAR)
1906 #define KNL_L2_READ SLM_DMND_READ
1907 #define KNL_L2_WRITE SLM_DMND_WRITE
1908 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
1909 #define KNL_L2_ACCESS SLM_LLC_ACCESS
1910 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
1911 KNL_DRAM_ANY | SNB_SNP_ANY | \
1914 static __initconst const u64 knl_hw_cache_extra_regs
1915 [PERF_COUNT_HW_CACHE_MAX]
1916 [PERF_COUNT_HW_CACHE_OP_MAX]
1917 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1920 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1921 [C(RESULT_MISS)] = 0,
1924 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1925 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
1927 [C(OP_PREFETCH)] = {
1928 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1929 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
1935 * Used from PMIs where the LBRs are already disabled.
1937 * This function could be called consecutively. It is required to remain in
1938 * disabled state if called consecutively.
1940 * During consecutive calls, the same disable value will be written to related
1941 * registers, so the PMU state remains unchanged.
1943 * intel_bts events don't coexist with intel PMU's BTS events because of
1944 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
1945 * disabled around intel PMU's event batching etc, only inside the PMI handler.
1947 static void __intel_pmu_disable_all(void)
1949 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1951 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1953 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1954 intel_pmu_disable_bts();
1956 intel_pmu_pebs_disable_all();
1959 static void intel_pmu_disable_all(void)
1961 __intel_pmu_disable_all();
1962 intel_pmu_lbr_disable_all();
1965 static void __intel_pmu_enable_all(int added, bool pmi)
1967 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1969 intel_pmu_pebs_enable_all();
1970 intel_pmu_lbr_enable_all(pmi);
1971 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1972 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1974 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1975 struct perf_event *event =
1976 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1978 if (WARN_ON_ONCE(!event))
1981 intel_pmu_enable_bts(event->hw.config);
1985 static void intel_pmu_enable_all(int added)
1987 __intel_pmu_enable_all(added, false);
1992 * Intel Errata AAK100 (model 26)
1993 * Intel Errata AAP53 (model 30)
1994 * Intel Errata BD53 (model 44)
1996 * The official story:
1997 * These chips need to be 'reset' when adding counters by programming the
1998 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1999 * in sequence on the same PMC or on different PMCs.
2001 * In practise it appears some of these events do in fact count, and
2002 * we need to program all 4 events.
2004 static void intel_pmu_nhm_workaround(void)
2006 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2007 static const unsigned long nhm_magic[4] = {
2013 struct perf_event *event;
2017 * The Errata requires below steps:
2018 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2019 * 2) Configure 4 PERFEVTSELx with the magic events and clear
2020 * the corresponding PMCx;
2021 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2022 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2023 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2027 * The real steps we choose are a little different from above.
2028 * A) To reduce MSR operations, we don't run step 1) as they
2029 * are already cleared before this function is called;
2030 * B) Call x86_perf_event_update to save PMCx before configuring
2031 * PERFEVTSELx with magic number;
2032 * C) With step 5), we do clear only when the PERFEVTSELx is
2033 * not used currently.
2034 * D) Call x86_perf_event_set_period to restore PMCx;
2037 /* We always operate 4 pairs of PERF Counters */
2038 for (i = 0; i < 4; i++) {
2039 event = cpuc->events[i];
2041 x86_perf_event_update(event);
2044 for (i = 0; i < 4; i++) {
2045 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2046 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2049 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2050 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2052 for (i = 0; i < 4; i++) {
2053 event = cpuc->events[i];
2056 x86_perf_event_set_period(event);
2057 __x86_pmu_enable_event(&event->hw,
2058 ARCH_PERFMON_EVENTSEL_ENABLE);
2060 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2064 static void intel_pmu_nhm_enable_all(int added)
2067 intel_pmu_nhm_workaround();
2068 intel_pmu_enable_all(added);
2071 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2073 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2075 if (cpuc->tfa_shadow != val) {
2076 cpuc->tfa_shadow = val;
2077 wrmsrl(MSR_TSX_FORCE_ABORT, val);
2081 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2084 * We're going to use PMC3, make sure TFA is set before we touch it.
2087 intel_set_tfa(cpuc, true);
2090 static void intel_tfa_pmu_enable_all(int added)
2092 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2095 * If we find PMC3 is no longer used when we enable the PMU, we can
2098 if (!test_bit(3, cpuc->active_mask))
2099 intel_set_tfa(cpuc, false);
2101 intel_pmu_enable_all(added);
2104 static void enable_counter_freeze(void)
2106 update_debugctlmsr(get_debugctlmsr() |
2107 DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI);
2110 static void disable_counter_freeze(void)
2112 update_debugctlmsr(get_debugctlmsr() &
2113 ~DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI);
2116 static inline u64 intel_pmu_get_status(void)
2120 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2125 static inline void intel_pmu_ack_status(u64 ack)
2127 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2130 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
2132 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
2135 mask = 0xfULL << (idx * 4);
2137 rdmsrl(hwc->config_base, ctrl_val);
2139 wrmsrl(hwc->config_base, ctrl_val);
2142 static inline bool event_is_checkpointed(struct perf_event *event)
2144 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2147 static void intel_pmu_disable_event(struct perf_event *event)
2149 struct hw_perf_event *hwc = &event->hw;
2150 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2152 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
2153 intel_pmu_disable_bts();
2154 intel_pmu_drain_bts_buffer();
2158 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
2159 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
2160 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
2162 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
2163 intel_pmu_disable_fixed(hwc);
2167 x86_pmu_disable_event(event);
2170 * Needs to be called after x86_pmu_disable_event,
2171 * so we don't trigger the event without PEBS bit set.
2173 if (unlikely(event->attr.precise_ip))
2174 intel_pmu_pebs_disable(event);
2177 static void intel_pmu_del_event(struct perf_event *event)
2179 if (needs_branch_stack(event))
2180 intel_pmu_lbr_del(event);
2181 if (event->attr.precise_ip)
2182 intel_pmu_pebs_del(event);
2185 static void intel_pmu_read_event(struct perf_event *event)
2187 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2188 intel_pmu_auto_reload_read(event);
2190 x86_perf_event_update(event);
2193 static void intel_pmu_enable_fixed(struct perf_event *event)
2195 struct hw_perf_event *hwc = &event->hw;
2196 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
2197 u64 ctrl_val, mask, bits = 0;
2200 * Enable IRQ generation (0x8), if not PEBS,
2201 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2204 if (!event->attr.precise_ip)
2206 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2208 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2212 * ANY bit is supported in v3 and up
2214 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2218 mask = 0xfULL << (idx * 4);
2220 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
2221 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2222 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2225 rdmsrl(hwc->config_base, ctrl_val);
2228 wrmsrl(hwc->config_base, ctrl_val);
2231 static void intel_pmu_enable_event(struct perf_event *event)
2233 struct hw_perf_event *hwc = &event->hw;
2234 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2236 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
2237 if (!__this_cpu_read(cpu_hw_events.enabled))
2240 intel_pmu_enable_bts(hwc->config);
2244 if (event->attr.exclude_host)
2245 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
2246 if (event->attr.exclude_guest)
2247 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
2249 if (unlikely(event_is_checkpointed(event)))
2250 cpuc->intel_cp_status |= (1ull << hwc->idx);
2252 if (unlikely(event->attr.precise_ip))
2253 intel_pmu_pebs_enable(event);
2255 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
2256 intel_pmu_enable_fixed(event);
2260 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2263 static void intel_pmu_add_event(struct perf_event *event)
2265 if (event->attr.precise_ip)
2266 intel_pmu_pebs_add(event);
2267 if (needs_branch_stack(event))
2268 intel_pmu_lbr_add(event);
2272 * Save and restart an expired event. Called by NMI contexts,
2273 * so it has to be careful about preempting normal event ops:
2275 int intel_pmu_save_and_restart(struct perf_event *event)
2277 x86_perf_event_update(event);
2279 * For a checkpointed counter always reset back to 0. This
2280 * avoids a situation where the counter overflows, aborts the
2281 * transaction and is then set back to shortly before the
2282 * overflow, and overflows and aborts again.
2284 if (unlikely(event_is_checkpointed(event))) {
2285 /* No race with NMIs because the counter should not be armed */
2286 wrmsrl(event->hw.event_base, 0);
2287 local64_set(&event->hw.prev_count, 0);
2289 return x86_perf_event_set_period(event);
2292 static void intel_pmu_reset(void)
2294 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2295 unsigned long flags;
2298 if (!x86_pmu.num_counters)
2301 local_irq_save(flags);
2303 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2305 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2306 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2307 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
2309 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
2310 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
2313 ds->bts_index = ds->bts_buffer_base;
2315 /* Ack all overflows and disable fixed counters */
2316 if (x86_pmu.version >= 2) {
2317 intel_pmu_ack_status(intel_pmu_get_status());
2318 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2321 /* Reset LBRs and LBR freezing */
2322 if (x86_pmu.lbr_nr) {
2323 update_debugctlmsr(get_debugctlmsr() &
2324 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2327 local_irq_restore(flags);
2330 static int handle_pmi_common(struct pt_regs *regs, u64 status)
2332 struct perf_sample_data data;
2333 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2337 inc_irq_stat(apic_perf_irqs);
2340 * Ignore a range of extra bits in status that do not indicate
2341 * overflow by themselves.
2343 status &= ~(GLOBAL_STATUS_COND_CHG |
2344 GLOBAL_STATUS_ASIF |
2345 GLOBAL_STATUS_LBRS_FROZEN);
2349 * In case multiple PEBS events are sampled at the same time,
2350 * it is possible to have GLOBAL_STATUS bit 62 set indicating
2351 * PEBS buffer overflow and also seeing at most 3 PEBS counters
2352 * having their bits set in the status register. This is a sign
2353 * that there was at least one PEBS record pending at the time
2354 * of the PMU interrupt. PEBS counters must only be processed
2355 * via the drain_pebs() calls and not via the regular sample
2356 * processing loop coming after that the function, otherwise
2357 * phony regular samples may be generated in the sampling buffer
2358 * not marked with the EXACT tag. Another possibility is to have
2359 * one PEBS event and at least one non-PEBS event whic hoverflows
2360 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
2361 * not be set, yet the overflow status bit for the PEBS counter will
2364 * To avoid this problem, we systematically ignore the PEBS-enabled
2365 * counters from the GLOBAL_STATUS mask and we always process PEBS
2366 * events via drain_pebs().
2368 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
2369 status &= ~cpuc->pebs_enabled;
2371 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
2374 * PEBS overflow sets bit 62 in the global status register
2376 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
2378 x86_pmu.drain_pebs(regs);
2379 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
2385 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
2387 intel_pt_interrupt();
2391 * Checkpointed counters can lead to 'spurious' PMIs because the
2392 * rollback caused by the PMI will have cleared the overflow status
2393 * bit. Therefore always force probe these counters.
2395 status |= cpuc->intel_cp_status;
2397 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
2398 struct perf_event *event = cpuc->events[bit];
2402 if (!test_bit(bit, cpuc->active_mask))
2405 if (!intel_pmu_save_and_restart(event))
2408 perf_sample_data_init(&data, 0, event->hw.last_period);
2410 if (has_branch_stack(event))
2411 data.br_stack = &cpuc->lbr_stack;
2413 if (perf_event_overflow(event, &data, regs))
2414 x86_pmu_stop(event, 0);
2420 static bool disable_counter_freezing = true;
2421 static int __init intel_perf_counter_freezing_setup(char *s)
2425 if (kstrtobool(s, &res))
2428 disable_counter_freezing = !res;
2431 __setup("perf_v4_pmi=", intel_perf_counter_freezing_setup);
2434 * Simplified handler for Arch Perfmon v4:
2435 * - We rely on counter freezing/unfreezing to enable/disable the PMU.
2436 * This is done automatically on PMU ack.
2437 * - Ack the PMU only after the APIC.
2440 static int intel_pmu_handle_irq_v4(struct pt_regs *regs)
2442 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2446 int pmu_enabled = cpuc->enabled;
2449 /* PMU has been disabled because of counter freezing */
2451 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2453 intel_bts_disable_local();
2454 handled = intel_pmu_drain_bts_buffer();
2455 handled += intel_bts_interrupt();
2457 status = intel_pmu_get_status();
2461 intel_pmu_lbr_read();
2462 if (++loops > 100) {
2466 WARN(1, "perfevents: irq loop stuck!\n");
2467 perf_event_print_debug();
2475 handled += handle_pmi_common(regs, status);
2477 /* Ack the PMI in the APIC */
2478 apic_write(APIC_LVTPC, APIC_DM_NMI);
2481 * The counters start counting immediately while ack the status.
2482 * Make it as close as possible to IRET. This avoids bogus
2483 * freezing on Skylake CPUs.
2486 intel_pmu_ack_status(status);
2489 * CPU may issues two PMIs very close to each other.
2490 * When the PMI handler services the first one, the
2491 * GLOBAL_STATUS is already updated to reflect both.
2492 * When it IRETs, the second PMI is immediately
2493 * handled and it sees clear status. At the meantime,
2494 * there may be a third PMI, because the freezing bit
2495 * isn't set since the ack in first PMI handlers.
2496 * Double check if there is more work to be done.
2498 status = intel_pmu_get_status();
2504 intel_bts_enable_local();
2505 cpuc->enabled = pmu_enabled;
2510 * This handler is triggered by the local APIC, so the APIC IRQ handling
2513 static int intel_pmu_handle_irq(struct pt_regs *regs)
2515 struct cpu_hw_events *cpuc;
2521 cpuc = this_cpu_ptr(&cpu_hw_events);
2524 * Save the PMU state.
2525 * It needs to be restored when leaving the handler.
2527 pmu_enabled = cpuc->enabled;
2529 * No known reason to not always do late ACK,
2530 * but just in case do it opt-in.
2532 if (!x86_pmu.late_ack)
2533 apic_write(APIC_LVTPC, APIC_DM_NMI);
2534 intel_bts_disable_local();
2536 __intel_pmu_disable_all();
2537 handled = intel_pmu_drain_bts_buffer();
2538 handled += intel_bts_interrupt();
2539 status = intel_pmu_get_status();
2545 intel_pmu_lbr_read();
2546 intel_pmu_ack_status(status);
2547 if (++loops > 100) {
2551 WARN(1, "perfevents: irq loop stuck!\n");
2552 perf_event_print_debug();
2559 handled += handle_pmi_common(regs, status);
2562 * Repeat if there is more work to be done:
2564 status = intel_pmu_get_status();
2569 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
2570 cpuc->enabled = pmu_enabled;
2572 __intel_pmu_enable_all(0, true);
2573 intel_bts_enable_local();
2576 * Only unmask the NMI after the overflow counters
2577 * have been reset. This avoids spurious NMIs on
2580 if (x86_pmu.late_ack)
2581 apic_write(APIC_LVTPC, APIC_DM_NMI);
2585 static struct event_constraint *
2586 intel_bts_constraints(struct perf_event *event)
2588 if (unlikely(intel_pmu_has_bts(event)))
2589 return &bts_constraint;
2594 static int intel_alt_er(int idx, u64 config)
2598 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
2601 if (idx == EXTRA_REG_RSP_0)
2602 alt_idx = EXTRA_REG_RSP_1;
2604 if (idx == EXTRA_REG_RSP_1)
2605 alt_idx = EXTRA_REG_RSP_0;
2607 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
2613 static void intel_fixup_er(struct perf_event *event, int idx)
2615 event->hw.extra_reg.idx = idx;
2617 if (idx == EXTRA_REG_RSP_0) {
2618 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2619 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
2620 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
2621 } else if (idx == EXTRA_REG_RSP_1) {
2622 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2623 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
2624 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
2629 * manage allocation of shared extra msr for certain events
2632 * per-cpu: to be shared between the various events on a single PMU
2633 * per-core: per-cpu + shared by HT threads
2635 static struct event_constraint *
2636 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
2637 struct perf_event *event,
2638 struct hw_perf_event_extra *reg)
2640 struct event_constraint *c = &emptyconstraint;
2641 struct er_account *era;
2642 unsigned long flags;
2646 * reg->alloc can be set due to existing state, so for fake cpuc we
2647 * need to ignore this, otherwise we might fail to allocate proper fake
2648 * state for this extra reg constraint. Also see the comment below.
2650 if (reg->alloc && !cpuc->is_fake)
2651 return NULL; /* call x86_get_event_constraint() */
2654 era = &cpuc->shared_regs->regs[idx];
2656 * we use spin_lock_irqsave() to avoid lockdep issues when
2657 * passing a fake cpuc
2659 raw_spin_lock_irqsave(&era->lock, flags);
2661 if (!atomic_read(&era->ref) || era->config == reg->config) {
2664 * If its a fake cpuc -- as per validate_{group,event}() we
2665 * shouldn't touch event state and we can avoid doing so
2666 * since both will only call get_event_constraints() once
2667 * on each event, this avoids the need for reg->alloc.
2669 * Not doing the ER fixup will only result in era->reg being
2670 * wrong, but since we won't actually try and program hardware
2671 * this isn't a problem either.
2673 if (!cpuc->is_fake) {
2674 if (idx != reg->idx)
2675 intel_fixup_er(event, idx);
2678 * x86_schedule_events() can call get_event_constraints()
2679 * multiple times on events in the case of incremental
2680 * scheduling(). reg->alloc ensures we only do the ER
2686 /* lock in msr value */
2687 era->config = reg->config;
2688 era->reg = reg->reg;
2691 atomic_inc(&era->ref);
2694 * need to call x86_get_event_constraint()
2695 * to check if associated event has constraints
2699 idx = intel_alt_er(idx, reg->config);
2700 if (idx != reg->idx) {
2701 raw_spin_unlock_irqrestore(&era->lock, flags);
2705 raw_spin_unlock_irqrestore(&era->lock, flags);
2711 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
2712 struct hw_perf_event_extra *reg)
2714 struct er_account *era;
2717 * Only put constraint if extra reg was actually allocated. Also takes
2718 * care of event which do not use an extra shared reg.
2720 * Also, if this is a fake cpuc we shouldn't touch any event state
2721 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
2722 * either since it'll be thrown out.
2724 if (!reg->alloc || cpuc->is_fake)
2727 era = &cpuc->shared_regs->regs[reg->idx];
2729 /* one fewer user */
2730 atomic_dec(&era->ref);
2732 /* allocate again next time */
2736 static struct event_constraint *
2737 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
2738 struct perf_event *event)
2740 struct event_constraint *c = NULL, *d;
2741 struct hw_perf_event_extra *xreg, *breg;
2743 xreg = &event->hw.extra_reg;
2744 if (xreg->idx != EXTRA_REG_NONE) {
2745 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
2746 if (c == &emptyconstraint)
2749 breg = &event->hw.branch_reg;
2750 if (breg->idx != EXTRA_REG_NONE) {
2751 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
2752 if (d == &emptyconstraint) {
2753 __intel_shared_reg_put_constraints(cpuc, xreg);
2760 struct event_constraint *
2761 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2762 struct perf_event *event)
2764 struct event_constraint *c;
2766 if (x86_pmu.event_constraints) {
2767 for_each_event_constraint(c, x86_pmu.event_constraints) {
2768 if (constraint_match(c, event->hw.config)) {
2769 event->hw.flags |= c->flags;
2775 return &unconstrained;
2778 static struct event_constraint *
2779 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2780 struct perf_event *event)
2782 struct event_constraint *c;
2784 c = intel_bts_constraints(event);
2788 c = intel_shared_regs_constraints(cpuc, event);
2792 c = intel_pebs_constraints(event);
2796 return x86_get_event_constraints(cpuc, idx, event);
2800 intel_start_scheduling(struct cpu_hw_events *cpuc)
2802 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2803 struct intel_excl_states *xl;
2804 int tid = cpuc->excl_thread_id;
2807 * nothing needed if in group validation mode
2809 if (cpuc->is_fake || !is_ht_workaround_enabled())
2813 * no exclusion needed
2815 if (WARN_ON_ONCE(!excl_cntrs))
2818 xl = &excl_cntrs->states[tid];
2820 xl->sched_started = true;
2822 * lock shared state until we are done scheduling
2823 * in stop_event_scheduling()
2824 * makes scheduling appear as a transaction
2826 raw_spin_lock(&excl_cntrs->lock);
2829 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2831 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2832 struct event_constraint *c = cpuc->event_constraint[idx];
2833 struct intel_excl_states *xl;
2834 int tid = cpuc->excl_thread_id;
2836 if (cpuc->is_fake || !is_ht_workaround_enabled())
2839 if (WARN_ON_ONCE(!excl_cntrs))
2842 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2845 xl = &excl_cntrs->states[tid];
2847 lockdep_assert_held(&excl_cntrs->lock);
2849 if (c->flags & PERF_X86_EVENT_EXCL)
2850 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
2852 xl->state[cntr] = INTEL_EXCL_SHARED;
2856 intel_stop_scheduling(struct cpu_hw_events *cpuc)
2858 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2859 struct intel_excl_states *xl;
2860 int tid = cpuc->excl_thread_id;
2863 * nothing needed if in group validation mode
2865 if (cpuc->is_fake || !is_ht_workaround_enabled())
2868 * no exclusion needed
2870 if (WARN_ON_ONCE(!excl_cntrs))
2873 xl = &excl_cntrs->states[tid];
2875 xl->sched_started = false;
2877 * release shared state lock (acquired in intel_start_scheduling())
2879 raw_spin_unlock(&excl_cntrs->lock);
2882 static struct event_constraint *
2883 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
2885 WARN_ON_ONCE(!cpuc->constraint_list);
2887 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
2888 struct event_constraint *cx;
2891 * grab pre-allocated constraint entry
2893 cx = &cpuc->constraint_list[idx];
2896 * initialize dynamic constraint
2897 * with static constraint
2902 * mark constraint as dynamic
2904 cx->flags |= PERF_X86_EVENT_DYNAMIC;
2911 static struct event_constraint *
2912 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
2913 int idx, struct event_constraint *c)
2915 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2916 struct intel_excl_states *xlo;
2917 int tid = cpuc->excl_thread_id;
2921 * validating a group does not require
2922 * enforcing cross-thread exclusion
2924 if (cpuc->is_fake || !is_ht_workaround_enabled())
2928 * no exclusion needed
2930 if (WARN_ON_ONCE(!excl_cntrs))
2934 * because we modify the constraint, we need
2935 * to make a copy. Static constraints come
2936 * from static const tables.
2938 * only needed when constraint has not yet
2939 * been cloned (marked dynamic)
2941 c = dyn_constraint(cpuc, c, idx);
2944 * From here on, the constraint is dynamic.
2945 * Either it was just allocated above, or it
2946 * was allocated during a earlier invocation
2951 * state of sibling HT
2953 xlo = &excl_cntrs->states[tid ^ 1];
2956 * event requires exclusive counter access
2959 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2960 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2961 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2962 if (!cpuc->n_excl++)
2963 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2967 * Modify static constraint with current dynamic
2970 * EXCLUSIVE: sibling counter measuring exclusive event
2971 * SHARED : sibling counter measuring non-exclusive event
2972 * UNUSED : sibling counter unused
2975 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
2977 * exclusive event in sibling counter
2978 * our corresponding counter cannot be used
2979 * regardless of our event
2981 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
2982 __clear_bit(i, c->idxmsk);
2987 * if measuring an exclusive event, sibling
2988 * measuring non-exclusive, then counter cannot
2991 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
2992 __clear_bit(i, c->idxmsk);
2999 * if we return an empty mask, then switch
3000 * back to static empty constraint to avoid
3001 * the cost of freeing later on
3004 c = &emptyconstraint;
3011 static struct event_constraint *
3012 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3013 struct perf_event *event)
3015 struct event_constraint *c1, *c2;
3017 c1 = cpuc->event_constraint[idx];
3021 * - static constraint: no change across incremental scheduling calls
3022 * - dynamic constraint: handled by intel_get_excl_constraints()
3024 c2 = __intel_get_event_constraints(cpuc, idx, event);
3026 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3027 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
3028 c1->weight = c2->weight;
3032 if (cpuc->excl_cntrs)
3033 return intel_get_excl_constraints(cpuc, event, idx, c2);
3038 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3039 struct perf_event *event)
3041 struct hw_perf_event *hwc = &event->hw;
3042 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3043 int tid = cpuc->excl_thread_id;
3044 struct intel_excl_states *xl;
3047 * nothing needed if in group validation mode
3052 if (WARN_ON_ONCE(!excl_cntrs))
3055 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
3056 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
3057 if (!--cpuc->n_excl)
3058 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
3062 * If event was actually assigned, then mark the counter state as
3065 if (hwc->idx >= 0) {
3066 xl = &excl_cntrs->states[tid];
3069 * put_constraint may be called from x86_schedule_events()
3070 * which already has the lock held so here make locking
3073 if (!xl->sched_started)
3074 raw_spin_lock(&excl_cntrs->lock);
3076 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
3078 if (!xl->sched_started)
3079 raw_spin_unlock(&excl_cntrs->lock);
3084 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
3085 struct perf_event *event)
3087 struct hw_perf_event_extra *reg;
3089 reg = &event->hw.extra_reg;
3090 if (reg->idx != EXTRA_REG_NONE)
3091 __intel_shared_reg_put_constraints(cpuc, reg);
3093 reg = &event->hw.branch_reg;
3094 if (reg->idx != EXTRA_REG_NONE)
3095 __intel_shared_reg_put_constraints(cpuc, reg);
3098 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
3099 struct perf_event *event)
3101 intel_put_shared_regs_event_constraints(cpuc, event);
3104 * is PMU has exclusive counter restrictions, then
3105 * all events are subject to and must call the
3106 * put_excl_constraints() routine
3108 if (cpuc->excl_cntrs)
3109 intel_put_excl_constraints(cpuc, event);
3112 static void intel_pebs_aliases_core2(struct perf_event *event)
3114 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3116 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3117 * (0x003c) so that we can use it with PEBS.
3119 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3120 * PEBS capable. However we can use INST_RETIRED.ANY_P
3121 * (0x00c0), which is a PEBS capable event, to get the same
3124 * INST_RETIRED.ANY_P counts the number of cycles that retires
3125 * CNTMASK instructions. By setting CNTMASK to a value (16)
3126 * larger than the maximum number of instructions that can be
3127 * retired per cycle (4) and then inverting the condition, we
3128 * count all cycles that retire 16 or less instructions, which
3131 * Thereby we gain a PEBS capable cycle counter.
3133 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3135 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3136 event->hw.config = alt_config;
3140 static void intel_pebs_aliases_snb(struct perf_event *event)
3142 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3144 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3145 * (0x003c) so that we can use it with PEBS.
3147 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3148 * PEBS capable. However we can use UOPS_RETIRED.ALL
3149 * (0x01c2), which is a PEBS capable event, to get the same
3152 * UOPS_RETIRED.ALL counts the number of cycles that retires
3153 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3154 * larger than the maximum number of micro-ops that can be
3155 * retired per cycle (4) and then inverting the condition, we
3156 * count all cycles that retire 16 or less micro-ops, which
3159 * Thereby we gain a PEBS capable cycle counter.
3161 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3163 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3164 event->hw.config = alt_config;
3168 static void intel_pebs_aliases_precdist(struct perf_event *event)
3170 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3172 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3173 * (0x003c) so that we can use it with PEBS.
3175 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3176 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3177 * (0x01c0), which is a PEBS capable event, to get the same
3180 * The PREC_DIST event has special support to minimize sample
3181 * shadowing effects. One drawback is that it can be
3182 * only programmed on counter 1, but that seems like an
3183 * acceptable trade off.
3185 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3187 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3188 event->hw.config = alt_config;
3192 static void intel_pebs_aliases_ivb(struct perf_event *event)
3194 if (event->attr.precise_ip < 3)
3195 return intel_pebs_aliases_snb(event);
3196 return intel_pebs_aliases_precdist(event);
3199 static void intel_pebs_aliases_skl(struct perf_event *event)
3201 if (event->attr.precise_ip < 3)
3202 return intel_pebs_aliases_core2(event);
3203 return intel_pebs_aliases_precdist(event);
3206 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3208 unsigned long flags = x86_pmu.large_pebs_flags;
3210 if (event->attr.use_clockid)
3211 flags &= ~PERF_SAMPLE_TIME;
3212 if (!event->attr.exclude_kernel)
3213 flags &= ~PERF_SAMPLE_REGS_USER;
3214 if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
3215 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3219 static int intel_pmu_bts_config(struct perf_event *event)
3221 struct perf_event_attr *attr = &event->attr;
3223 if (unlikely(intel_pmu_has_bts(event))) {
3224 /* BTS is not supported by this architecture. */
3225 if (!x86_pmu.bts_active)
3228 /* BTS is currently only allowed for user-mode. */
3229 if (!attr->exclude_kernel)
3232 /* BTS is not allowed for precise events. */
3233 if (attr->precise_ip)
3236 /* disallow bts if conflicting events are present */
3237 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3240 event->destroy = hw_perf_lbr_event_destroy;
3246 static int core_pmu_hw_config(struct perf_event *event)
3248 int ret = x86_pmu_hw_config(event);
3253 return intel_pmu_bts_config(event);
3256 static int intel_pmu_hw_config(struct perf_event *event)
3258 int ret = x86_pmu_hw_config(event);
3263 ret = intel_pmu_bts_config(event);
3267 if (event->attr.precise_ip) {
3268 if (!(event->attr.freq || event->attr.wakeup_events)) {
3269 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
3270 if (!(event->attr.sample_type &
3271 ~intel_pmu_large_pebs_flags(event)))
3272 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
3274 if (x86_pmu.pebs_aliases)
3275 x86_pmu.pebs_aliases(event);
3277 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN)
3278 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY;
3281 if (needs_branch_stack(event)) {
3282 ret = intel_pmu_setup_lbr_filter(event);
3287 * BTS is set up earlier in this path, so don't account twice
3289 if (!unlikely(intel_pmu_has_bts(event))) {
3290 /* disallow lbr if conflicting events are present */
3291 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3294 event->destroy = hw_perf_lbr_event_destroy;
3298 if (event->attr.type != PERF_TYPE_RAW)
3301 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
3304 if (x86_pmu.version < 3)
3307 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
3310 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
3315 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
3317 if (x86_pmu.guest_get_msrs)
3318 return x86_pmu.guest_get_msrs(nr);
3322 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
3324 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
3326 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3327 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3329 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
3330 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
3331 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
3332 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
3333 arr[0].guest &= ~cpuc->pebs_enabled;
3335 arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
3338 if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) {
3340 * If PMU counter has PEBS enabled it is not enough to
3341 * disable counter on a guest entry since PEBS memory
3342 * write can overshoot guest entry and corrupt guest
3343 * memory. Disabling PEBS solves the problem.
3345 * Don't do this if the CPU already enforces it.
3347 arr[1].msr = MSR_IA32_PEBS_ENABLE;
3348 arr[1].host = cpuc->pebs_enabled;
3356 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
3358 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3359 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3362 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3363 struct perf_event *event = cpuc->events[idx];
3365 arr[idx].msr = x86_pmu_config_addr(idx);
3366 arr[idx].host = arr[idx].guest = 0;
3368 if (!test_bit(idx, cpuc->active_mask))
3371 arr[idx].host = arr[idx].guest =
3372 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
3374 if (event->attr.exclude_host)
3375 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3376 else if (event->attr.exclude_guest)
3377 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3380 *nr = x86_pmu.num_counters;
3384 static void core_pmu_enable_event(struct perf_event *event)
3386 if (!event->attr.exclude_host)
3387 x86_pmu_enable_event(event);
3390 static void core_pmu_enable_all(int added)
3392 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3395 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3396 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
3398 if (!test_bit(idx, cpuc->active_mask) ||
3399 cpuc->events[idx]->attr.exclude_host)
3402 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
3406 static int hsw_hw_config(struct perf_event *event)
3408 int ret = intel_pmu_hw_config(event);
3412 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
3414 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
3417 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
3418 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
3421 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
3422 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
3423 event->attr.precise_ip > 0))
3426 if (event_is_checkpointed(event)) {
3428 * Sampling of checkpointed events can cause situations where
3429 * the CPU constantly aborts because of a overflow, which is
3430 * then checkpointed back and ignored. Forbid checkpointing
3433 * But still allow a long sampling period, so that perf stat
3436 if (event->attr.sample_period > 0 &&
3437 event->attr.sample_period < 0x7fffffff)
3443 static struct event_constraint counter0_constraint =
3444 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
3446 static struct event_constraint counter2_constraint =
3447 EVENT_CONSTRAINT(0, 0x4, 0);
3449 static struct event_constraint fixed0_constraint =
3450 FIXED_EVENT_CONSTRAINT(0x00c0, 0);
3452 static struct event_constraint fixed0_counter0_constraint =
3453 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
3455 static struct event_constraint *
3456 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3457 struct perf_event *event)
3459 struct event_constraint *c;
3461 c = intel_get_event_constraints(cpuc, idx, event);
3463 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
3464 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
3465 if (c->idxmsk64 & (1U << 2))
3466 return &counter2_constraint;
3467 return &emptyconstraint;
3473 static struct event_constraint *
3474 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3475 struct perf_event *event)
3478 * Fixed counter 0 has less skid.
3479 * Force instruction:ppp in Fixed counter 0
3481 if ((event->attr.precise_ip == 3) &&
3482 constraint_match(&fixed0_constraint, event->hw.config))
3483 return &fixed0_constraint;
3485 return hsw_get_event_constraints(cpuc, idx, event);
3488 static struct event_constraint *
3489 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3490 struct perf_event *event)
3492 struct event_constraint *c;
3494 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
3495 if (event->attr.precise_ip == 3)
3496 return &counter0_constraint;
3498 c = intel_get_event_constraints(cpuc, idx, event);
3503 static struct event_constraint *
3504 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3505 struct perf_event *event)
3507 struct event_constraint *c;
3510 * :ppp means to do reduced skid PEBS,
3511 * which is available on PMC0 and fixed counter 0.
3513 if (event->attr.precise_ip == 3) {
3514 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
3515 if (constraint_match(&fixed0_constraint, event->hw.config))
3516 return &fixed0_counter0_constraint;
3518 return &counter0_constraint;
3521 c = intel_get_event_constraints(cpuc, idx, event);
3526 static bool allow_tsx_force_abort = true;
3528 static struct event_constraint *
3529 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3530 struct perf_event *event)
3532 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
3535 * Without TFA we must not use PMC3.
3537 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
3538 c = dyn_constraint(cpuc, c, idx);
3539 c->idxmsk64 &= ~(1ULL << 3);
3549 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
3550 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
3551 * the two to enforce a minimum period of 128 (the smallest value that has bits
3552 * 0-5 cleared and >= 100).
3554 * Because of how the code in x86_perf_event_set_period() works, the truncation
3555 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
3556 * to make up for the 'lost' events due to carrying the 'error' in period_left.
3558 * Therefore the effective (average) period matches the requested period,
3559 * despite coarser hardware granularity.
3561 static u64 bdw_limit_period(struct perf_event *event, u64 left)
3563 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
3564 X86_CONFIG(.event=0xc0, .umask=0x01)) {
3572 PMU_FORMAT_ATTR(event, "config:0-7" );
3573 PMU_FORMAT_ATTR(umask, "config:8-15" );
3574 PMU_FORMAT_ATTR(edge, "config:18" );
3575 PMU_FORMAT_ATTR(pc, "config:19" );
3576 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
3577 PMU_FORMAT_ATTR(inv, "config:23" );
3578 PMU_FORMAT_ATTR(cmask, "config:24-31" );
3579 PMU_FORMAT_ATTR(in_tx, "config:32");
3580 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
3582 static struct attribute *intel_arch_formats_attr[] = {
3583 &format_attr_event.attr,
3584 &format_attr_umask.attr,
3585 &format_attr_edge.attr,
3586 &format_attr_pc.attr,
3587 &format_attr_inv.attr,
3588 &format_attr_cmask.attr,
3592 ssize_t intel_event_sysfs_show(char *page, u64 config)
3594 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
3596 return x86_event_sysfs_show(page, config, event);
3599 static struct intel_shared_regs *allocate_shared_regs(int cpu)
3601 struct intel_shared_regs *regs;
3604 regs = kzalloc_node(sizeof(struct intel_shared_regs),
3605 GFP_KERNEL, cpu_to_node(cpu));
3608 * initialize the locks to keep lockdep happy
3610 for (i = 0; i < EXTRA_REG_MAX; i++)
3611 raw_spin_lock_init(®s->regs[i].lock);
3618 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
3620 struct intel_excl_cntrs *c;
3622 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
3623 GFP_KERNEL, cpu_to_node(cpu));
3625 raw_spin_lock_init(&c->lock);
3632 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
3634 cpuc->pebs_record_size = x86_pmu.pebs_record_size;
3636 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
3637 cpuc->shared_regs = allocate_shared_regs(cpu);
3638 if (!cpuc->shared_regs)
3642 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) {
3643 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
3645 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
3646 if (!cpuc->constraint_list)
3647 goto err_shared_regs;
3650 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3651 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
3652 if (!cpuc->excl_cntrs)
3653 goto err_constraint_list;
3655 cpuc->excl_thread_id = 0;
3660 err_constraint_list:
3661 kfree(cpuc->constraint_list);
3662 cpuc->constraint_list = NULL;
3665 kfree(cpuc->shared_regs);
3666 cpuc->shared_regs = NULL;
3672 static int intel_pmu_cpu_prepare(int cpu)
3674 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
3677 static void flip_smm_bit(void *data)
3679 unsigned long set = *(unsigned long *)data;
3682 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
3683 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
3685 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
3686 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
3690 static void intel_pmu_cpu_starting(int cpu)
3692 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3693 int core_id = topology_core_id(cpu);
3696 init_debug_store_on_cpu(cpu);
3698 * Deal with CPUs that don't clear their LBRs on power-up.
3700 intel_pmu_lbr_reset();
3702 cpuc->lbr_sel = NULL;
3704 if (x86_pmu.flags & PMU_FL_TFA) {
3705 WARN_ON_ONCE(cpuc->tfa_shadow);
3706 cpuc->tfa_shadow = ~0ULL;
3707 intel_set_tfa(cpuc, false);
3710 if (x86_pmu.version > 1)
3711 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
3713 if (x86_pmu.counter_freezing)
3714 enable_counter_freeze();
3716 if (!cpuc->shared_regs)
3719 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
3720 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
3721 struct intel_shared_regs *pc;
3723 pc = per_cpu(cpu_hw_events, i).shared_regs;
3724 if (pc && pc->core_id == core_id) {
3725 cpuc->kfree_on_online[0] = cpuc->shared_regs;
3726 cpuc->shared_regs = pc;
3730 cpuc->shared_regs->core_id = core_id;
3731 cpuc->shared_regs->refcnt++;
3734 if (x86_pmu.lbr_sel_map)
3735 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
3737 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3738 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
3739 struct cpu_hw_events *sibling;
3740 struct intel_excl_cntrs *c;
3742 sibling = &per_cpu(cpu_hw_events, i);
3743 c = sibling->excl_cntrs;
3744 if (c && c->core_id == core_id) {
3745 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
3746 cpuc->excl_cntrs = c;
3747 if (!sibling->excl_thread_id)
3748 cpuc->excl_thread_id = 1;
3752 cpuc->excl_cntrs->core_id = core_id;
3753 cpuc->excl_cntrs->refcnt++;
3757 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
3759 struct intel_excl_cntrs *c;
3761 c = cpuc->excl_cntrs;
3763 if (c->core_id == -1 || --c->refcnt == 0)
3765 cpuc->excl_cntrs = NULL;
3768 kfree(cpuc->constraint_list);
3769 cpuc->constraint_list = NULL;
3772 static void intel_pmu_cpu_dying(int cpu)
3774 fini_debug_store_on_cpu(cpu);
3776 if (x86_pmu.counter_freezing)
3777 disable_counter_freeze();
3780 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
3782 struct intel_shared_regs *pc;
3784 pc = cpuc->shared_regs;
3786 if (pc->core_id == -1 || --pc->refcnt == 0)
3788 cpuc->shared_regs = NULL;
3791 free_excl_cntrs(cpuc);
3794 static void intel_pmu_cpu_dead(int cpu)
3796 intel_cpuc_finish(&per_cpu(cpu_hw_events, cpu));
3799 static void intel_pmu_sched_task(struct perf_event_context *ctx,
3802 intel_pmu_pebs_sched_task(ctx, sched_in);
3803 intel_pmu_lbr_sched_task(ctx, sched_in);
3806 static int intel_pmu_check_period(struct perf_event *event, u64 value)
3808 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
3811 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
3813 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
3815 PMU_FORMAT_ATTR(frontend, "config1:0-23");
3817 static struct attribute *intel_arch3_formats_attr[] = {
3818 &format_attr_event.attr,
3819 &format_attr_umask.attr,
3820 &format_attr_edge.attr,
3821 &format_attr_pc.attr,
3822 &format_attr_any.attr,
3823 &format_attr_inv.attr,
3824 &format_attr_cmask.attr,
3828 static struct attribute *hsw_format_attr[] = {
3829 &format_attr_in_tx.attr,
3830 &format_attr_in_tx_cp.attr,
3831 &format_attr_offcore_rsp.attr,
3832 &format_attr_ldlat.attr,
3836 static struct attribute *nhm_format_attr[] = {
3837 &format_attr_offcore_rsp.attr,
3838 &format_attr_ldlat.attr,
3842 static struct attribute *slm_format_attr[] = {
3843 &format_attr_offcore_rsp.attr,
3847 static struct attribute *skl_format_attr[] = {
3848 &format_attr_frontend.attr,
3852 static __initconst const struct x86_pmu core_pmu = {
3854 .handle_irq = x86_pmu_handle_irq,
3855 .disable_all = x86_pmu_disable_all,
3856 .enable_all = core_pmu_enable_all,
3857 .enable = core_pmu_enable_event,
3858 .disable = x86_pmu_disable_event,
3859 .hw_config = core_pmu_hw_config,
3860 .schedule_events = x86_schedule_events,
3861 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3862 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3863 .event_map = intel_pmu_event_map,
3864 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3866 .large_pebs_flags = LARGE_PEBS_FLAGS,
3869 * Intel PMCs cannot be accessed sanely above 32-bit width,
3870 * so we install an artificial 1<<31 period regardless of
3871 * the generic event period:
3873 .max_period = (1ULL<<31) - 1,
3874 .get_event_constraints = intel_get_event_constraints,
3875 .put_event_constraints = intel_put_event_constraints,
3876 .event_constraints = intel_core_event_constraints,
3877 .guest_get_msrs = core_guest_get_msrs,
3878 .format_attrs = intel_arch_formats_attr,
3879 .events_sysfs_show = intel_event_sysfs_show,
3882 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
3883 * together with PMU version 1 and thus be using core_pmu with
3884 * shared_regs. We need following callbacks here to allocate
3887 .cpu_prepare = intel_pmu_cpu_prepare,
3888 .cpu_starting = intel_pmu_cpu_starting,
3889 .cpu_dying = intel_pmu_cpu_dying,
3890 .cpu_dead = intel_pmu_cpu_dead,
3892 .check_period = intel_pmu_check_period,
3895 static struct attribute *intel_pmu_attrs[];
3897 static __initconst const struct x86_pmu intel_pmu = {
3899 .handle_irq = intel_pmu_handle_irq,
3900 .disable_all = intel_pmu_disable_all,
3901 .enable_all = intel_pmu_enable_all,
3902 .enable = intel_pmu_enable_event,
3903 .disable = intel_pmu_disable_event,
3904 .add = intel_pmu_add_event,
3905 .del = intel_pmu_del_event,
3906 .read = intel_pmu_read_event,
3907 .hw_config = intel_pmu_hw_config,
3908 .schedule_events = x86_schedule_events,
3909 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3910 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3911 .event_map = intel_pmu_event_map,
3912 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3914 .large_pebs_flags = LARGE_PEBS_FLAGS,
3916 * Intel PMCs cannot be accessed sanely above 32 bit width,
3917 * so we install an artificial 1<<31 period regardless of
3918 * the generic event period:
3920 .max_period = (1ULL << 31) - 1,
3921 .get_event_constraints = intel_get_event_constraints,
3922 .put_event_constraints = intel_put_event_constraints,
3923 .pebs_aliases = intel_pebs_aliases_core2,
3925 .format_attrs = intel_arch3_formats_attr,
3926 .events_sysfs_show = intel_event_sysfs_show,
3928 .attrs = intel_pmu_attrs,
3930 .cpu_prepare = intel_pmu_cpu_prepare,
3931 .cpu_starting = intel_pmu_cpu_starting,
3932 .cpu_dying = intel_pmu_cpu_dying,
3933 .cpu_dead = intel_pmu_cpu_dead,
3935 .guest_get_msrs = intel_guest_get_msrs,
3936 .sched_task = intel_pmu_sched_task,
3938 .check_period = intel_pmu_check_period,
3941 static __init void intel_clovertown_quirk(void)
3944 * PEBS is unreliable due to:
3946 * AJ67 - PEBS may experience CPL leaks
3947 * AJ68 - PEBS PMI may be delayed by one event
3948 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
3949 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
3951 * AJ67 could be worked around by restricting the OS/USR flags.
3952 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
3954 * AJ106 could possibly be worked around by not allowing LBR
3955 * usage from PEBS, including the fixup.
3956 * AJ68 could possibly be worked around by always programming
3957 * a pebs_event_reset[0] value and coping with the lost events.
3959 * But taken together it might just make sense to not enable PEBS on
3962 pr_warn("PEBS disabled due to CPU errata\n");
3964 x86_pmu.pebs_constraints = NULL;
3967 static const struct x86_cpu_desc isolation_ucodes[] = {
3968 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_CORE, 3, 0x0000001f),
3969 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_ULT, 1, 0x0000001e),
3970 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_GT3E, 1, 0x00000015),
3971 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037),
3972 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a),
3973 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_CORE, 4, 0x00000023),
3974 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_GT3E, 1, 0x00000014),
3975 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D, 2, 0x00000010),
3976 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D, 3, 0x07000009),
3977 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D, 4, 0x0f000009),
3978 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D, 5, 0x0e000002),
3979 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 2, 0x0b000014),
3980 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021),
3981 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000),
3982 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_MOBILE, 3, 0x0000007c),
3983 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_DESKTOP, 3, 0x0000007c),
3984 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 9, 0x0000004e),
3985 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_MOBILE, 9, 0x0000004e),
3986 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_MOBILE, 10, 0x0000004e),
3987 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_MOBILE, 11, 0x0000004e),
3988 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_MOBILE, 12, 0x0000004e),
3989 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 10, 0x0000004e),
3990 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 11, 0x0000004e),
3991 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 12, 0x0000004e),
3992 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 13, 0x0000004e),
3996 static void intel_check_pebs_isolation(void)
3998 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes);
4001 static __init void intel_pebs_isolation_quirk(void)
4003 WARN_ON_ONCE(x86_pmu.check_microcode);
4004 x86_pmu.check_microcode = intel_check_pebs_isolation;
4005 intel_check_pebs_isolation();
4008 static const struct x86_cpu_desc pebs_ucodes[] = {
4009 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028),
4010 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618),
4011 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c),
4015 static bool intel_snb_pebs_broken(void)
4017 return !x86_cpu_has_min_microcode_rev(pebs_ucodes);
4020 static void intel_snb_check_microcode(void)
4022 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
4026 * Serialized by the microcode lock..
4028 if (x86_pmu.pebs_broken) {
4029 pr_info("PEBS enabled due to microcode update\n");
4030 x86_pmu.pebs_broken = 0;
4032 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
4033 x86_pmu.pebs_broken = 1;
4037 static bool is_lbr_from(unsigned long msr)
4039 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
4041 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
4045 * Under certain circumstances, access certain MSR may cause #GP.
4046 * The function tests if the input MSR can be safely accessed.
4048 static bool check_msr(unsigned long msr, u64 mask)
4050 u64 val_old, val_new, val_tmp;
4053 * Read the current value, change it and read it back to see if it
4054 * matches, this is needed to detect certain hardware emulators
4055 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
4057 if (rdmsrl_safe(msr, &val_old))
4061 * Only change the bits which can be updated by wrmsrl.
4063 val_tmp = val_old ^ mask;
4065 if (is_lbr_from(msr))
4066 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
4068 if (wrmsrl_safe(msr, val_tmp) ||
4069 rdmsrl_safe(msr, &val_new))
4073 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
4074 * should equal rdmsrl()'s even with the quirk.
4076 if (val_new != val_tmp)
4079 if (is_lbr_from(msr))
4080 val_old = lbr_from_signext_quirk_wr(val_old);
4082 /* Here it's sure that the MSR can be safely accessed.
4083 * Restore the old value and return.
4085 wrmsrl(msr, val_old);
4090 static __init void intel_sandybridge_quirk(void)
4092 x86_pmu.check_microcode = intel_snb_check_microcode;
4094 intel_snb_check_microcode();
4098 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
4099 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
4100 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
4101 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
4102 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
4103 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
4104 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
4105 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
4108 static __init void intel_arch_events_quirk(void)
4112 /* disable event that reported as not presend by cpuid */
4113 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
4114 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
4115 pr_warn("CPUID marked event: \'%s\' unavailable\n",
4116 intel_arch_events_map[bit].name);
4120 static __init void intel_nehalem_quirk(void)
4122 union cpuid10_ebx ebx;
4124 ebx.full = x86_pmu.events_maskl;
4125 if (ebx.split.no_branch_misses_retired) {
4127 * Erratum AAJ80 detected, we work it around by using
4128 * the BR_MISP_EXEC.ANY event. This will over-count
4129 * branch-misses, but it's still much better than the
4130 * architectural event which is often completely bogus:
4132 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
4133 ebx.split.no_branch_misses_retired = 0;
4134 x86_pmu.events_maskl = ebx.full;
4135 pr_info("CPU erratum AAJ80 worked around\n");
4139 static const struct x86_cpu_desc counter_freezing_ucodes[] = {
4140 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 2, 0x0000000e),
4141 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 9, 0x0000002e),
4142 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 10, 0x00000008),
4143 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_X, 1, 0x00000028),
4144 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 1, 0x00000028),
4145 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 8, 0x00000006),
4149 static bool intel_counter_freezing_broken(void)
4151 return !x86_cpu_has_min_microcode_rev(counter_freezing_ucodes);
4154 static __init void intel_counter_freezing_quirk(void)
4156 /* Check if it's already disabled */
4157 if (disable_counter_freezing)
4161 * If the system starts with the wrong ucode, leave the
4162 * counter-freezing feature permanently disabled.
4164 if (intel_counter_freezing_broken()) {
4165 pr_info("PMU counter freezing disabled due to CPU errata,"
4166 "please upgrade microcode\n");
4167 x86_pmu.counter_freezing = false;
4168 x86_pmu.handle_irq = intel_pmu_handle_irq;
4173 * enable software workaround for errata:
4178 * Only needed when HT is enabled. However detecting
4179 * if HT is enabled is difficult (model specific). So instead,
4180 * we enable the workaround in the early boot, and verify if
4181 * it is needed in a later initcall phase once we have valid
4182 * topology information to check if HT is actually enabled
4184 static __init void intel_ht_bug(void)
4186 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
4188 x86_pmu.start_scheduling = intel_start_scheduling;
4189 x86_pmu.commit_scheduling = intel_commit_scheduling;
4190 x86_pmu.stop_scheduling = intel_stop_scheduling;
4193 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
4194 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
4196 /* Haswell special events */
4197 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
4198 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
4199 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
4200 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
4201 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
4202 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
4203 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
4204 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
4205 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
4206 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
4207 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
4208 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4210 static struct attribute *hsw_events_attrs[] = {
4211 EVENT_PTR(td_slots_issued),
4212 EVENT_PTR(td_slots_retired),
4213 EVENT_PTR(td_fetch_bubbles),
4214 EVENT_PTR(td_total_slots),
4215 EVENT_PTR(td_total_slots_scale),
4216 EVENT_PTR(td_recovery_bubbles),
4217 EVENT_PTR(td_recovery_bubbles_scale),
4221 static struct attribute *hsw_mem_events_attrs[] = {
4222 EVENT_PTR(mem_ld_hsw),
4223 EVENT_PTR(mem_st_hsw),
4227 static struct attribute *hsw_tsx_events_attrs[] = {
4228 EVENT_PTR(tx_start),
4229 EVENT_PTR(tx_commit),
4230 EVENT_PTR(tx_abort),
4231 EVENT_PTR(tx_capacity),
4232 EVENT_PTR(tx_conflict),
4233 EVENT_PTR(el_start),
4234 EVENT_PTR(el_commit),
4235 EVENT_PTR(el_abort),
4236 EVENT_PTR(el_capacity),
4237 EVENT_PTR(el_conflict),
4238 EVENT_PTR(cycles_t),
4239 EVENT_PTR(cycles_ct),
4243 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80");
4244 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
4245 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80");
4246 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
4248 static struct attribute *icl_events_attrs[] = {
4249 EVENT_PTR(mem_ld_hsw),
4250 EVENT_PTR(mem_st_hsw),
4254 static struct attribute *icl_tsx_events_attrs[] = {
4255 EVENT_PTR(tx_start),
4256 EVENT_PTR(tx_abort),
4257 EVENT_PTR(tx_commit),
4258 EVENT_PTR(tx_capacity_read),
4259 EVENT_PTR(tx_capacity_write),
4260 EVENT_PTR(tx_conflict),
4261 EVENT_PTR(el_start),
4262 EVENT_PTR(el_abort),
4263 EVENT_PTR(el_commit),
4264 EVENT_PTR(el_capacity_read),
4265 EVENT_PTR(el_capacity_write),
4266 EVENT_PTR(el_conflict),
4267 EVENT_PTR(cycles_t),
4268 EVENT_PTR(cycles_ct),
4272 static __init struct attribute **get_icl_events_attrs(void)
4274 return boot_cpu_has(X86_FEATURE_RTM) ?
4275 merge_attr(icl_events_attrs, icl_tsx_events_attrs) :
4279 static ssize_t freeze_on_smi_show(struct device *cdev,
4280 struct device_attribute *attr,
4283 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
4286 static DEFINE_MUTEX(freeze_on_smi_mutex);
4288 static ssize_t freeze_on_smi_store(struct device *cdev,
4289 struct device_attribute *attr,
4290 const char *buf, size_t count)
4295 ret = kstrtoul(buf, 0, &val);
4302 mutex_lock(&freeze_on_smi_mutex);
4304 if (x86_pmu.attr_freeze_on_smi == val)
4307 x86_pmu.attr_freeze_on_smi = val;
4310 on_each_cpu(flip_smm_bit, &val, 1);
4313 mutex_unlock(&freeze_on_smi_mutex);
4318 static void update_tfa_sched(void *ignored)
4320 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4323 * check if PMC3 is used
4324 * and if so force schedule out for all event types all contexts
4326 if (test_bit(3, cpuc->active_mask))
4327 perf_pmu_resched(x86_get_pmu());
4330 static ssize_t show_sysctl_tfa(struct device *cdev,
4331 struct device_attribute *attr,
4334 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
4337 static ssize_t set_sysctl_tfa(struct device *cdev,
4338 struct device_attribute *attr,
4339 const char *buf, size_t count)
4344 ret = kstrtobool(buf, &val);
4349 if (val == allow_tsx_force_abort)
4352 allow_tsx_force_abort = val;
4355 on_each_cpu(update_tfa_sched, NULL, 1);
4362 static DEVICE_ATTR_RW(freeze_on_smi);
4364 static ssize_t branches_show(struct device *cdev,
4365 struct device_attribute *attr,
4368 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
4371 static DEVICE_ATTR_RO(branches);
4373 static struct attribute *lbr_attrs[] = {
4374 &dev_attr_branches.attr,
4378 static char pmu_name_str[30];
4380 static ssize_t pmu_name_show(struct device *cdev,
4381 struct device_attribute *attr,
4384 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str);
4387 static DEVICE_ATTR_RO(pmu_name);
4389 static struct attribute *intel_pmu_caps_attrs[] = {
4390 &dev_attr_pmu_name.attr,
4394 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
4398 static struct attribute *intel_pmu_attrs[] = {
4399 &dev_attr_freeze_on_smi.attr,
4400 NULL, /* &dev_attr_allow_tsx_force_abort.attr.attr */
4404 static __init struct attribute **
4405 get_events_attrs(struct attribute **base,
4406 struct attribute **mem,
4407 struct attribute **tsx)
4409 struct attribute **attrs = base;
4410 struct attribute **old;
4412 if (mem && x86_pmu.pebs)
4413 attrs = merge_attr(attrs, mem);
4415 if (tsx && boot_cpu_has(X86_FEATURE_RTM)) {
4417 attrs = merge_attr(attrs, tsx);
4425 __init int intel_pmu_init(void)
4427 struct attribute **extra_attr = NULL;
4428 struct attribute **mem_attr = NULL;
4429 struct attribute **tsx_attr = NULL;
4430 struct attribute **to_free = NULL;
4431 union cpuid10_edx edx;
4432 union cpuid10_eax eax;
4433 union cpuid10_ebx ebx;
4434 struct event_constraint *c;
4435 unsigned int unused;
4436 struct extra_reg *er;
4440 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
4441 switch (boot_cpu_data.x86) {
4443 return p6_pmu_init();
4445 return knc_pmu_init();
4447 return p4_pmu_init();
4453 * Check whether the Architectural PerfMon supports
4454 * Branch Misses Retired hw_event or not.
4456 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
4457 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
4460 version = eax.split.version_id;
4464 x86_pmu = intel_pmu;
4466 x86_pmu.version = version;
4467 x86_pmu.num_counters = eax.split.num_counters;
4468 x86_pmu.cntval_bits = eax.split.bit_width;
4469 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
4471 x86_pmu.events_maskl = ebx.full;
4472 x86_pmu.events_mask_len = eax.split.mask_length;
4474 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
4477 * Quirk: v2 perfmon does not report fixed-purpose events, so
4478 * assume at least 3 events, when not running in a hypervisor:
4481 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
4483 x86_pmu.num_counters_fixed =
4484 max((int)edx.split.num_counters_fixed, assume);
4488 x86_pmu.counter_freezing = !disable_counter_freezing;
4490 if (boot_cpu_has(X86_FEATURE_PDCM)) {
4493 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
4494 x86_pmu.intel_cap.capabilities = capabilities;
4499 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
4502 * Install the hw-cache-events table:
4504 switch (boot_cpu_data.x86_model) {
4505 case INTEL_FAM6_CORE_YONAH:
4506 pr_cont("Core events, ");
4510 case INTEL_FAM6_CORE2_MEROM:
4511 x86_add_quirk(intel_clovertown_quirk);
4514 case INTEL_FAM6_CORE2_MEROM_L:
4515 case INTEL_FAM6_CORE2_PENRYN:
4516 case INTEL_FAM6_CORE2_DUNNINGTON:
4517 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
4518 sizeof(hw_cache_event_ids));
4520 intel_pmu_lbr_init_core();
4522 x86_pmu.event_constraints = intel_core2_event_constraints;
4523 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
4524 pr_cont("Core2 events, ");
4528 case INTEL_FAM6_NEHALEM:
4529 case INTEL_FAM6_NEHALEM_EP:
4530 case INTEL_FAM6_NEHALEM_EX:
4531 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
4532 sizeof(hw_cache_event_ids));
4533 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
4534 sizeof(hw_cache_extra_regs));
4536 intel_pmu_lbr_init_nhm();
4538 x86_pmu.event_constraints = intel_nehalem_event_constraints;
4539 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
4540 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
4541 x86_pmu.extra_regs = intel_nehalem_extra_regs;
4543 mem_attr = nhm_mem_events_attrs;
4545 /* UOPS_ISSUED.STALLED_CYCLES */
4546 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4547 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4548 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
4549 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4550 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
4552 intel_pmu_pebs_data_source_nhm();
4553 x86_add_quirk(intel_nehalem_quirk);
4554 x86_pmu.pebs_no_tlb = 1;
4555 extra_attr = nhm_format_attr;
4557 pr_cont("Nehalem events, ");
4561 case INTEL_FAM6_ATOM_BONNELL:
4562 case INTEL_FAM6_ATOM_BONNELL_MID:
4563 case INTEL_FAM6_ATOM_SALTWELL:
4564 case INTEL_FAM6_ATOM_SALTWELL_MID:
4565 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
4566 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
4567 sizeof(hw_cache_event_ids));
4569 intel_pmu_lbr_init_atom();
4571 x86_pmu.event_constraints = intel_gen_event_constraints;
4572 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
4573 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
4574 pr_cont("Atom events, ");
4578 case INTEL_FAM6_ATOM_SILVERMONT:
4579 case INTEL_FAM6_ATOM_SILVERMONT_X:
4580 case INTEL_FAM6_ATOM_SILVERMONT_MID:
4581 case INTEL_FAM6_ATOM_AIRMONT:
4582 case INTEL_FAM6_ATOM_AIRMONT_MID:
4583 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
4584 sizeof(hw_cache_event_ids));
4585 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
4586 sizeof(hw_cache_extra_regs));
4588 intel_pmu_lbr_init_slm();
4590 x86_pmu.event_constraints = intel_slm_event_constraints;
4591 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
4592 x86_pmu.extra_regs = intel_slm_extra_regs;
4593 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4594 x86_pmu.cpu_events = slm_events_attrs;
4595 extra_attr = slm_format_attr;
4596 pr_cont("Silvermont events, ");
4597 name = "silvermont";
4600 case INTEL_FAM6_ATOM_GOLDMONT:
4601 case INTEL_FAM6_ATOM_GOLDMONT_X:
4602 x86_add_quirk(intel_counter_freezing_quirk);
4603 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
4604 sizeof(hw_cache_event_ids));
4605 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
4606 sizeof(hw_cache_extra_regs));
4608 intel_pmu_lbr_init_skl();
4610 x86_pmu.event_constraints = intel_slm_event_constraints;
4611 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
4612 x86_pmu.extra_regs = intel_glm_extra_regs;
4614 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
4615 * for precise cycles.
4616 * :pp is identical to :ppp
4618 x86_pmu.pebs_aliases = NULL;
4619 x86_pmu.pebs_prec_dist = true;
4620 x86_pmu.lbr_pt_coexist = true;
4621 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4622 x86_pmu.cpu_events = glm_events_attrs;
4623 extra_attr = slm_format_attr;
4624 pr_cont("Goldmont events, ");
4628 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
4629 x86_add_quirk(intel_counter_freezing_quirk);
4630 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
4631 sizeof(hw_cache_event_ids));
4632 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
4633 sizeof(hw_cache_extra_regs));
4635 intel_pmu_lbr_init_skl();
4637 x86_pmu.event_constraints = intel_slm_event_constraints;
4638 x86_pmu.extra_regs = intel_glm_extra_regs;
4640 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
4641 * for precise cycles.
4643 x86_pmu.pebs_aliases = NULL;
4644 x86_pmu.pebs_prec_dist = true;
4645 x86_pmu.lbr_pt_coexist = true;
4646 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4647 x86_pmu.flags |= PMU_FL_PEBS_ALL;
4648 x86_pmu.get_event_constraints = glp_get_event_constraints;
4649 x86_pmu.cpu_events = glm_events_attrs;
4650 /* Goldmont Plus has 4-wide pipeline */
4651 event_attr_td_total_slots_scale_glm.event_str = "4";
4652 extra_attr = slm_format_attr;
4653 pr_cont("Goldmont plus events, ");
4654 name = "goldmont_plus";
4657 case INTEL_FAM6_ATOM_TREMONT_X:
4658 x86_pmu.late_ack = true;
4659 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
4660 sizeof(hw_cache_event_ids));
4661 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
4662 sizeof(hw_cache_extra_regs));
4663 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
4665 intel_pmu_lbr_init_skl();
4667 x86_pmu.event_constraints = intel_slm_event_constraints;
4668 x86_pmu.extra_regs = intel_tnt_extra_regs;
4670 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
4671 * for precise cycles.
4673 x86_pmu.pebs_aliases = NULL;
4674 x86_pmu.pebs_prec_dist = true;
4675 x86_pmu.lbr_pt_coexist = true;
4676 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4677 x86_pmu.get_event_constraints = tnt_get_event_constraints;
4678 extra_attr = slm_format_attr;
4679 pr_cont("Tremont events, ");
4683 case INTEL_FAM6_WESTMERE:
4684 case INTEL_FAM6_WESTMERE_EP:
4685 case INTEL_FAM6_WESTMERE_EX:
4686 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
4687 sizeof(hw_cache_event_ids));
4688 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
4689 sizeof(hw_cache_extra_regs));
4691 intel_pmu_lbr_init_nhm();
4693 x86_pmu.event_constraints = intel_westmere_event_constraints;
4694 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
4695 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
4696 x86_pmu.extra_regs = intel_westmere_extra_regs;
4697 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4699 mem_attr = nhm_mem_events_attrs;
4701 /* UOPS_ISSUED.STALLED_CYCLES */
4702 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4703 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4704 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
4705 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4706 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
4708 intel_pmu_pebs_data_source_nhm();
4709 extra_attr = nhm_format_attr;
4710 pr_cont("Westmere events, ");
4714 case INTEL_FAM6_SANDYBRIDGE:
4715 case INTEL_FAM6_SANDYBRIDGE_X:
4716 x86_add_quirk(intel_sandybridge_quirk);
4717 x86_add_quirk(intel_ht_bug);
4718 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
4719 sizeof(hw_cache_event_ids));
4720 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
4721 sizeof(hw_cache_extra_regs));
4723 intel_pmu_lbr_init_snb();
4725 x86_pmu.event_constraints = intel_snb_event_constraints;
4726 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
4727 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
4728 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
4729 x86_pmu.extra_regs = intel_snbep_extra_regs;
4731 x86_pmu.extra_regs = intel_snb_extra_regs;
4734 /* all extra regs are per-cpu when HT is on */
4735 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4736 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4738 x86_pmu.cpu_events = snb_events_attrs;
4739 mem_attr = snb_mem_events_attrs;
4741 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
4742 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4743 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4744 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
4745 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4746 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
4748 extra_attr = nhm_format_attr;
4750 pr_cont("SandyBridge events, ");
4751 name = "sandybridge";
4754 case INTEL_FAM6_IVYBRIDGE:
4755 case INTEL_FAM6_IVYBRIDGE_X:
4756 x86_add_quirk(intel_ht_bug);
4757 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
4758 sizeof(hw_cache_event_ids));
4759 /* dTLB-load-misses on IVB is different than SNB */
4760 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
4762 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
4763 sizeof(hw_cache_extra_regs));
4765 intel_pmu_lbr_init_snb();
4767 x86_pmu.event_constraints = intel_ivb_event_constraints;
4768 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
4769 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4770 x86_pmu.pebs_prec_dist = true;
4771 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
4772 x86_pmu.extra_regs = intel_snbep_extra_regs;
4774 x86_pmu.extra_regs = intel_snb_extra_regs;
4775 /* all extra regs are per-cpu when HT is on */
4776 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4777 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4779 x86_pmu.cpu_events = snb_events_attrs;
4780 mem_attr = snb_mem_events_attrs;
4782 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
4783 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4784 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4786 extra_attr = nhm_format_attr;
4788 pr_cont("IvyBridge events, ");
4793 case INTEL_FAM6_HASWELL_CORE:
4794 case INTEL_FAM6_HASWELL_X:
4795 case INTEL_FAM6_HASWELL_ULT:
4796 case INTEL_FAM6_HASWELL_GT3E:
4797 x86_add_quirk(intel_ht_bug);
4798 x86_add_quirk(intel_pebs_isolation_quirk);
4799 x86_pmu.late_ack = true;
4800 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4801 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4803 intel_pmu_lbr_init_hsw();
4805 x86_pmu.event_constraints = intel_hsw_event_constraints;
4806 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
4807 x86_pmu.extra_regs = intel_snbep_extra_regs;
4808 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4809 x86_pmu.pebs_prec_dist = true;
4810 /* all extra regs are per-cpu when HT is on */
4811 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4812 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4814 x86_pmu.hw_config = hsw_hw_config;
4815 x86_pmu.get_event_constraints = hsw_get_event_constraints;
4816 x86_pmu.cpu_events = hsw_events_attrs;
4817 x86_pmu.lbr_double_abort = true;
4818 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4819 hsw_format_attr : nhm_format_attr;
4820 mem_attr = hsw_mem_events_attrs;
4821 tsx_attr = hsw_tsx_events_attrs;
4822 pr_cont("Haswell events, ");
4826 case INTEL_FAM6_BROADWELL_CORE:
4827 case INTEL_FAM6_BROADWELL_XEON_D:
4828 case INTEL_FAM6_BROADWELL_GT3E:
4829 case INTEL_FAM6_BROADWELL_X:
4830 x86_add_quirk(intel_pebs_isolation_quirk);
4831 x86_pmu.late_ack = true;
4832 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4833 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4835 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
4836 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
4837 BDW_L3_MISS|HSW_SNOOP_DRAM;
4838 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
4840 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
4841 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
4842 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
4843 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
4845 intel_pmu_lbr_init_hsw();
4847 x86_pmu.event_constraints = intel_bdw_event_constraints;
4848 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
4849 x86_pmu.extra_regs = intel_snbep_extra_regs;
4850 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4851 x86_pmu.pebs_prec_dist = true;
4852 /* all extra regs are per-cpu when HT is on */
4853 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4854 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4856 x86_pmu.hw_config = hsw_hw_config;
4857 x86_pmu.get_event_constraints = hsw_get_event_constraints;
4858 x86_pmu.cpu_events = hsw_events_attrs;
4859 x86_pmu.limit_period = bdw_limit_period;
4860 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4861 hsw_format_attr : nhm_format_attr;
4862 mem_attr = hsw_mem_events_attrs;
4863 tsx_attr = hsw_tsx_events_attrs;
4864 pr_cont("Broadwell events, ");
4868 case INTEL_FAM6_XEON_PHI_KNL:
4869 case INTEL_FAM6_XEON_PHI_KNM:
4870 memcpy(hw_cache_event_ids,
4871 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4872 memcpy(hw_cache_extra_regs,
4873 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4874 intel_pmu_lbr_init_knl();
4876 x86_pmu.event_constraints = intel_slm_event_constraints;
4877 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
4878 x86_pmu.extra_regs = intel_knl_extra_regs;
4880 /* all extra regs are per-cpu when HT is on */
4881 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4882 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4883 extra_attr = slm_format_attr;
4884 pr_cont("Knights Landing/Mill events, ");
4885 name = "knights-landing";
4888 case INTEL_FAM6_SKYLAKE_MOBILE:
4889 case INTEL_FAM6_SKYLAKE_DESKTOP:
4890 case INTEL_FAM6_SKYLAKE_X:
4891 case INTEL_FAM6_KABYLAKE_MOBILE:
4892 case INTEL_FAM6_KABYLAKE_DESKTOP:
4893 x86_add_quirk(intel_pebs_isolation_quirk);
4894 x86_pmu.late_ack = true;
4895 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4896 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4897 intel_pmu_lbr_init_skl();
4899 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
4900 event_attr_td_recovery_bubbles.event_str_noht =
4901 "event=0xd,umask=0x1,cmask=1";
4902 event_attr_td_recovery_bubbles.event_str_ht =
4903 "event=0xd,umask=0x1,cmask=1,any=1";
4905 x86_pmu.event_constraints = intel_skl_event_constraints;
4906 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
4907 x86_pmu.extra_regs = intel_skl_extra_regs;
4908 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
4909 x86_pmu.pebs_prec_dist = true;
4910 /* all extra regs are per-cpu when HT is on */
4911 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4912 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4914 x86_pmu.hw_config = hsw_hw_config;
4915 x86_pmu.get_event_constraints = hsw_get_event_constraints;
4916 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4917 hsw_format_attr : nhm_format_attr;
4918 extra_attr = merge_attr(extra_attr, skl_format_attr);
4919 to_free = extra_attr;
4920 x86_pmu.cpu_events = hsw_events_attrs;
4921 mem_attr = hsw_mem_events_attrs;
4922 tsx_attr = hsw_tsx_events_attrs;
4923 intel_pmu_pebs_data_source_skl(
4924 boot_cpu_data.x86_model == INTEL_FAM6_SKYLAKE_X);
4926 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
4927 x86_pmu.flags |= PMU_FL_TFA;
4928 x86_pmu.get_event_constraints = tfa_get_event_constraints;
4929 x86_pmu.enable_all = intel_tfa_pmu_enable_all;
4930 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
4931 intel_pmu_attrs[1] = &dev_attr_allow_tsx_force_abort.attr;
4934 pr_cont("Skylake events, ");
4938 case INTEL_FAM6_ICELAKE_MOBILE:
4939 x86_pmu.late_ack = true;
4940 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4941 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4942 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
4943 intel_pmu_lbr_init_skl();
4945 x86_pmu.event_constraints = intel_icl_event_constraints;
4946 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
4947 x86_pmu.extra_regs = intel_icl_extra_regs;
4948 x86_pmu.pebs_aliases = NULL;
4949 x86_pmu.pebs_prec_dist = true;
4950 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4951 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4953 x86_pmu.hw_config = hsw_hw_config;
4954 x86_pmu.get_event_constraints = icl_get_event_constraints;
4955 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4956 hsw_format_attr : nhm_format_attr;
4957 extra_attr = merge_attr(extra_attr, skl_format_attr);
4958 x86_pmu.cpu_events = get_icl_events_attrs();
4959 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xca, .umask=0x02);
4960 x86_pmu.lbr_pt_coexist = true;
4961 intel_pmu_pebs_data_source_skl(false);
4962 pr_cont("Icelake events, ");
4967 switch (x86_pmu.version) {
4969 x86_pmu.event_constraints = intel_v1_event_constraints;
4970 pr_cont("generic architected perfmon v1, ");
4971 name = "generic_arch_v1";
4975 * default constraints for v2 and up
4977 x86_pmu.event_constraints = intel_gen_event_constraints;
4978 pr_cont("generic architected perfmon, ");
4979 name = "generic_arch_v2+";
4984 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
4986 if (version >= 2 && extra_attr) {
4987 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr,
4989 WARN_ON(!x86_pmu.format_attrs);
4992 x86_pmu.cpu_events = get_events_attrs(x86_pmu.cpu_events,
4993 mem_attr, tsx_attr);
4995 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
4996 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
4997 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
4998 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
5000 x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1;
5002 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
5003 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
5004 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
5005 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
5008 x86_pmu.intel_ctrl |=
5009 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
5011 if (x86_pmu.event_constraints) {
5013 * event on fixed counter2 (REF_CYCLES) only works on this
5014 * counter, so do not extend mask to generic counters
5016 for_each_event_constraint(c, x86_pmu.event_constraints) {
5017 if (c->cmask == FIXED_EVENT_FLAGS
5018 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
5019 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
5022 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
5023 c->weight = hweight64(c->idxmsk64);
5028 * Access LBR MSR may cause #GP under certain circumstances.
5029 * E.g. KVM doesn't support LBR MSR
5030 * Check all LBT MSR here.
5031 * Disable LBR access if any LBR MSRs can not be accessed.
5033 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
5035 for (i = 0; i < x86_pmu.lbr_nr; i++) {
5036 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
5037 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
5041 x86_pmu.caps_attrs = intel_pmu_caps_attrs;
5043 if (x86_pmu.lbr_nr) {
5044 x86_pmu.caps_attrs = merge_attr(x86_pmu.caps_attrs, lbr_attrs);
5045 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
5049 * Access extra MSR may cause #GP under certain circumstances.
5050 * E.g. KVM doesn't support offcore event
5051 * Check all extra_regs here.
5053 if (x86_pmu.extra_regs) {
5054 for (er = x86_pmu.extra_regs; er->msr; er++) {
5055 er->extra_msr_access = check_msr(er->msr, 0x11UL);
5056 /* Disable LBR select mapping */
5057 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
5058 x86_pmu.lbr_sel_map = NULL;
5062 /* Support full width counters using alternative MSR range */
5063 if (x86_pmu.intel_cap.full_width_write) {
5064 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
5065 x86_pmu.perfctr = MSR_IA32_PMC0;
5066 pr_cont("full-width counters, ");
5070 * For arch perfmon 4 use counter freezing to avoid
5071 * several MSR accesses in the PMI.
5073 if (x86_pmu.counter_freezing)
5074 x86_pmu.handle_irq = intel_pmu_handle_irq_v4;
5081 * HT bug: phase 2 init
5082 * Called once we have valid topology information to check
5083 * whether or not HT is enabled
5084 * If HT is off, then we disable the workaround
5086 static __init int fixup_ht_bug(void)
5090 * problem not present on this CPU model, nothing to do
5092 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
5095 if (topology_max_smt_threads() > 1) {
5096 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
5102 hardlockup_detector_perf_stop();
5104 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
5106 x86_pmu.start_scheduling = NULL;
5107 x86_pmu.commit_scheduling = NULL;
5108 x86_pmu.stop_scheduling = NULL;
5110 hardlockup_detector_perf_restart();
5112 for_each_online_cpu(c)
5113 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
5116 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
5119 subsys_initcall(fixup_ht_bug)