2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/nospec.h>
31 #include <linux/static_call.h>
34 #include <asm/stacktrace.h>
37 #include <asm/alternative.h>
38 #include <asm/mmu_context.h>
39 #include <asm/tlbflush.h>
40 #include <asm/timer.h>
43 #include <asm/unwind.h>
45 #include "perf_event.h"
47 struct x86_pmu x86_pmu __read_mostly;
48 static struct pmu pmu;
50 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
55 DEFINE_STATIC_KEY_FALSE(rdpmc_never_available_key);
56 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
57 DEFINE_STATIC_KEY_FALSE(perf_is_hybrid);
60 * This here uses DEFINE_STATIC_CALL_NULL() to get a static_call defined
61 * from just a typename, as opposed to an actual function.
63 DEFINE_STATIC_CALL_NULL(x86_pmu_handle_irq, *x86_pmu.handle_irq);
64 DEFINE_STATIC_CALL_NULL(x86_pmu_disable_all, *x86_pmu.disable_all);
65 DEFINE_STATIC_CALL_NULL(x86_pmu_enable_all, *x86_pmu.enable_all);
66 DEFINE_STATIC_CALL_NULL(x86_pmu_enable, *x86_pmu.enable);
67 DEFINE_STATIC_CALL_NULL(x86_pmu_disable, *x86_pmu.disable);
69 DEFINE_STATIC_CALL_NULL(x86_pmu_add, *x86_pmu.add);
70 DEFINE_STATIC_CALL_NULL(x86_pmu_del, *x86_pmu.del);
71 DEFINE_STATIC_CALL_NULL(x86_pmu_read, *x86_pmu.read);
73 DEFINE_STATIC_CALL_NULL(x86_pmu_schedule_events, *x86_pmu.schedule_events);
74 DEFINE_STATIC_CALL_NULL(x86_pmu_get_event_constraints, *x86_pmu.get_event_constraints);
75 DEFINE_STATIC_CALL_NULL(x86_pmu_put_event_constraints, *x86_pmu.put_event_constraints);
77 DEFINE_STATIC_CALL_NULL(x86_pmu_start_scheduling, *x86_pmu.start_scheduling);
78 DEFINE_STATIC_CALL_NULL(x86_pmu_commit_scheduling, *x86_pmu.commit_scheduling);
79 DEFINE_STATIC_CALL_NULL(x86_pmu_stop_scheduling, *x86_pmu.stop_scheduling);
81 DEFINE_STATIC_CALL_NULL(x86_pmu_sched_task, *x86_pmu.sched_task);
82 DEFINE_STATIC_CALL_NULL(x86_pmu_swap_task_ctx, *x86_pmu.swap_task_ctx);
84 DEFINE_STATIC_CALL_NULL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs);
85 DEFINE_STATIC_CALL_NULL(x86_pmu_pebs_aliases, *x86_pmu.pebs_aliases);
88 * This one is magic, it will get called even when PMU init fails (because
89 * there is no PMU), in which case it should simply return NULL.
91 DEFINE_STATIC_CALL_RET0(x86_pmu_guest_get_msrs, *x86_pmu.guest_get_msrs);
93 u64 __read_mostly hw_cache_event_ids
94 [PERF_COUNT_HW_CACHE_MAX]
95 [PERF_COUNT_HW_CACHE_OP_MAX]
96 [PERF_COUNT_HW_CACHE_RESULT_MAX];
97 u64 __read_mostly hw_cache_extra_regs
98 [PERF_COUNT_HW_CACHE_MAX]
99 [PERF_COUNT_HW_CACHE_OP_MAX]
100 [PERF_COUNT_HW_CACHE_RESULT_MAX];
103 * Propagate event elapsed time into the generic event.
104 * Can only be executed on the CPU where the event is active.
105 * Returns the delta events processed.
107 u64 x86_perf_event_update(struct perf_event *event)
109 struct hw_perf_event *hwc = &event->hw;
110 int shift = 64 - x86_pmu.cntval_bits;
111 u64 prev_raw_count, new_raw_count;
114 if (unlikely(!hwc->event_base))
117 if (unlikely(is_topdown_count(event)) && x86_pmu.update_topdown_event)
118 return x86_pmu.update_topdown_event(event);
121 * Careful: an NMI might modify the previous event value.
123 * Our tactic to handle this is to first atomically read and
124 * exchange a new raw count - then add that new-prev delta
125 * count to the generic event atomically:
128 prev_raw_count = local64_read(&hwc->prev_count);
129 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
131 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
132 new_raw_count) != prev_raw_count)
136 * Now we have the new raw value and have updated the prev
137 * timestamp already. We can now calculate the elapsed delta
138 * (event-)time and add that to the generic event.
140 * Careful, not all hw sign-extends above the physical width
143 delta = (new_raw_count << shift) - (prev_raw_count << shift);
146 local64_add(delta, &event->count);
147 local64_sub(delta, &hwc->period_left);
149 return new_raw_count;
153 * Find and validate any extra registers to set up.
155 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
157 struct hw_perf_event_extra *reg;
158 struct extra_reg *er;
160 reg = &event->hw.extra_reg;
162 if (!x86_pmu.extra_regs)
165 for (er = x86_pmu.extra_regs; er->msr; er++) {
166 if (er->event != (config & er->config_mask))
168 if (event->attr.config1 & ~er->valid_mask)
170 /* Check if the extra msrs can be safely accessed*/
171 if (!er->extra_msr_access)
175 reg->config = event->attr.config1;
182 static atomic_t active_events;
183 static atomic_t pmc_refcount;
184 static DEFINE_MUTEX(pmc_reserve_mutex);
186 #ifdef CONFIG_X86_LOCAL_APIC
188 static inline int get_possible_num_counters(void)
190 int i, num_counters = x86_pmu.num_counters;
195 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++)
196 num_counters = max_t(int, num_counters, x86_pmu.hybrid_pmu[i].num_counters);
201 static bool reserve_pmc_hardware(void)
203 int i, num_counters = get_possible_num_counters();
205 for (i = 0; i < num_counters; i++) {
206 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
210 for (i = 0; i < num_counters; i++) {
211 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
218 for (i--; i >= 0; i--)
219 release_evntsel_nmi(x86_pmu_config_addr(i));
224 for (i--; i >= 0; i--)
225 release_perfctr_nmi(x86_pmu_event_addr(i));
230 static void release_pmc_hardware(void)
232 int i, num_counters = get_possible_num_counters();
234 for (i = 0; i < num_counters; i++) {
235 release_perfctr_nmi(x86_pmu_event_addr(i));
236 release_evntsel_nmi(x86_pmu_config_addr(i));
242 static bool reserve_pmc_hardware(void) { return true; }
243 static void release_pmc_hardware(void) {}
247 bool check_hw_exists(struct pmu *pmu, int num_counters, int num_counters_fixed)
249 u64 val, val_fail = -1, val_new= ~0;
250 int i, reg, reg_fail = -1, ret = 0;
255 * Check to see if the BIOS enabled any of the counters, if so
258 for (i = 0; i < num_counters; i++) {
259 reg = x86_pmu_config_addr(i);
260 ret = rdmsrl_safe(reg, &val);
263 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
272 if (num_counters_fixed) {
273 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
274 ret = rdmsrl_safe(reg, &val);
277 for (i = 0; i < num_counters_fixed; i++) {
278 if (fixed_counter_disabled(i, pmu))
280 if (val & (0x03 << i*4)) {
289 * If all the counters are enabled, the below test will always
290 * fail. The tools will also become useless in this scenario.
291 * Just fail and disable the hardware counters.
294 if (reg_safe == -1) {
300 * Read the current value, change it and read it back to see if it
301 * matches, this is needed to detect certain hardware emulators
302 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
304 reg = x86_pmu_event_addr(reg_safe);
305 if (rdmsrl_safe(reg, &val))
308 ret = wrmsrl_safe(reg, val);
309 ret |= rdmsrl_safe(reg, &val_new);
310 if (ret || val != val_new)
314 * We still allow the PMU driver to operate:
317 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
318 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
325 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
326 pr_cont("PMU not available due to virtualization, using software events only.\n");
328 pr_cont("Broken PMU hardware detected, using software events only.\n");
329 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
336 static void hw_perf_event_destroy(struct perf_event *event)
338 x86_release_hardware();
339 atomic_dec(&active_events);
342 void hw_perf_lbr_event_destroy(struct perf_event *event)
344 hw_perf_event_destroy(event);
346 /* undo the lbr/bts event accounting */
347 x86_del_exclusive(x86_lbr_exclusive_lbr);
350 static inline int x86_pmu_initialized(void)
352 return x86_pmu.handle_irq != NULL;
356 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
358 struct perf_event_attr *attr = &event->attr;
359 unsigned int cache_type, cache_op, cache_result;
362 config = attr->config;
364 cache_type = (config >> 0) & 0xff;
365 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
367 cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
369 cache_op = (config >> 8) & 0xff;
370 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
372 cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
374 cache_result = (config >> 16) & 0xff;
375 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
377 cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
379 val = hybrid_var(event->pmu, hw_cache_event_ids)[cache_type][cache_op][cache_result];
387 attr->config1 = hybrid_var(event->pmu, hw_cache_extra_regs)[cache_type][cache_op][cache_result];
388 return x86_pmu_extra_regs(val, event);
391 int x86_reserve_hardware(void)
395 if (!atomic_inc_not_zero(&pmc_refcount)) {
396 mutex_lock(&pmc_reserve_mutex);
397 if (atomic_read(&pmc_refcount) == 0) {
398 if (!reserve_pmc_hardware())
401 reserve_ds_buffers();
404 atomic_inc(&pmc_refcount);
405 mutex_unlock(&pmc_reserve_mutex);
411 void x86_release_hardware(void)
413 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
414 release_pmc_hardware();
415 release_ds_buffers();
416 release_lbr_buffers();
417 mutex_unlock(&pmc_reserve_mutex);
422 * Check if we can create event of a certain type (that no conflicting events
425 int x86_add_exclusive(unsigned int what)
430 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
431 * LBR and BTS are still mutually exclusive.
433 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
436 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
437 mutex_lock(&pmc_reserve_mutex);
438 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
439 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
442 atomic_inc(&x86_pmu.lbr_exclusive[what]);
443 mutex_unlock(&pmc_reserve_mutex);
447 atomic_inc(&active_events);
451 mutex_unlock(&pmc_reserve_mutex);
455 void x86_del_exclusive(unsigned int what)
457 atomic_dec(&active_events);
460 * See the comment in x86_add_exclusive().
462 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
465 atomic_dec(&x86_pmu.lbr_exclusive[what]);
468 int x86_setup_perfctr(struct perf_event *event)
470 struct perf_event_attr *attr = &event->attr;
471 struct hw_perf_event *hwc = &event->hw;
474 if (!is_sampling_event(event)) {
475 hwc->sample_period = x86_pmu.max_period;
476 hwc->last_period = hwc->sample_period;
477 local64_set(&hwc->period_left, hwc->sample_period);
480 if (attr->type == PERF_TYPE_RAW)
481 return x86_pmu_extra_regs(event->attr.config, event);
483 if (attr->type == PERF_TYPE_HW_CACHE)
484 return set_ext_hw_attr(hwc, event);
486 if (attr->config >= x86_pmu.max_events)
489 attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
494 config = x86_pmu.event_map(attr->config);
502 hwc->config |= config;
508 * check that branch_sample_type is compatible with
509 * settings needed for precise_ip > 1 which implies
510 * using the LBR to capture ALL taken branches at the
511 * priv levels of the measurement
513 static inline int precise_br_compat(struct perf_event *event)
515 u64 m = event->attr.branch_sample_type;
518 /* must capture all branches */
519 if (!(m & PERF_SAMPLE_BRANCH_ANY))
522 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
524 if (!event->attr.exclude_user)
525 b |= PERF_SAMPLE_BRANCH_USER;
527 if (!event->attr.exclude_kernel)
528 b |= PERF_SAMPLE_BRANCH_KERNEL;
531 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
537 int x86_pmu_max_precise(void)
541 /* Support for constant skid */
542 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
545 /* Support for IP fixup */
546 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
549 if (x86_pmu.pebs_prec_dist)
555 int x86_pmu_hw_config(struct perf_event *event)
557 if (event->attr.precise_ip) {
558 int precise = x86_pmu_max_precise();
560 if (event->attr.precise_ip > precise)
563 /* There's no sense in having PEBS for non sampling events: */
564 if (!is_sampling_event(event))
568 * check that PEBS LBR correction does not conflict with
569 * whatever the user is asking with attr->branch_sample_type
571 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
572 u64 *br_type = &event->attr.branch_sample_type;
574 if (has_branch_stack(event)) {
575 if (!precise_br_compat(event))
578 /* branch_sample_type is compatible */
582 * user did not specify branch_sample_type
584 * For PEBS fixups, we capture all
585 * the branches at the priv level of the
588 *br_type = PERF_SAMPLE_BRANCH_ANY;
590 if (!event->attr.exclude_user)
591 *br_type |= PERF_SAMPLE_BRANCH_USER;
593 if (!event->attr.exclude_kernel)
594 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
598 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
599 event->attach_state |= PERF_ATTACH_TASK_DATA;
603 * (keep 'enabled' bit clear for now)
605 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
608 * Count user and OS events unless requested not to
610 if (!event->attr.exclude_user)
611 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
612 if (!event->attr.exclude_kernel)
613 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
615 if (event->attr.type == PERF_TYPE_RAW)
616 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
618 if (event->attr.sample_period && x86_pmu.limit_period) {
619 if (x86_pmu.limit_period(event, event->attr.sample_period) >
620 event->attr.sample_period)
624 /* sample_regs_user never support XMM registers */
625 if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
628 * Besides the general purpose registers, XMM registers may
629 * be collected in PEBS on some platforms, e.g. Icelake
631 if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
632 if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
635 if (!event->attr.precise_ip)
639 return x86_setup_perfctr(event);
643 * Setup the hardware configuration for a given attr_type
645 static int __x86_pmu_event_init(struct perf_event *event)
649 if (!x86_pmu_initialized())
652 err = x86_reserve_hardware();
656 atomic_inc(&active_events);
657 event->destroy = hw_perf_event_destroy;
660 event->hw.last_cpu = -1;
661 event->hw.last_tag = ~0ULL;
664 event->hw.extra_reg.idx = EXTRA_REG_NONE;
665 event->hw.branch_reg.idx = EXTRA_REG_NONE;
667 return x86_pmu.hw_config(event);
670 void x86_pmu_disable_all(void)
672 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
675 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
676 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
679 if (!test_bit(idx, cpuc->active_mask))
681 rdmsrl(x86_pmu_config_addr(idx), val);
682 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
684 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
685 wrmsrl(x86_pmu_config_addr(idx), val);
686 if (is_counter_pair(hwc))
687 wrmsrl(x86_pmu_config_addr(idx + 1), 0);
691 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
693 return static_call(x86_pmu_guest_get_msrs)(nr);
695 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
698 * There may be PMI landing after enabled=0. The PMI hitting could be before or
701 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
702 * It will not be re-enabled in the NMI handler again, because enabled=0. After
703 * handling the NMI, disable_all will be called, which will not change the
704 * state either. If PMI hits after disable_all, the PMU is already disabled
705 * before entering NMI handler. The NMI handler will not change the state
708 * So either situation is harmless.
710 static void x86_pmu_disable(struct pmu *pmu)
712 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
714 if (!x86_pmu_initialized())
724 static_call(x86_pmu_disable_all)();
727 void x86_pmu_enable_all(int added)
729 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
732 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
733 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
735 if (!test_bit(idx, cpuc->active_mask))
738 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
742 static inline int is_x86_event(struct perf_event *event)
744 return event->pmu == &pmu;
747 struct pmu *x86_get_pmu(unsigned int cpu)
749 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
752 * All CPUs of the hybrid type have been offline.
753 * The x86_get_pmu() should not be invoked.
755 if (WARN_ON_ONCE(!cpuc->pmu))
761 * Event scheduler state:
763 * Assign events iterating over all events and counters, beginning
764 * with events with least weights first. Keep the current iterator
765 * state in struct sched_state.
769 int event; /* event index */
770 int counter; /* counter index */
771 int unassigned; /* number of events to be assigned left */
772 int nr_gp; /* number of GP counters used */
776 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
777 #define SCHED_STATES_MAX 2
784 struct event_constraint **constraints;
785 struct sched_state state;
786 struct sched_state saved[SCHED_STATES_MAX];
790 * Initialize interator that runs through all events and counters.
792 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
793 int num, int wmin, int wmax, int gpmax)
797 memset(sched, 0, sizeof(*sched));
798 sched->max_events = num;
799 sched->max_weight = wmax;
800 sched->max_gp = gpmax;
801 sched->constraints = constraints;
803 for (idx = 0; idx < num; idx++) {
804 if (constraints[idx]->weight == wmin)
808 sched->state.event = idx; /* start with min weight */
809 sched->state.weight = wmin;
810 sched->state.unassigned = num;
813 static void perf_sched_save_state(struct perf_sched *sched)
815 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
818 sched->saved[sched->saved_states] = sched->state;
819 sched->saved_states++;
822 static bool perf_sched_restore_state(struct perf_sched *sched)
824 if (!sched->saved_states)
827 sched->saved_states--;
828 sched->state = sched->saved[sched->saved_states];
830 /* this assignment didn't work out */
831 /* XXX broken vs EVENT_PAIR */
832 sched->state.used &= ~BIT_ULL(sched->state.counter);
834 /* try the next one */
835 sched->state.counter++;
841 * Select a counter for the current event to schedule. Return true on
844 static bool __perf_sched_find_counter(struct perf_sched *sched)
846 struct event_constraint *c;
849 if (!sched->state.unassigned)
852 if (sched->state.event >= sched->max_events)
855 c = sched->constraints[sched->state.event];
856 /* Prefer fixed purpose counters */
857 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
858 idx = INTEL_PMC_IDX_FIXED;
859 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
860 u64 mask = BIT_ULL(idx);
862 if (sched->state.used & mask)
865 sched->state.used |= mask;
870 /* Grab the first unused counter starting with idx */
871 idx = sched->state.counter;
872 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
873 u64 mask = BIT_ULL(idx);
875 if (c->flags & PERF_X86_EVENT_PAIR)
878 if (sched->state.used & mask)
881 if (sched->state.nr_gp++ >= sched->max_gp)
884 sched->state.used |= mask;
891 sched->state.counter = idx;
894 perf_sched_save_state(sched);
899 static bool perf_sched_find_counter(struct perf_sched *sched)
901 while (!__perf_sched_find_counter(sched)) {
902 if (!perf_sched_restore_state(sched))
910 * Go through all unassigned events and find the next one to schedule.
911 * Take events with the least weight first. Return true on success.
913 static bool perf_sched_next_event(struct perf_sched *sched)
915 struct event_constraint *c;
917 if (!sched->state.unassigned || !--sched->state.unassigned)
922 sched->state.event++;
923 if (sched->state.event >= sched->max_events) {
925 sched->state.event = 0;
926 sched->state.weight++;
927 if (sched->state.weight > sched->max_weight)
930 c = sched->constraints[sched->state.event];
931 } while (c->weight != sched->state.weight);
933 sched->state.counter = 0; /* start with first counter */
939 * Assign a counter for each event.
941 int perf_assign_events(struct event_constraint **constraints, int n,
942 int wmin, int wmax, int gpmax, int *assign)
944 struct perf_sched sched;
946 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
949 if (!perf_sched_find_counter(&sched))
952 assign[sched.state.event] = sched.state.counter;
953 } while (perf_sched_next_event(&sched));
955 return sched.state.unassigned;
957 EXPORT_SYMBOL_GPL(perf_assign_events);
959 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
961 int num_counters = hybrid(cpuc->pmu, num_counters);
962 struct event_constraint *c;
963 struct perf_event *e;
964 int n0, i, wmin, wmax, unsched = 0;
965 struct hw_perf_event *hwc;
969 * Compute the number of events already present; see x86_pmu_add(),
970 * validate_group() and x86_pmu_commit_txn(). For the former two
971 * cpuc->n_events hasn't been updated yet, while for the latter
972 * cpuc->n_txn contains the number of events added in the current
976 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
979 static_call_cond(x86_pmu_start_scheduling)(cpuc);
981 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
982 c = cpuc->event_constraint[i];
985 * Previously scheduled events should have a cached constraint,
986 * while new events should not have one.
988 WARN_ON_ONCE((c && i >= n0) || (!c && i < n0));
991 * Request constraints for new events; or for those events that
992 * have a dynamic constraint -- for those the constraint can
993 * change due to external factors (sibling state, allow_tfa).
995 if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) {
996 c = static_call(x86_pmu_get_event_constraints)(cpuc, i, cpuc->event_list[i]);
997 cpuc->event_constraint[i] = c;
1000 wmin = min(wmin, c->weight);
1001 wmax = max(wmax, c->weight);
1005 * fastpath, try to reuse previous register
1007 for (i = 0; i < n; i++) {
1010 hwc = &cpuc->event_list[i]->hw;
1011 c = cpuc->event_constraint[i];
1013 /* never assigned */
1017 /* constraint still honored */
1018 if (!test_bit(hwc->idx, c->idxmsk))
1021 mask = BIT_ULL(hwc->idx);
1022 if (is_counter_pair(hwc))
1025 /* not already used */
1026 if (used_mask & mask)
1032 assign[i] = hwc->idx;
1037 int gpmax = num_counters;
1040 * Do not allow scheduling of more than half the available
1043 * This helps avoid counter starvation of sibling thread by
1044 * ensuring at most half the counters cannot be in exclusive
1045 * mode. There is no designated counters for the limits. Any
1046 * N/2 counters can be used. This helps with events with
1047 * specific counter constraints.
1049 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
1050 READ_ONCE(cpuc->excl_cntrs->exclusive_present))
1054 * Reduce the amount of available counters to allow fitting
1055 * the extra Merge events needed by large increment events.
1057 if (x86_pmu.flags & PMU_FL_PAIR) {
1058 gpmax = num_counters - cpuc->n_pair;
1059 WARN_ON(gpmax <= 0);
1062 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
1063 wmax, gpmax, assign);
1067 * In case of success (unsched = 0), mark events as committed,
1068 * so we do not put_constraint() in case new events are added
1069 * and fail to be scheduled
1071 * We invoke the lower level commit callback to lock the resource
1073 * We do not need to do all of this in case we are called to
1074 * validate an event group (assign == NULL)
1076 if (!unsched && assign) {
1077 for (i = 0; i < n; i++) {
1078 e = cpuc->event_list[i];
1079 static_call_cond(x86_pmu_commit_scheduling)(cpuc, i, assign[i]);
1082 for (i = n0; i < n; i++) {
1083 e = cpuc->event_list[i];
1086 * release events that failed scheduling
1088 static_call_cond(x86_pmu_put_event_constraints)(cpuc, e);
1090 cpuc->event_constraint[i] = NULL;
1094 static_call_cond(x86_pmu_stop_scheduling)(cpuc);
1096 return unsched ? -EINVAL : 0;
1099 static int add_nr_metric_event(struct cpu_hw_events *cpuc,
1100 struct perf_event *event)
1102 if (is_metric_event(event)) {
1103 if (cpuc->n_metric == INTEL_TD_METRIC_NUM)
1106 cpuc->n_txn_metric++;
1112 static void del_nr_metric_event(struct cpu_hw_events *cpuc,
1113 struct perf_event *event)
1115 if (is_metric_event(event))
1119 static int collect_event(struct cpu_hw_events *cpuc, struct perf_event *event,
1120 int max_count, int n)
1122 union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);
1124 if (intel_cap.perf_metrics && add_nr_metric_event(cpuc, event))
1127 if (n >= max_count + cpuc->n_metric)
1130 cpuc->event_list[n] = event;
1131 if (is_counter_pair(&event->hw)) {
1140 * dogrp: true if must collect siblings events (group)
1141 * returns total number of events and error code
1143 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1145 int num_counters = hybrid(cpuc->pmu, num_counters);
1146 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1147 struct perf_event *event;
1150 max_count = num_counters + num_counters_fixed;
1152 /* current number of events already accepted */
1154 if (!cpuc->n_events)
1155 cpuc->pebs_output = 0;
1157 if (!cpuc->is_fake && leader->attr.precise_ip) {
1159 * For PEBS->PT, if !aux_event, the group leader (PT) went
1160 * away, the group was broken down and this singleton event
1161 * can't schedule any more.
1163 if (is_pebs_pt(leader) && !leader->aux_event)
1167 * pebs_output: 0: no PEBS so far, 1: PT, 2: DS
1169 if (cpuc->pebs_output &&
1170 cpuc->pebs_output != is_pebs_pt(leader) + 1)
1173 cpuc->pebs_output = is_pebs_pt(leader) + 1;
1176 if (is_x86_event(leader)) {
1177 if (collect_event(cpuc, leader, max_count, n))
1185 for_each_sibling_event(event, leader) {
1186 if (!is_x86_event(event) || event->state <= PERF_EVENT_STATE_OFF)
1189 if (collect_event(cpuc, event, max_count, n))
1197 static inline void x86_assign_hw_event(struct perf_event *event,
1198 struct cpu_hw_events *cpuc, int i)
1200 struct hw_perf_event *hwc = &event->hw;
1203 idx = hwc->idx = cpuc->assign[i];
1204 hwc->last_cpu = smp_processor_id();
1205 hwc->last_tag = ++cpuc->tags[i];
1208 case INTEL_PMC_IDX_FIXED_BTS:
1209 case INTEL_PMC_IDX_FIXED_VLBR:
1210 hwc->config_base = 0;
1211 hwc->event_base = 0;
1214 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
1215 /* All the metric events are mapped onto the fixed counter 3. */
1216 idx = INTEL_PMC_IDX_FIXED_SLOTS;
1218 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1:
1219 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1220 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 +
1221 (idx - INTEL_PMC_IDX_FIXED);
1222 hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) |
1223 INTEL_PMC_FIXED_RDPMC_BASE;
1227 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1228 hwc->event_base = x86_pmu_event_addr(hwc->idx);
1229 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1235 * x86_perf_rdpmc_index - Return PMC counter used for event
1236 * @event: the perf_event to which the PMC counter was assigned
1238 * The counter assigned to this performance event may change if interrupts
1239 * are enabled. This counter should thus never be used while interrupts are
1240 * enabled. Before this function is used to obtain the assigned counter the
1241 * event should be checked for validity using, for example,
1242 * perf_event_read_local(), within the same interrupt disabled section in
1243 * which this counter is planned to be used.
1245 * Return: The index of the performance monitoring counter assigned to
1248 int x86_perf_rdpmc_index(struct perf_event *event)
1250 lockdep_assert_irqs_disabled();
1252 return event->hw.event_base_rdpmc;
1255 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1256 struct cpu_hw_events *cpuc,
1259 return hwc->idx == cpuc->assign[i] &&
1260 hwc->last_cpu == smp_processor_id() &&
1261 hwc->last_tag == cpuc->tags[i];
1264 static void x86_pmu_start(struct perf_event *event, int flags);
1266 static void x86_pmu_enable(struct pmu *pmu)
1268 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1269 struct perf_event *event;
1270 struct hw_perf_event *hwc;
1271 int i, added = cpuc->n_added;
1273 if (!x86_pmu_initialized())
1279 if (cpuc->n_added) {
1280 int n_running = cpuc->n_events - cpuc->n_added;
1282 * apply assignment obtained either from
1283 * hw_perf_group_sched_in() or x86_pmu_enable()
1285 * step1: save events moving to new counters
1287 for (i = 0; i < n_running; i++) {
1288 event = cpuc->event_list[i];
1292 * we can avoid reprogramming counter if:
1293 * - assigned same counter as last time
1294 * - running on same CPU as last time
1295 * - no other event has used the counter since
1297 if (hwc->idx == -1 ||
1298 match_prev_assignment(hwc, cpuc, i))
1302 * Ensure we don't accidentally enable a stopped
1303 * counter simply because we rescheduled.
1305 if (hwc->state & PERF_HES_STOPPED)
1306 hwc->state |= PERF_HES_ARCH;
1308 x86_pmu_stop(event, PERF_EF_UPDATE);
1312 * step2: reprogram moved events into new counters
1314 for (i = 0; i < cpuc->n_events; i++) {
1315 event = cpuc->event_list[i];
1318 if (!match_prev_assignment(hwc, cpuc, i))
1319 x86_assign_hw_event(event, cpuc, i);
1320 else if (i < n_running)
1323 if (hwc->state & PERF_HES_ARCH)
1326 x86_pmu_start(event, PERF_EF_RELOAD);
1329 perf_events_lapic_init();
1335 static_call(x86_pmu_enable_all)(added);
1338 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1341 * Set the next IRQ period, based on the hwc->period_left value.
1342 * To be called with the event disabled in hw:
1344 int x86_perf_event_set_period(struct perf_event *event)
1346 struct hw_perf_event *hwc = &event->hw;
1347 s64 left = local64_read(&hwc->period_left);
1348 s64 period = hwc->sample_period;
1349 int ret = 0, idx = hwc->idx;
1351 if (unlikely(!hwc->event_base))
1354 if (unlikely(is_topdown_count(event)) &&
1355 x86_pmu.set_topdown_event_period)
1356 return x86_pmu.set_topdown_event_period(event);
1359 * If we are way outside a reasonable range then just skip forward:
1361 if (unlikely(left <= -period)) {
1363 local64_set(&hwc->period_left, left);
1364 hwc->last_period = period;
1368 if (unlikely(left <= 0)) {
1370 local64_set(&hwc->period_left, left);
1371 hwc->last_period = period;
1375 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1377 if (unlikely(left < 2))
1380 if (left > x86_pmu.max_period)
1381 left = x86_pmu.max_period;
1383 if (x86_pmu.limit_period)
1384 left = x86_pmu.limit_period(event, left);
1386 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1389 * The hw event starts counting from this event offset,
1390 * mark it to be able to extra future deltas:
1392 local64_set(&hwc->prev_count, (u64)-left);
1394 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1397 * Sign extend the Merge event counter's upper 16 bits since
1398 * we currently declare a 48-bit counter width
1400 if (is_counter_pair(hwc))
1401 wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff);
1404 * Due to erratum on certan cpu we need
1405 * a second write to be sure the register
1406 * is updated properly
1408 if (x86_pmu.perfctr_second_write) {
1409 wrmsrl(hwc->event_base,
1410 (u64)(-left) & x86_pmu.cntval_mask);
1413 perf_event_update_userpage(event);
1418 void x86_pmu_enable_event(struct perf_event *event)
1420 if (__this_cpu_read(cpu_hw_events.enabled))
1421 __x86_pmu_enable_event(&event->hw,
1422 ARCH_PERFMON_EVENTSEL_ENABLE);
1426 * Add a single event to the PMU.
1428 * The event is added to the group of enabled events
1429 * but only if it can be scheduled with existing events.
1431 static int x86_pmu_add(struct perf_event *event, int flags)
1433 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1434 struct hw_perf_event *hwc;
1435 int assign[X86_PMC_IDX_MAX];
1440 n0 = cpuc->n_events;
1441 ret = n = collect_events(cpuc, event, false);
1445 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1446 if (!(flags & PERF_EF_START))
1447 hwc->state |= PERF_HES_ARCH;
1450 * If group events scheduling transaction was started,
1451 * skip the schedulability test here, it will be performed
1452 * at commit time (->commit_txn) as a whole.
1454 * If commit fails, we'll call ->del() on all events
1455 * for which ->add() was called.
1457 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1460 ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
1464 * copy new assignment, now we know it is possible
1465 * will be used by hw_perf_enable()
1467 memcpy(cpuc->assign, assign, n*sizeof(int));
1471 * Commit the collect_events() state. See x86_pmu_del() and
1475 cpuc->n_added += n - n0;
1476 cpuc->n_txn += n - n0;
1479 * This is before x86_pmu_enable() will call x86_pmu_start(),
1480 * so we enable LBRs before an event needs them etc..
1482 static_call_cond(x86_pmu_add)(event);
1489 static void x86_pmu_start(struct perf_event *event, int flags)
1491 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1492 int idx = event->hw.idx;
1494 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1497 if (WARN_ON_ONCE(idx == -1))
1500 if (flags & PERF_EF_RELOAD) {
1501 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1502 x86_perf_event_set_period(event);
1505 event->hw.state = 0;
1507 cpuc->events[idx] = event;
1508 __set_bit(idx, cpuc->active_mask);
1509 static_call(x86_pmu_enable)(event);
1510 perf_event_update_userpage(event);
1513 void perf_event_print_debug(void)
1515 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1517 int cpu = smp_processor_id();
1518 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1519 int num_counters = hybrid(cpuc->pmu, num_counters);
1520 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1521 struct event_constraint *pebs_constraints = hybrid(cpuc->pmu, pebs_constraints);
1522 unsigned long flags;
1528 local_irq_save(flags);
1530 if (x86_pmu.version >= 2) {
1531 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1532 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1533 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1534 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1537 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1538 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1539 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1540 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1541 if (pebs_constraints) {
1542 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1543 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1545 if (x86_pmu.lbr_nr) {
1546 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1547 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1550 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1552 for (idx = 0; idx < num_counters; idx++) {
1553 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1554 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1556 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1558 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1559 cpu, idx, pmc_ctrl);
1560 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1561 cpu, idx, pmc_count);
1562 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1563 cpu, idx, prev_left);
1565 for (idx = 0; idx < num_counters_fixed; idx++) {
1566 if (fixed_counter_disabled(idx, cpuc->pmu))
1568 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1570 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1571 cpu, idx, pmc_count);
1573 local_irq_restore(flags);
1576 void x86_pmu_stop(struct perf_event *event, int flags)
1578 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1579 struct hw_perf_event *hwc = &event->hw;
1581 if (test_bit(hwc->idx, cpuc->active_mask)) {
1582 static_call(x86_pmu_disable)(event);
1583 __clear_bit(hwc->idx, cpuc->active_mask);
1584 cpuc->events[hwc->idx] = NULL;
1585 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1586 hwc->state |= PERF_HES_STOPPED;
1589 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1591 * Drain the remaining delta count out of a event
1592 * that we are disabling:
1594 x86_perf_event_update(event);
1595 hwc->state |= PERF_HES_UPTODATE;
1599 static void x86_pmu_del(struct perf_event *event, int flags)
1601 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1602 union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);
1606 * If we're called during a txn, we only need to undo x86_pmu.add.
1607 * The events never got scheduled and ->cancel_txn will truncate
1610 * XXX assumes any ->del() called during a TXN will only be on
1611 * an event added during that same TXN.
1613 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1617 * Not a TXN, therefore cleanup properly.
1619 x86_pmu_stop(event, PERF_EF_UPDATE);
1621 for (i = 0; i < cpuc->n_events; i++) {
1622 if (event == cpuc->event_list[i])
1626 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1629 /* If we have a newly added event; make sure to decrease n_added. */
1630 if (i >= cpuc->n_events - cpuc->n_added)
1633 static_call_cond(x86_pmu_put_event_constraints)(cpuc, event);
1635 /* Delete the array entry. */
1636 while (++i < cpuc->n_events) {
1637 cpuc->event_list[i-1] = cpuc->event_list[i];
1638 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1640 cpuc->event_constraint[i-1] = NULL;
1642 if (intel_cap.perf_metrics)
1643 del_nr_metric_event(cpuc, event);
1645 perf_event_update_userpage(event);
1650 * This is after x86_pmu_stop(); so we disable LBRs after any
1651 * event can need them etc..
1653 static_call_cond(x86_pmu_del)(event);
1656 int x86_pmu_handle_irq(struct pt_regs *regs)
1658 struct perf_sample_data data;
1659 struct cpu_hw_events *cpuc;
1660 struct perf_event *event;
1661 int idx, handled = 0;
1664 cpuc = this_cpu_ptr(&cpu_hw_events);
1667 * Some chipsets need to unmask the LVTPC in a particular spot
1668 * inside the nmi handler. As a result, the unmasking was pushed
1669 * into all the nmi handlers.
1671 * This generic handler doesn't seem to have any issues where the
1672 * unmasking occurs so it was left at the top.
1674 apic_write(APIC_LVTPC, APIC_DM_NMI);
1676 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1677 if (!test_bit(idx, cpuc->active_mask))
1680 event = cpuc->events[idx];
1682 val = x86_perf_event_update(event);
1683 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1690 perf_sample_data_init(&data, 0, event->hw.last_period);
1692 if (!x86_perf_event_set_period(event))
1695 if (perf_event_overflow(event, &data, regs))
1696 x86_pmu_stop(event, 0);
1700 inc_irq_stat(apic_perf_irqs);
1705 void perf_events_lapic_init(void)
1707 if (!x86_pmu.apic || !x86_pmu_initialized())
1711 * Always use NMI for PMU
1713 apic_write(APIC_LVTPC, APIC_DM_NMI);
1717 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1724 * All PMUs/events that share this PMI handler should make sure to
1725 * increment active_events for their events.
1727 if (!atomic_read(&active_events))
1730 start_clock = sched_clock();
1731 ret = static_call(x86_pmu_handle_irq)(regs);
1732 finish_clock = sched_clock();
1734 perf_sample_event_took(finish_clock - start_clock);
1738 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1740 struct event_constraint emptyconstraint;
1741 struct event_constraint unconstrained;
1743 static int x86_pmu_prepare_cpu(unsigned int cpu)
1745 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1748 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1749 cpuc->kfree_on_online[i] = NULL;
1750 if (x86_pmu.cpu_prepare)
1751 return x86_pmu.cpu_prepare(cpu);
1755 static int x86_pmu_dead_cpu(unsigned int cpu)
1757 if (x86_pmu.cpu_dead)
1758 x86_pmu.cpu_dead(cpu);
1762 static int x86_pmu_online_cpu(unsigned int cpu)
1764 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1767 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1768 kfree(cpuc->kfree_on_online[i]);
1769 cpuc->kfree_on_online[i] = NULL;
1774 static int x86_pmu_starting_cpu(unsigned int cpu)
1776 if (x86_pmu.cpu_starting)
1777 x86_pmu.cpu_starting(cpu);
1781 static int x86_pmu_dying_cpu(unsigned int cpu)
1783 if (x86_pmu.cpu_dying)
1784 x86_pmu.cpu_dying(cpu);
1788 static void __init pmu_check_apic(void)
1790 if (boot_cpu_has(X86_FEATURE_APIC))
1794 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1795 pr_info("no hardware sampling interrupt available.\n");
1798 * If we have a PMU initialized but no APIC
1799 * interrupts, we cannot sample hardware
1800 * events (user-space has to fall back and
1801 * sample via a hrtimer based software event):
1803 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1807 static struct attribute_group x86_pmu_format_group __ro_after_init = {
1812 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1814 struct perf_pmu_events_attr *pmu_attr =
1815 container_of(attr, struct perf_pmu_events_attr, attr);
1818 if (pmu_attr->id < x86_pmu.max_events)
1819 config = x86_pmu.event_map(pmu_attr->id);
1821 /* string trumps id */
1822 if (pmu_attr->event_str)
1823 return sprintf(page, "%s", pmu_attr->event_str);
1825 return x86_pmu.events_sysfs_show(page, config);
1827 EXPORT_SYMBOL_GPL(events_sysfs_show);
1829 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1832 struct perf_pmu_events_ht_attr *pmu_attr =
1833 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1836 * Report conditional events depending on Hyper-Threading.
1838 * This is overly conservative as usually the HT special
1839 * handling is not needed if the other CPU thread is idle.
1841 * Note this does not (and cannot) handle the case when thread
1842 * siblings are invisible, for example with virtualization
1843 * if they are owned by some other guest. The user tool
1844 * has to re-read when a thread sibling gets onlined later.
1846 return sprintf(page, "%s",
1847 topology_max_smt_threads() > 1 ?
1848 pmu_attr->event_str_ht :
1849 pmu_attr->event_str_noht);
1852 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1853 EVENT_ATTR(instructions, INSTRUCTIONS );
1854 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1855 EVENT_ATTR(cache-misses, CACHE_MISSES );
1856 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1857 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1858 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1859 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1860 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1861 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1863 static struct attribute *empty_attrs;
1865 static struct attribute *events_attr[] = {
1866 EVENT_PTR(CPU_CYCLES),
1867 EVENT_PTR(INSTRUCTIONS),
1868 EVENT_PTR(CACHE_REFERENCES),
1869 EVENT_PTR(CACHE_MISSES),
1870 EVENT_PTR(BRANCH_INSTRUCTIONS),
1871 EVENT_PTR(BRANCH_MISSES),
1872 EVENT_PTR(BUS_CYCLES),
1873 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1874 EVENT_PTR(STALLED_CYCLES_BACKEND),
1875 EVENT_PTR(REF_CPU_CYCLES),
1880 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1881 * out of events_attr attributes.
1884 is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1886 struct perf_pmu_events_attr *pmu_attr;
1888 if (idx >= x86_pmu.max_events)
1891 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
1893 return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0;
1896 static struct attribute_group x86_pmu_events_group __ro_after_init = {
1898 .attrs = events_attr,
1899 .is_visible = is_visible,
1902 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1904 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1905 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1906 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1907 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1908 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1909 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1913 * We have whole page size to spend and just little data
1914 * to write, so we can safely use sprintf.
1916 ret = sprintf(page, "event=0x%02llx", event);
1919 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1922 ret += sprintf(page + ret, ",edge");
1925 ret += sprintf(page + ret, ",pc");
1928 ret += sprintf(page + ret, ",any");
1931 ret += sprintf(page + ret, ",inv");
1934 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1936 ret += sprintf(page + ret, "\n");
1941 static struct attribute_group x86_pmu_attr_group;
1942 static struct attribute_group x86_pmu_caps_group;
1944 static void x86_pmu_static_call_update(void)
1946 static_call_update(x86_pmu_handle_irq, x86_pmu.handle_irq);
1947 static_call_update(x86_pmu_disable_all, x86_pmu.disable_all);
1948 static_call_update(x86_pmu_enable_all, x86_pmu.enable_all);
1949 static_call_update(x86_pmu_enable, x86_pmu.enable);
1950 static_call_update(x86_pmu_disable, x86_pmu.disable);
1952 static_call_update(x86_pmu_add, x86_pmu.add);
1953 static_call_update(x86_pmu_del, x86_pmu.del);
1954 static_call_update(x86_pmu_read, x86_pmu.read);
1956 static_call_update(x86_pmu_schedule_events, x86_pmu.schedule_events);
1957 static_call_update(x86_pmu_get_event_constraints, x86_pmu.get_event_constraints);
1958 static_call_update(x86_pmu_put_event_constraints, x86_pmu.put_event_constraints);
1960 static_call_update(x86_pmu_start_scheduling, x86_pmu.start_scheduling);
1961 static_call_update(x86_pmu_commit_scheduling, x86_pmu.commit_scheduling);
1962 static_call_update(x86_pmu_stop_scheduling, x86_pmu.stop_scheduling);
1964 static_call_update(x86_pmu_sched_task, x86_pmu.sched_task);
1965 static_call_update(x86_pmu_swap_task_ctx, x86_pmu.swap_task_ctx);
1967 static_call_update(x86_pmu_drain_pebs, x86_pmu.drain_pebs);
1968 static_call_update(x86_pmu_pebs_aliases, x86_pmu.pebs_aliases);
1970 static_call_update(x86_pmu_guest_get_msrs, x86_pmu.guest_get_msrs);
1973 static void _x86_pmu_read(struct perf_event *event)
1975 x86_perf_event_update(event);
1978 static int __init init_hw_perf_events(void)
1980 struct x86_pmu_quirk *quirk;
1983 pr_info("Performance Events: ");
1985 switch (boot_cpu_data.x86_vendor) {
1986 case X86_VENDOR_INTEL:
1987 err = intel_pmu_init();
1989 case X86_VENDOR_AMD:
1990 err = amd_pmu_init();
1992 case X86_VENDOR_HYGON:
1993 err = amd_pmu_init();
1994 x86_pmu.name = "HYGON";
1996 case X86_VENDOR_ZHAOXIN:
1997 case X86_VENDOR_CENTAUR:
1998 err = zhaoxin_pmu_init();
2004 pr_cont("no PMU driver, software events only.\n");
2010 /* sanity check that the hardware exists or is emulated */
2011 if (!check_hw_exists(&pmu, x86_pmu.num_counters, x86_pmu.num_counters_fixed))
2014 pr_cont("%s PMU driver.\n", x86_pmu.name);
2016 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
2018 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
2021 if (!x86_pmu.intel_ctrl)
2022 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2024 perf_events_lapic_init();
2025 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
2027 unconstrained = (struct event_constraint)
2028 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
2029 0, x86_pmu.num_counters, 0, 0);
2031 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
2033 if (!x86_pmu.events_sysfs_show)
2034 x86_pmu_events_group.attrs = &empty_attrs;
2036 pmu.attr_update = x86_pmu.attr_update;
2038 pr_info("... version: %d\n", x86_pmu.version);
2039 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
2040 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
2041 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
2042 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
2043 pr_info("... fixed-purpose events: %lu\n",
2044 hweight64((((1ULL << x86_pmu.num_counters_fixed) - 1)
2045 << INTEL_PMC_IDX_FIXED) & x86_pmu.intel_ctrl));
2046 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
2049 x86_pmu.read = _x86_pmu_read;
2051 if (!x86_pmu.guest_get_msrs)
2052 x86_pmu.guest_get_msrs = (void *)&__static_call_return0;
2054 x86_pmu_static_call_update();
2057 * Install callbacks. Core will call them for each online
2060 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare",
2061 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
2065 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
2066 "perf/x86:starting", x86_pmu_starting_cpu,
2071 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online",
2072 x86_pmu_online_cpu, NULL);
2076 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
2083 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
2085 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
2087 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
2090 early_initcall(init_hw_perf_events);
2092 static void x86_pmu_read(struct perf_event *event)
2094 static_call(x86_pmu_read)(event);
2098 * Start group events scheduling transaction
2099 * Set the flag to make pmu::enable() not perform the
2100 * schedulability test, it will be performed at commit time
2102 * We only support PERF_PMU_TXN_ADD transactions. Save the
2103 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
2106 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
2108 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2110 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */
2112 cpuc->txn_flags = txn_flags;
2113 if (txn_flags & ~PERF_PMU_TXN_ADD)
2116 perf_pmu_disable(pmu);
2117 __this_cpu_write(cpu_hw_events.n_txn, 0);
2118 __this_cpu_write(cpu_hw_events.n_txn_pair, 0);
2119 __this_cpu_write(cpu_hw_events.n_txn_metric, 0);
2123 * Stop group events scheduling transaction
2124 * Clear the flag and pmu::enable() will perform the
2125 * schedulability test.
2127 static void x86_pmu_cancel_txn(struct pmu *pmu)
2129 unsigned int txn_flags;
2130 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2132 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2134 txn_flags = cpuc->txn_flags;
2135 cpuc->txn_flags = 0;
2136 if (txn_flags & ~PERF_PMU_TXN_ADD)
2140 * Truncate collected array by the number of events added in this
2141 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
2143 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
2144 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
2145 __this_cpu_sub(cpu_hw_events.n_pair, __this_cpu_read(cpu_hw_events.n_txn_pair));
2146 __this_cpu_sub(cpu_hw_events.n_metric, __this_cpu_read(cpu_hw_events.n_txn_metric));
2147 perf_pmu_enable(pmu);
2151 * Commit group events scheduling transaction
2152 * Perform the group schedulability test as a whole
2153 * Return 0 if success
2155 * Does not cancel the transaction on failure; expects the caller to do this.
2157 static int x86_pmu_commit_txn(struct pmu *pmu)
2159 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2160 int assign[X86_PMC_IDX_MAX];
2163 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2165 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
2166 cpuc->txn_flags = 0;
2172 if (!x86_pmu_initialized())
2175 ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
2180 * copy new assignment, now we know it is possible
2181 * will be used by hw_perf_enable()
2183 memcpy(cpuc->assign, assign, n*sizeof(int));
2185 cpuc->txn_flags = 0;
2186 perf_pmu_enable(pmu);
2190 * a fake_cpuc is used to validate event groups. Due to
2191 * the extra reg logic, we need to also allocate a fake
2192 * per_core and per_cpu structure. Otherwise, group events
2193 * using extra reg may conflict without the kernel being
2194 * able to catch this when the last event gets added to
2197 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
2199 intel_cpuc_finish(cpuc);
2203 static struct cpu_hw_events *allocate_fake_cpuc(void)
2205 struct cpu_hw_events *cpuc;
2206 int cpu = raw_smp_processor_id();
2208 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
2210 return ERR_PTR(-ENOMEM);
2213 if (intel_cpuc_prepare(cpuc, cpu))
2218 free_fake_cpuc(cpuc);
2219 return ERR_PTR(-ENOMEM);
2223 * validate that we can schedule this event
2225 static int validate_event(struct perf_event *event)
2227 struct cpu_hw_events *fake_cpuc;
2228 struct event_constraint *c;
2231 fake_cpuc = allocate_fake_cpuc();
2232 if (IS_ERR(fake_cpuc))
2233 return PTR_ERR(fake_cpuc);
2235 c = x86_pmu.get_event_constraints(fake_cpuc, 0, event);
2237 if (!c || !c->weight)
2240 if (x86_pmu.put_event_constraints)
2241 x86_pmu.put_event_constraints(fake_cpuc, event);
2243 free_fake_cpuc(fake_cpuc);
2249 * validate a single event group
2251 * validation include:
2252 * - check events are compatible which each other
2253 * - events do not compete for the same counter
2254 * - number of events <= number of counters
2256 * validation ensures the group can be loaded onto the
2257 * PMU if it was the only group available.
2259 static int validate_group(struct perf_event *event)
2261 struct perf_event *leader = event->group_leader;
2262 struct cpu_hw_events *fake_cpuc;
2263 int ret = -EINVAL, n;
2265 fake_cpuc = allocate_fake_cpuc();
2266 if (IS_ERR(fake_cpuc))
2267 return PTR_ERR(fake_cpuc);
2269 * the event is not yet connected with its
2270 * siblings therefore we must first collect
2271 * existing siblings, then add the new event
2272 * before we can simulate the scheduling
2274 n = collect_events(fake_cpuc, leader, true);
2278 fake_cpuc->n_events = n;
2279 n = collect_events(fake_cpuc, event, false);
2283 fake_cpuc->n_events = 0;
2284 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2287 free_fake_cpuc(fake_cpuc);
2291 static int x86_pmu_event_init(struct perf_event *event)
2296 switch (event->attr.type) {
2298 case PERF_TYPE_HARDWARE:
2299 case PERF_TYPE_HW_CACHE:
2306 err = __x86_pmu_event_init(event);
2309 * we temporarily connect event to its pmu
2310 * such that validate_group() can classify
2311 * it as an x86 event using is_x86_event()
2316 if (event->group_leader != event)
2317 err = validate_group(event);
2319 err = validate_event(event);
2325 event->destroy(event);
2328 if (READ_ONCE(x86_pmu.attr_rdpmc) &&
2329 !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
2330 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
2335 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
2337 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2341 * This function relies on not being called concurrently in two
2342 * tasks in the same mm. Otherwise one task could observe
2343 * perf_rdpmc_allowed > 1 and return all the way back to
2344 * userspace with CR4.PCE clear while another task is still
2345 * doing on_each_cpu_mask() to propagate CR4.PCE.
2347 * For now, this can't happen because all callers hold mmap_lock
2348 * for write. If this changes, we'll need a different solution.
2350 mmap_assert_write_locked(mm);
2352 if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1)
2353 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2356 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
2359 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2362 if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed))
2363 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2366 static int x86_pmu_event_idx(struct perf_event *event)
2368 struct hw_perf_event *hwc = &event->hw;
2370 if (!(hwc->flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2373 if (is_metric_idx(hwc->idx))
2374 return INTEL_PMC_FIXED_RDPMC_METRICS + 1;
2376 return hwc->event_base_rdpmc + 1;
2379 static ssize_t get_attr_rdpmc(struct device *cdev,
2380 struct device_attribute *attr,
2383 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2386 static ssize_t set_attr_rdpmc(struct device *cdev,
2387 struct device_attribute *attr,
2388 const char *buf, size_t count)
2393 ret = kstrtoul(buf, 0, &val);
2400 if (x86_pmu.attr_rdpmc_broken)
2403 if (val != x86_pmu.attr_rdpmc) {
2405 * Changing into or out of never available or always available,
2406 * aka perf-event-bypassing mode. This path is extremely slow,
2407 * but only root can trigger it, so it's okay.
2410 static_branch_inc(&rdpmc_never_available_key);
2411 else if (x86_pmu.attr_rdpmc == 0)
2412 static_branch_dec(&rdpmc_never_available_key);
2415 static_branch_inc(&rdpmc_always_available_key);
2416 else if (x86_pmu.attr_rdpmc == 2)
2417 static_branch_dec(&rdpmc_always_available_key);
2419 on_each_cpu(cr4_update_pce, NULL, 1);
2420 x86_pmu.attr_rdpmc = val;
2426 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2428 static struct attribute *x86_pmu_attrs[] = {
2429 &dev_attr_rdpmc.attr,
2433 static struct attribute_group x86_pmu_attr_group __ro_after_init = {
2434 .attrs = x86_pmu_attrs,
2437 static ssize_t max_precise_show(struct device *cdev,
2438 struct device_attribute *attr,
2441 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
2444 static DEVICE_ATTR_RO(max_precise);
2446 static struct attribute *x86_pmu_caps_attrs[] = {
2447 &dev_attr_max_precise.attr,
2451 static struct attribute_group x86_pmu_caps_group __ro_after_init = {
2453 .attrs = x86_pmu_caps_attrs,
2456 static const struct attribute_group *x86_pmu_attr_groups[] = {
2457 &x86_pmu_attr_group,
2458 &x86_pmu_format_group,
2459 &x86_pmu_events_group,
2460 &x86_pmu_caps_group,
2464 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2466 static_call_cond(x86_pmu_sched_task)(ctx, sched_in);
2469 static void x86_pmu_swap_task_ctx(struct perf_event_context *prev,
2470 struct perf_event_context *next)
2472 static_call_cond(x86_pmu_swap_task_ctx)(prev, next);
2475 void perf_check_microcode(void)
2477 if (x86_pmu.check_microcode)
2478 x86_pmu.check_microcode();
2481 static int x86_pmu_check_period(struct perf_event *event, u64 value)
2483 if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2486 if (value && x86_pmu.limit_period) {
2487 if (x86_pmu.limit_period(event, value) > value)
2494 static int x86_pmu_aux_output_match(struct perf_event *event)
2496 if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT))
2499 if (x86_pmu.aux_output_match)
2500 return x86_pmu.aux_output_match(event);
2505 static struct pmu pmu = {
2506 .pmu_enable = x86_pmu_enable,
2507 .pmu_disable = x86_pmu_disable,
2509 .attr_groups = x86_pmu_attr_groups,
2511 .event_init = x86_pmu_event_init,
2513 .event_mapped = x86_pmu_event_mapped,
2514 .event_unmapped = x86_pmu_event_unmapped,
2518 .start = x86_pmu_start,
2519 .stop = x86_pmu_stop,
2520 .read = x86_pmu_read,
2522 .start_txn = x86_pmu_start_txn,
2523 .cancel_txn = x86_pmu_cancel_txn,
2524 .commit_txn = x86_pmu_commit_txn,
2526 .event_idx = x86_pmu_event_idx,
2527 .sched_task = x86_pmu_sched_task,
2528 .swap_task_ctx = x86_pmu_swap_task_ctx,
2529 .check_period = x86_pmu_check_period,
2531 .aux_output_match = x86_pmu_aux_output_match,
2534 void arch_perf_update_userpage(struct perf_event *event,
2535 struct perf_event_mmap_page *userpg, u64 now)
2537 struct cyc2ns_data data;
2540 userpg->cap_user_time = 0;
2541 userpg->cap_user_time_zero = 0;
2542 userpg->cap_user_rdpmc =
2543 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2544 userpg->pmc_width = x86_pmu.cntval_bits;
2546 if (!using_native_sched_clock() || !sched_clock_stable())
2549 cyc2ns_read_begin(&data);
2551 offset = data.cyc2ns_offset + __sched_clock_offset;
2554 * Internal timekeeping for enabled/running/stopped times
2555 * is always in the local_clock domain.
2557 userpg->cap_user_time = 1;
2558 userpg->time_mult = data.cyc2ns_mul;
2559 userpg->time_shift = data.cyc2ns_shift;
2560 userpg->time_offset = offset - now;
2563 * cap_user_time_zero doesn't make sense when we're using a different
2564 * time base for the records.
2566 if (!event->attr.use_clockid) {
2567 userpg->cap_user_time_zero = 1;
2568 userpg->time_zero = offset;
2575 * Determine whether the regs were taken from an irq/exception handler rather
2576 * than from perf_arch_fetch_caller_regs().
2578 static bool perf_hw_regs(struct pt_regs *regs)
2580 return regs->flags & X86_EFLAGS_FIXED;
2584 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2586 struct unwind_state state;
2589 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2590 /* TODO: We don't support guest os callchain now */
2594 if (perf_callchain_store(entry, regs->ip))
2597 if (perf_hw_regs(regs))
2598 unwind_start(&state, current, regs, NULL);
2600 unwind_start(&state, current, NULL, (void *)regs->sp);
2602 for (; !unwind_done(&state); unwind_next_frame(&state)) {
2603 addr = unwind_get_return_address(&state);
2604 if (!addr || perf_callchain_store(entry, addr))
2610 valid_user_frame(const void __user *fp, unsigned long size)
2612 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2615 static unsigned long get_segment_base(unsigned int segment)
2617 struct desc_struct *desc;
2618 unsigned int idx = segment >> 3;
2620 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2621 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2622 struct ldt_struct *ldt;
2624 /* IRQs are off, so this synchronizes with smp_store_release */
2625 ldt = READ_ONCE(current->active_mm->context.ldt);
2626 if (!ldt || idx >= ldt->nr_entries)
2629 desc = &ldt->entries[idx];
2634 if (idx >= GDT_ENTRIES)
2637 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2640 return get_desc_base(desc);
2643 #ifdef CONFIG_IA32_EMULATION
2645 #include <linux/compat.h>
2648 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2650 /* 32-bit process in 64-bit kernel. */
2651 unsigned long ss_base, cs_base;
2652 struct stack_frame_ia32 frame;
2653 const struct stack_frame_ia32 __user *fp;
2655 if (user_64bit_mode(regs))
2658 cs_base = get_segment_base(regs->cs);
2659 ss_base = get_segment_base(regs->ss);
2661 fp = compat_ptr(ss_base + regs->bp);
2662 pagefault_disable();
2663 while (entry->nr < entry->max_stack) {
2664 if (!valid_user_frame(fp, sizeof(frame)))
2667 if (__get_user(frame.next_frame, &fp->next_frame))
2669 if (__get_user(frame.return_address, &fp->return_address))
2672 perf_callchain_store(entry, cs_base + frame.return_address);
2673 fp = compat_ptr(ss_base + frame.next_frame);
2680 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2687 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2689 struct stack_frame frame;
2690 const struct stack_frame __user *fp;
2692 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2693 /* TODO: We don't support guest os callchain now */
2698 * We don't know what to do with VM86 stacks.. ignore them for now.
2700 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2703 fp = (void __user *)regs->bp;
2705 perf_callchain_store(entry, regs->ip);
2707 if (!nmi_uaccess_okay())
2710 if (perf_callchain_user32(regs, entry))
2713 pagefault_disable();
2714 while (entry->nr < entry->max_stack) {
2715 if (!valid_user_frame(fp, sizeof(frame)))
2718 if (__get_user(frame.next_frame, &fp->next_frame))
2720 if (__get_user(frame.return_address, &fp->return_address))
2723 perf_callchain_store(entry, frame.return_address);
2724 fp = (void __user *)frame.next_frame;
2730 * Deal with code segment offsets for the various execution modes:
2732 * VM86 - the good olde 16 bit days, where the linear address is
2733 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2735 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2736 * to figure out what the 32bit base address is.
2738 * X32 - has TIF_X32 set, but is running in x86_64
2740 * X86_64 - CS,DS,SS,ES are all zero based.
2742 static unsigned long code_segment_base(struct pt_regs *regs)
2745 * For IA32 we look at the GDT/LDT segment base to convert the
2746 * effective IP to a linear address.
2749 #ifdef CONFIG_X86_32
2751 * If we are in VM86 mode, add the segment offset to convert to a
2754 if (regs->flags & X86_VM_MASK)
2755 return 0x10 * regs->cs;
2757 if (user_mode(regs) && regs->cs != __USER_CS)
2758 return get_segment_base(regs->cs);
2760 if (user_mode(regs) && !user_64bit_mode(regs) &&
2761 regs->cs != __USER32_CS)
2762 return get_segment_base(regs->cs);
2767 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2769 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2770 return perf_guest_cbs->get_guest_ip();
2772 return regs->ip + code_segment_base(regs);
2775 unsigned long perf_misc_flags(struct pt_regs *regs)
2779 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2780 if (perf_guest_cbs->is_user_mode())
2781 misc |= PERF_RECORD_MISC_GUEST_USER;
2783 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2785 if (user_mode(regs))
2786 misc |= PERF_RECORD_MISC_USER;
2788 misc |= PERF_RECORD_MISC_KERNEL;
2791 if (regs->flags & PERF_EFLAGS_EXACT)
2792 misc |= PERF_RECORD_MISC_EXACT_IP;
2797 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2799 cap->version = x86_pmu.version;
2801 * KVM doesn't support the hybrid PMU yet.
2802 * Return the common value in global x86_pmu,
2803 * which available for all cores.
2805 cap->num_counters_gp = x86_pmu.num_counters;
2806 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2807 cap->bit_width_gp = x86_pmu.cntval_bits;
2808 cap->bit_width_fixed = x86_pmu.cntval_bits;
2809 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2810 cap->events_mask_len = x86_pmu.events_mask_len;
2812 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);