2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/nospec.h>
33 #include <asm/stacktrace.h>
36 #include <asm/alternative.h>
37 #include <asm/mmu_context.h>
38 #include <asm/tlbflush.h>
39 #include <asm/timer.h>
42 #include <asm/unwind.h>
44 #include "perf_event.h"
46 struct x86_pmu x86_pmu __read_mostly;
48 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
52 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
54 u64 __read_mostly hw_cache_event_ids
55 [PERF_COUNT_HW_CACHE_MAX]
56 [PERF_COUNT_HW_CACHE_OP_MAX]
57 [PERF_COUNT_HW_CACHE_RESULT_MAX];
58 u64 __read_mostly hw_cache_extra_regs
59 [PERF_COUNT_HW_CACHE_MAX]
60 [PERF_COUNT_HW_CACHE_OP_MAX]
61 [PERF_COUNT_HW_CACHE_RESULT_MAX];
64 * Propagate event elapsed time into the generic event.
65 * Can only be executed on the CPU where the event is active.
66 * Returns the delta events processed.
68 u64 x86_perf_event_update(struct perf_event *event)
70 struct hw_perf_event *hwc = &event->hw;
71 int shift = 64 - x86_pmu.cntval_bits;
72 u64 prev_raw_count, new_raw_count;
76 if (idx == INTEL_PMC_IDX_FIXED_BTS)
80 * Careful: an NMI might modify the previous event value.
82 * Our tactic to handle this is to first atomically read and
83 * exchange a new raw count - then add that new-prev delta
84 * count to the generic event atomically:
87 prev_raw_count = local64_read(&hwc->prev_count);
88 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
90 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
91 new_raw_count) != prev_raw_count)
95 * Now we have the new raw value and have updated the prev
96 * timestamp already. We can now calculate the elapsed delta
97 * (event-)time and add that to the generic event.
99 * Careful, not all hw sign-extends above the physical width
102 delta = (new_raw_count << shift) - (prev_raw_count << shift);
105 local64_add(delta, &event->count);
106 local64_sub(delta, &hwc->period_left);
108 return new_raw_count;
112 * Find and validate any extra registers to set up.
114 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
116 struct hw_perf_event_extra *reg;
117 struct extra_reg *er;
119 reg = &event->hw.extra_reg;
121 if (!x86_pmu.extra_regs)
124 for (er = x86_pmu.extra_regs; er->msr; er++) {
125 if (er->event != (config & er->config_mask))
127 if (event->attr.config1 & ~er->valid_mask)
129 /* Check if the extra msrs can be safely accessed*/
130 if (!er->extra_msr_access)
134 reg->config = event->attr.config1;
141 static atomic_t active_events;
142 static atomic_t pmc_refcount;
143 static DEFINE_MUTEX(pmc_reserve_mutex);
145 #ifdef CONFIG_X86_LOCAL_APIC
147 static bool reserve_pmc_hardware(void)
151 for (i = 0; i < x86_pmu.num_counters; i++) {
152 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
156 for (i = 0; i < x86_pmu.num_counters; i++) {
157 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
164 for (i--; i >= 0; i--)
165 release_evntsel_nmi(x86_pmu_config_addr(i));
167 i = x86_pmu.num_counters;
170 for (i--; i >= 0; i--)
171 release_perfctr_nmi(x86_pmu_event_addr(i));
176 static void release_pmc_hardware(void)
180 for (i = 0; i < x86_pmu.num_counters; i++) {
181 release_perfctr_nmi(x86_pmu_event_addr(i));
182 release_evntsel_nmi(x86_pmu_config_addr(i));
188 static bool reserve_pmc_hardware(void) { return true; }
189 static void release_pmc_hardware(void) {}
193 static bool check_hw_exists(void)
195 u64 val, val_fail = -1, val_new= ~0;
196 int i, reg, reg_fail = -1, ret = 0;
201 * Check to see if the BIOS enabled any of the counters, if so
204 for (i = 0; i < x86_pmu.num_counters; i++) {
205 reg = x86_pmu_config_addr(i);
206 ret = rdmsrl_safe(reg, &val);
209 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
218 if (x86_pmu.num_counters_fixed) {
219 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
220 ret = rdmsrl_safe(reg, &val);
223 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
224 if (val & (0x03 << i*4)) {
233 * If all the counters are enabled, the below test will always
234 * fail. The tools will also become useless in this scenario.
235 * Just fail and disable the hardware counters.
238 if (reg_safe == -1) {
244 * Read the current value, change it and read it back to see if it
245 * matches, this is needed to detect certain hardware emulators
246 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
248 reg = x86_pmu_event_addr(reg_safe);
249 if (rdmsrl_safe(reg, &val))
252 ret = wrmsrl_safe(reg, val);
253 ret |= rdmsrl_safe(reg, &val_new);
254 if (ret || val != val_new)
258 * We still allow the PMU driver to operate:
261 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
262 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
269 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
270 pr_cont("PMU not available due to virtualization, using software events only.\n");
272 pr_cont("Broken PMU hardware detected, using software events only.\n");
273 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
280 static void hw_perf_event_destroy(struct perf_event *event)
282 x86_release_hardware();
283 atomic_dec(&active_events);
286 void hw_perf_lbr_event_destroy(struct perf_event *event)
288 hw_perf_event_destroy(event);
290 /* undo the lbr/bts event accounting */
291 x86_del_exclusive(x86_lbr_exclusive_lbr);
294 static inline int x86_pmu_initialized(void)
296 return x86_pmu.handle_irq != NULL;
300 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
302 struct perf_event_attr *attr = &event->attr;
303 unsigned int cache_type, cache_op, cache_result;
306 config = attr->config;
308 cache_type = (config >> 0) & 0xff;
309 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
311 cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
313 cache_op = (config >> 8) & 0xff;
314 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
316 cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
318 cache_result = (config >> 16) & 0xff;
319 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
321 cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
323 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
332 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
333 return x86_pmu_extra_regs(val, event);
336 int x86_reserve_hardware(void)
340 if (!atomic_inc_not_zero(&pmc_refcount)) {
341 mutex_lock(&pmc_reserve_mutex);
342 if (atomic_read(&pmc_refcount) == 0) {
343 if (!reserve_pmc_hardware())
346 reserve_ds_buffers();
349 atomic_inc(&pmc_refcount);
350 mutex_unlock(&pmc_reserve_mutex);
356 void x86_release_hardware(void)
358 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
359 release_pmc_hardware();
360 release_ds_buffers();
361 mutex_unlock(&pmc_reserve_mutex);
366 * Check if we can create event of a certain type (that no conflicting events
369 int x86_add_exclusive(unsigned int what)
374 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
375 * LBR and BTS are still mutually exclusive.
377 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
380 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
381 mutex_lock(&pmc_reserve_mutex);
382 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
383 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
386 atomic_inc(&x86_pmu.lbr_exclusive[what]);
387 mutex_unlock(&pmc_reserve_mutex);
390 atomic_inc(&active_events);
394 mutex_unlock(&pmc_reserve_mutex);
398 void x86_del_exclusive(unsigned int what)
400 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
403 atomic_dec(&x86_pmu.lbr_exclusive[what]);
404 atomic_dec(&active_events);
407 int x86_setup_perfctr(struct perf_event *event)
409 struct perf_event_attr *attr = &event->attr;
410 struct hw_perf_event *hwc = &event->hw;
413 if (!is_sampling_event(event)) {
414 hwc->sample_period = x86_pmu.max_period;
415 hwc->last_period = hwc->sample_period;
416 local64_set(&hwc->period_left, hwc->sample_period);
419 if (attr->type == PERF_TYPE_RAW)
420 return x86_pmu_extra_regs(event->attr.config, event);
422 if (attr->type == PERF_TYPE_HW_CACHE)
423 return set_ext_hw_attr(hwc, event);
425 if (attr->config >= x86_pmu.max_events)
428 attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
433 config = x86_pmu.event_map(attr->config);
441 hwc->config |= config;
447 * check that branch_sample_type is compatible with
448 * settings needed for precise_ip > 1 which implies
449 * using the LBR to capture ALL taken branches at the
450 * priv levels of the measurement
452 static inline int precise_br_compat(struct perf_event *event)
454 u64 m = event->attr.branch_sample_type;
457 /* must capture all branches */
458 if (!(m & PERF_SAMPLE_BRANCH_ANY))
461 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
463 if (!event->attr.exclude_user)
464 b |= PERF_SAMPLE_BRANCH_USER;
466 if (!event->attr.exclude_kernel)
467 b |= PERF_SAMPLE_BRANCH_KERNEL;
470 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
476 int x86_pmu_max_precise(void)
480 /* Support for constant skid */
481 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
484 /* Support for IP fixup */
485 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
488 if (x86_pmu.pebs_prec_dist)
494 int x86_pmu_hw_config(struct perf_event *event)
496 if (event->attr.precise_ip) {
497 int precise = x86_pmu_max_precise();
499 if (event->attr.precise_ip > precise)
502 /* There's no sense in having PEBS for non sampling events: */
503 if (!is_sampling_event(event))
507 * check that PEBS LBR correction does not conflict with
508 * whatever the user is asking with attr->branch_sample_type
510 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
511 u64 *br_type = &event->attr.branch_sample_type;
513 if (has_branch_stack(event)) {
514 if (!precise_br_compat(event))
517 /* branch_sample_type is compatible */
521 * user did not specify branch_sample_type
523 * For PEBS fixups, we capture all
524 * the branches at the priv level of the
527 *br_type = PERF_SAMPLE_BRANCH_ANY;
529 if (!event->attr.exclude_user)
530 *br_type |= PERF_SAMPLE_BRANCH_USER;
532 if (!event->attr.exclude_kernel)
533 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
537 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
538 event->attach_state |= PERF_ATTACH_TASK_DATA;
542 * (keep 'enabled' bit clear for now)
544 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
547 * Count user and OS events unless requested not to
549 if (!event->attr.exclude_user)
550 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
551 if (!event->attr.exclude_kernel)
552 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
554 if (event->attr.type == PERF_TYPE_RAW)
555 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
557 if (event->attr.sample_period && x86_pmu.limit_period) {
558 if (x86_pmu.limit_period(event, event->attr.sample_period) >
559 event->attr.sample_period)
563 /* sample_regs_user never support XMM registers */
564 if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
567 * Besides the general purpose registers, XMM registers may
568 * be collected in PEBS on some platforms, e.g. Icelake
570 if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
571 if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
574 if (!event->attr.precise_ip)
578 return x86_setup_perfctr(event);
582 * Setup the hardware configuration for a given attr_type
584 static int __x86_pmu_event_init(struct perf_event *event)
588 if (!x86_pmu_initialized())
591 err = x86_reserve_hardware();
595 atomic_inc(&active_events);
596 event->destroy = hw_perf_event_destroy;
599 event->hw.last_cpu = -1;
600 event->hw.last_tag = ~0ULL;
603 event->hw.extra_reg.idx = EXTRA_REG_NONE;
604 event->hw.branch_reg.idx = EXTRA_REG_NONE;
606 return x86_pmu.hw_config(event);
609 void x86_pmu_disable_all(void)
611 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
614 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
617 if (!test_bit(idx, cpuc->active_mask))
619 rdmsrl(x86_pmu_config_addr(idx), val);
620 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
622 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
623 wrmsrl(x86_pmu_config_addr(idx), val);
628 * There may be PMI landing after enabled=0. The PMI hitting could be before or
631 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
632 * It will not be re-enabled in the NMI handler again, because enabled=0. After
633 * handling the NMI, disable_all will be called, which will not change the
634 * state either. If PMI hits after disable_all, the PMU is already disabled
635 * before entering NMI handler. The NMI handler will not change the state
638 * So either situation is harmless.
640 static void x86_pmu_disable(struct pmu *pmu)
642 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
644 if (!x86_pmu_initialized())
654 x86_pmu.disable_all();
657 void x86_pmu_enable_all(int added)
659 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
662 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
663 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
665 if (!test_bit(idx, cpuc->active_mask))
668 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
672 static struct pmu pmu;
674 static inline int is_x86_event(struct perf_event *event)
676 return event->pmu == &pmu;
679 struct pmu *x86_get_pmu(void)
684 * Event scheduler state:
686 * Assign events iterating over all events and counters, beginning
687 * with events with least weights first. Keep the current iterator
688 * state in struct sched_state.
692 int event; /* event index */
693 int counter; /* counter index */
694 int unassigned; /* number of events to be assigned left */
695 int nr_gp; /* number of GP counters used */
696 unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
699 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
700 #define SCHED_STATES_MAX 2
707 struct event_constraint **constraints;
708 struct sched_state state;
709 struct sched_state saved[SCHED_STATES_MAX];
713 * Initialize interator that runs through all events and counters.
715 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
716 int num, int wmin, int wmax, int gpmax)
720 memset(sched, 0, sizeof(*sched));
721 sched->max_events = num;
722 sched->max_weight = wmax;
723 sched->max_gp = gpmax;
724 sched->constraints = constraints;
726 for (idx = 0; idx < num; idx++) {
727 if (constraints[idx]->weight == wmin)
731 sched->state.event = idx; /* start with min weight */
732 sched->state.weight = wmin;
733 sched->state.unassigned = num;
736 static void perf_sched_save_state(struct perf_sched *sched)
738 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
741 sched->saved[sched->saved_states] = sched->state;
742 sched->saved_states++;
745 static bool perf_sched_restore_state(struct perf_sched *sched)
747 if (!sched->saved_states)
750 sched->saved_states--;
751 sched->state = sched->saved[sched->saved_states];
753 /* continue with next counter: */
754 clear_bit(sched->state.counter++, sched->state.used);
760 * Select a counter for the current event to schedule. Return true on
763 static bool __perf_sched_find_counter(struct perf_sched *sched)
765 struct event_constraint *c;
768 if (!sched->state.unassigned)
771 if (sched->state.event >= sched->max_events)
774 c = sched->constraints[sched->state.event];
775 /* Prefer fixed purpose counters */
776 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
777 idx = INTEL_PMC_IDX_FIXED;
778 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
779 if (!__test_and_set_bit(idx, sched->state.used))
784 /* Grab the first unused counter starting with idx */
785 idx = sched->state.counter;
786 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
787 if (!__test_and_set_bit(idx, sched->state.used)) {
788 if (sched->state.nr_gp++ >= sched->max_gp)
798 sched->state.counter = idx;
801 perf_sched_save_state(sched);
806 static bool perf_sched_find_counter(struct perf_sched *sched)
808 while (!__perf_sched_find_counter(sched)) {
809 if (!perf_sched_restore_state(sched))
817 * Go through all unassigned events and find the next one to schedule.
818 * Take events with the least weight first. Return true on success.
820 static bool perf_sched_next_event(struct perf_sched *sched)
822 struct event_constraint *c;
824 if (!sched->state.unassigned || !--sched->state.unassigned)
829 sched->state.event++;
830 if (sched->state.event >= sched->max_events) {
832 sched->state.event = 0;
833 sched->state.weight++;
834 if (sched->state.weight > sched->max_weight)
837 c = sched->constraints[sched->state.event];
838 } while (c->weight != sched->state.weight);
840 sched->state.counter = 0; /* start with first counter */
846 * Assign a counter for each event.
848 int perf_assign_events(struct event_constraint **constraints, int n,
849 int wmin, int wmax, int gpmax, int *assign)
851 struct perf_sched sched;
853 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
856 if (!perf_sched_find_counter(&sched))
859 assign[sched.state.event] = sched.state.counter;
860 } while (perf_sched_next_event(&sched));
862 return sched.state.unassigned;
864 EXPORT_SYMBOL_GPL(perf_assign_events);
866 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
868 struct event_constraint *c;
869 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
870 struct perf_event *e;
871 int n0, i, wmin, wmax, unsched = 0;
872 struct hw_perf_event *hwc;
874 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
877 * Compute the number of events already present; see x86_pmu_add(),
878 * validate_group() and x86_pmu_commit_txn(). For the former two
879 * cpuc->n_events hasn't been updated yet, while for the latter
880 * cpuc->n_txn contains the number of events added in the current
884 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
887 if (x86_pmu.start_scheduling)
888 x86_pmu.start_scheduling(cpuc);
890 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
891 c = cpuc->event_constraint[i];
894 * Previously scheduled events should have a cached constraint,
895 * while new events should not have one.
897 WARN_ON_ONCE((c && i >= n0) || (!c && i < n0));
900 * Request constraints for new events; or for those events that
901 * have a dynamic constraint -- for those the constraint can
902 * change due to external factors (sibling state, allow_tfa).
904 if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) {
905 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
906 cpuc->event_constraint[i] = c;
909 wmin = min(wmin, c->weight);
910 wmax = max(wmax, c->weight);
914 * fastpath, try to reuse previous register
916 for (i = 0; i < n; i++) {
917 hwc = &cpuc->event_list[i]->hw;
918 c = cpuc->event_constraint[i];
924 /* constraint still honored */
925 if (!test_bit(hwc->idx, c->idxmsk))
928 /* not already used */
929 if (test_bit(hwc->idx, used_mask))
932 __set_bit(hwc->idx, used_mask);
934 assign[i] = hwc->idx;
939 int gpmax = x86_pmu.num_counters;
942 * Do not allow scheduling of more than half the available
945 * This helps avoid counter starvation of sibling thread by
946 * ensuring at most half the counters cannot be in exclusive
947 * mode. There is no designated counters for the limits. Any
948 * N/2 counters can be used. This helps with events with
949 * specific counter constraints.
951 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
952 READ_ONCE(cpuc->excl_cntrs->exclusive_present))
955 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
956 wmax, gpmax, assign);
960 * In case of success (unsched = 0), mark events as committed,
961 * so we do not put_constraint() in case new events are added
962 * and fail to be scheduled
964 * We invoke the lower level commit callback to lock the resource
966 * We do not need to do all of this in case we are called to
967 * validate an event group (assign == NULL)
969 if (!unsched && assign) {
970 for (i = 0; i < n; i++) {
971 e = cpuc->event_list[i];
972 if (x86_pmu.commit_scheduling)
973 x86_pmu.commit_scheduling(cpuc, i, assign[i]);
976 for (i = n0; i < n; i++) {
977 e = cpuc->event_list[i];
980 * release events that failed scheduling
982 if (x86_pmu.put_event_constraints)
983 x86_pmu.put_event_constraints(cpuc, e);
985 cpuc->event_constraint[i] = NULL;
989 if (x86_pmu.stop_scheduling)
990 x86_pmu.stop_scheduling(cpuc);
992 return unsched ? -EINVAL : 0;
996 * dogrp: true if must collect siblings events (group)
997 * returns total number of events and error code
999 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1001 struct perf_event *event;
1004 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
1006 /* current number of events already accepted */
1009 if (is_x86_event(leader)) {
1012 cpuc->event_list[n] = leader;
1018 for_each_sibling_event(event, leader) {
1019 if (!is_x86_event(event) ||
1020 event->state <= PERF_EVENT_STATE_OFF)
1026 cpuc->event_list[n] = event;
1032 static inline void x86_assign_hw_event(struct perf_event *event,
1033 struct cpu_hw_events *cpuc, int i)
1035 struct hw_perf_event *hwc = &event->hw;
1037 hwc->idx = cpuc->assign[i];
1038 hwc->last_cpu = smp_processor_id();
1039 hwc->last_tag = ++cpuc->tags[i];
1041 if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
1042 hwc->config_base = 0;
1043 hwc->event_base = 0;
1044 } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
1045 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1046 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
1047 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
1049 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1050 hwc->event_base = x86_pmu_event_addr(hwc->idx);
1051 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1056 * x86_perf_rdpmc_index - Return PMC counter used for event
1057 * @event: the perf_event to which the PMC counter was assigned
1059 * The counter assigned to this performance event may change if interrupts
1060 * are enabled. This counter should thus never be used while interrupts are
1061 * enabled. Before this function is used to obtain the assigned counter the
1062 * event should be checked for validity using, for example,
1063 * perf_event_read_local(), within the same interrupt disabled section in
1064 * which this counter is planned to be used.
1066 * Return: The index of the performance monitoring counter assigned to
1069 int x86_perf_rdpmc_index(struct perf_event *event)
1071 lockdep_assert_irqs_disabled();
1073 return event->hw.event_base_rdpmc;
1076 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1077 struct cpu_hw_events *cpuc,
1080 return hwc->idx == cpuc->assign[i] &&
1081 hwc->last_cpu == smp_processor_id() &&
1082 hwc->last_tag == cpuc->tags[i];
1085 static void x86_pmu_start(struct perf_event *event, int flags);
1087 static void x86_pmu_enable(struct pmu *pmu)
1089 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1090 struct perf_event *event;
1091 struct hw_perf_event *hwc;
1092 int i, added = cpuc->n_added;
1094 if (!x86_pmu_initialized())
1100 if (cpuc->n_added) {
1101 int n_running = cpuc->n_events - cpuc->n_added;
1103 * apply assignment obtained either from
1104 * hw_perf_group_sched_in() or x86_pmu_enable()
1106 * step1: save events moving to new counters
1108 for (i = 0; i < n_running; i++) {
1109 event = cpuc->event_list[i];
1113 * we can avoid reprogramming counter if:
1114 * - assigned same counter as last time
1115 * - running on same CPU as last time
1116 * - no other event has used the counter since
1118 if (hwc->idx == -1 ||
1119 match_prev_assignment(hwc, cpuc, i))
1123 * Ensure we don't accidentally enable a stopped
1124 * counter simply because we rescheduled.
1126 if (hwc->state & PERF_HES_STOPPED)
1127 hwc->state |= PERF_HES_ARCH;
1129 x86_pmu_stop(event, PERF_EF_UPDATE);
1133 * step2: reprogram moved events into new counters
1135 for (i = 0; i < cpuc->n_events; i++) {
1136 event = cpuc->event_list[i];
1139 if (!match_prev_assignment(hwc, cpuc, i))
1140 x86_assign_hw_event(event, cpuc, i);
1141 else if (i < n_running)
1144 if (hwc->state & PERF_HES_ARCH)
1147 x86_pmu_start(event, PERF_EF_RELOAD);
1150 perf_events_lapic_init();
1156 x86_pmu.enable_all(added);
1159 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1162 * Set the next IRQ period, based on the hwc->period_left value.
1163 * To be called with the event disabled in hw:
1165 int x86_perf_event_set_period(struct perf_event *event)
1167 struct hw_perf_event *hwc = &event->hw;
1168 s64 left = local64_read(&hwc->period_left);
1169 s64 period = hwc->sample_period;
1170 int ret = 0, idx = hwc->idx;
1172 if (idx == INTEL_PMC_IDX_FIXED_BTS)
1176 * If we are way outside a reasonable range then just skip forward:
1178 if (unlikely(left <= -period)) {
1180 local64_set(&hwc->period_left, left);
1181 hwc->last_period = period;
1185 if (unlikely(left <= 0)) {
1187 local64_set(&hwc->period_left, left);
1188 hwc->last_period = period;
1192 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1194 if (unlikely(left < 2))
1197 if (left > x86_pmu.max_period)
1198 left = x86_pmu.max_period;
1200 if (x86_pmu.limit_period)
1201 left = x86_pmu.limit_period(event, left);
1203 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1206 * The hw event starts counting from this event offset,
1207 * mark it to be able to extra future deltas:
1209 local64_set(&hwc->prev_count, (u64)-left);
1211 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1214 * Due to erratum on certan cpu we need
1215 * a second write to be sure the register
1216 * is updated properly
1218 if (x86_pmu.perfctr_second_write) {
1219 wrmsrl(hwc->event_base,
1220 (u64)(-left) & x86_pmu.cntval_mask);
1223 perf_event_update_userpage(event);
1228 void x86_pmu_enable_event(struct perf_event *event)
1230 if (__this_cpu_read(cpu_hw_events.enabled))
1231 __x86_pmu_enable_event(&event->hw,
1232 ARCH_PERFMON_EVENTSEL_ENABLE);
1236 * Add a single event to the PMU.
1238 * The event is added to the group of enabled events
1239 * but only if it can be scehduled with existing events.
1241 static int x86_pmu_add(struct perf_event *event, int flags)
1243 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1244 struct hw_perf_event *hwc;
1245 int assign[X86_PMC_IDX_MAX];
1250 n0 = cpuc->n_events;
1251 ret = n = collect_events(cpuc, event, false);
1255 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1256 if (!(flags & PERF_EF_START))
1257 hwc->state |= PERF_HES_ARCH;
1260 * If group events scheduling transaction was started,
1261 * skip the schedulability test here, it will be performed
1262 * at commit time (->commit_txn) as a whole.
1264 * If commit fails, we'll call ->del() on all events
1265 * for which ->add() was called.
1267 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1270 ret = x86_pmu.schedule_events(cpuc, n, assign);
1274 * copy new assignment, now we know it is possible
1275 * will be used by hw_perf_enable()
1277 memcpy(cpuc->assign, assign, n*sizeof(int));
1281 * Commit the collect_events() state. See x86_pmu_del() and
1285 cpuc->n_added += n - n0;
1286 cpuc->n_txn += n - n0;
1290 * This is before x86_pmu_enable() will call x86_pmu_start(),
1291 * so we enable LBRs before an event needs them etc..
1301 static void x86_pmu_start(struct perf_event *event, int flags)
1303 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1304 int idx = event->hw.idx;
1306 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1309 if (WARN_ON_ONCE(idx == -1))
1312 if (flags & PERF_EF_RELOAD) {
1313 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1314 x86_perf_event_set_period(event);
1317 event->hw.state = 0;
1319 cpuc->events[idx] = event;
1320 __set_bit(idx, cpuc->active_mask);
1321 __set_bit(idx, cpuc->running);
1322 x86_pmu.enable(event);
1323 perf_event_update_userpage(event);
1326 void perf_event_print_debug(void)
1328 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1330 struct cpu_hw_events *cpuc;
1331 unsigned long flags;
1334 if (!x86_pmu.num_counters)
1337 local_irq_save(flags);
1339 cpu = smp_processor_id();
1340 cpuc = &per_cpu(cpu_hw_events, cpu);
1342 if (x86_pmu.version >= 2) {
1343 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1344 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1345 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1346 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1349 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1350 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1351 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1352 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1353 if (x86_pmu.pebs_constraints) {
1354 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1355 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1357 if (x86_pmu.lbr_nr) {
1358 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1359 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1362 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1364 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1365 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1366 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1368 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1370 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1371 cpu, idx, pmc_ctrl);
1372 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1373 cpu, idx, pmc_count);
1374 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1375 cpu, idx, prev_left);
1377 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1378 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1380 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1381 cpu, idx, pmc_count);
1383 local_irq_restore(flags);
1386 void x86_pmu_stop(struct perf_event *event, int flags)
1388 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1389 struct hw_perf_event *hwc = &event->hw;
1391 if (test_bit(hwc->idx, cpuc->active_mask)) {
1392 x86_pmu.disable(event);
1393 __clear_bit(hwc->idx, cpuc->active_mask);
1394 cpuc->events[hwc->idx] = NULL;
1395 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1396 hwc->state |= PERF_HES_STOPPED;
1399 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1401 * Drain the remaining delta count out of a event
1402 * that we are disabling:
1404 x86_perf_event_update(event);
1405 hwc->state |= PERF_HES_UPTODATE;
1409 static void x86_pmu_del(struct perf_event *event, int flags)
1411 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1415 * If we're called during a txn, we only need to undo x86_pmu.add.
1416 * The events never got scheduled and ->cancel_txn will truncate
1419 * XXX assumes any ->del() called during a TXN will only be on
1420 * an event added during that same TXN.
1422 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1426 * Not a TXN, therefore cleanup properly.
1428 x86_pmu_stop(event, PERF_EF_UPDATE);
1430 for (i = 0; i < cpuc->n_events; i++) {
1431 if (event == cpuc->event_list[i])
1435 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1438 /* If we have a newly added event; make sure to decrease n_added. */
1439 if (i >= cpuc->n_events - cpuc->n_added)
1442 if (x86_pmu.put_event_constraints)
1443 x86_pmu.put_event_constraints(cpuc, event);
1445 /* Delete the array entry. */
1446 while (++i < cpuc->n_events) {
1447 cpuc->event_list[i-1] = cpuc->event_list[i];
1448 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1450 cpuc->event_constraint[i-1] = NULL;
1453 perf_event_update_userpage(event);
1458 * This is after x86_pmu_stop(); so we disable LBRs after any
1459 * event can need them etc..
1465 int x86_pmu_handle_irq(struct pt_regs *regs)
1467 struct perf_sample_data data;
1468 struct cpu_hw_events *cpuc;
1469 struct perf_event *event;
1470 int idx, handled = 0;
1473 cpuc = this_cpu_ptr(&cpu_hw_events);
1476 * Some chipsets need to unmask the LVTPC in a particular spot
1477 * inside the nmi handler. As a result, the unmasking was pushed
1478 * into all the nmi handlers.
1480 * This generic handler doesn't seem to have any issues where the
1481 * unmasking occurs so it was left at the top.
1483 apic_write(APIC_LVTPC, APIC_DM_NMI);
1485 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1486 if (!test_bit(idx, cpuc->active_mask))
1489 event = cpuc->events[idx];
1491 val = x86_perf_event_update(event);
1492 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1499 perf_sample_data_init(&data, 0, event->hw.last_period);
1501 if (!x86_perf_event_set_period(event))
1504 if (perf_event_overflow(event, &data, regs))
1505 x86_pmu_stop(event, 0);
1509 inc_irq_stat(apic_perf_irqs);
1514 void perf_events_lapic_init(void)
1516 if (!x86_pmu.apic || !x86_pmu_initialized())
1520 * Always use NMI for PMU
1522 apic_write(APIC_LVTPC, APIC_DM_NMI);
1526 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1533 * All PMUs/events that share this PMI handler should make sure to
1534 * increment active_events for their events.
1536 if (!atomic_read(&active_events))
1539 start_clock = sched_clock();
1540 ret = x86_pmu.handle_irq(regs);
1541 finish_clock = sched_clock();
1543 perf_sample_event_took(finish_clock - start_clock);
1547 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1549 struct event_constraint emptyconstraint;
1550 struct event_constraint unconstrained;
1552 static int x86_pmu_prepare_cpu(unsigned int cpu)
1554 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1557 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1558 cpuc->kfree_on_online[i] = NULL;
1559 if (x86_pmu.cpu_prepare)
1560 return x86_pmu.cpu_prepare(cpu);
1564 static int x86_pmu_dead_cpu(unsigned int cpu)
1566 if (x86_pmu.cpu_dead)
1567 x86_pmu.cpu_dead(cpu);
1571 static int x86_pmu_online_cpu(unsigned int cpu)
1573 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1576 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1577 kfree(cpuc->kfree_on_online[i]);
1578 cpuc->kfree_on_online[i] = NULL;
1583 static int x86_pmu_starting_cpu(unsigned int cpu)
1585 if (x86_pmu.cpu_starting)
1586 x86_pmu.cpu_starting(cpu);
1590 static int x86_pmu_dying_cpu(unsigned int cpu)
1592 if (x86_pmu.cpu_dying)
1593 x86_pmu.cpu_dying(cpu);
1597 static void __init pmu_check_apic(void)
1599 if (boot_cpu_has(X86_FEATURE_APIC))
1603 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1604 pr_info("no hardware sampling interrupt available.\n");
1607 * If we have a PMU initialized but no APIC
1608 * interrupts, we cannot sample hardware
1609 * events (user-space has to fall back and
1610 * sample via a hrtimer based software event):
1612 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1616 static struct attribute_group x86_pmu_format_group __ro_after_init = {
1621 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1623 struct perf_pmu_events_attr *pmu_attr = \
1624 container_of(attr, struct perf_pmu_events_attr, attr);
1625 u64 config = x86_pmu.event_map(pmu_attr->id);
1627 /* string trumps id */
1628 if (pmu_attr->event_str)
1629 return sprintf(page, "%s", pmu_attr->event_str);
1631 return x86_pmu.events_sysfs_show(page, config);
1633 EXPORT_SYMBOL_GPL(events_sysfs_show);
1635 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1638 struct perf_pmu_events_ht_attr *pmu_attr =
1639 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1642 * Report conditional events depending on Hyper-Threading.
1644 * This is overly conservative as usually the HT special
1645 * handling is not needed if the other CPU thread is idle.
1647 * Note this does not (and cannot) handle the case when thread
1648 * siblings are invisible, for example with virtualization
1649 * if they are owned by some other guest. The user tool
1650 * has to re-read when a thread sibling gets onlined later.
1652 return sprintf(page, "%s",
1653 topology_max_smt_threads() > 1 ?
1654 pmu_attr->event_str_ht :
1655 pmu_attr->event_str_noht);
1658 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1659 EVENT_ATTR(instructions, INSTRUCTIONS );
1660 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1661 EVENT_ATTR(cache-misses, CACHE_MISSES );
1662 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1663 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1664 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1665 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1666 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1667 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1669 static struct attribute *empty_attrs;
1671 static struct attribute *events_attr[] = {
1672 EVENT_PTR(CPU_CYCLES),
1673 EVENT_PTR(INSTRUCTIONS),
1674 EVENT_PTR(CACHE_REFERENCES),
1675 EVENT_PTR(CACHE_MISSES),
1676 EVENT_PTR(BRANCH_INSTRUCTIONS),
1677 EVENT_PTR(BRANCH_MISSES),
1678 EVENT_PTR(BUS_CYCLES),
1679 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1680 EVENT_PTR(STALLED_CYCLES_BACKEND),
1681 EVENT_PTR(REF_CPU_CYCLES),
1686 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1687 * out of events_attr attributes.
1690 is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1692 struct perf_pmu_events_attr *pmu_attr;
1694 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
1696 return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0;
1699 static struct attribute_group x86_pmu_events_group __ro_after_init = {
1701 .attrs = events_attr,
1702 .is_visible = is_visible,
1705 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1707 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1708 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1709 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1710 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1711 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1712 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1716 * We have whole page size to spend and just little data
1717 * to write, so we can safely use sprintf.
1719 ret = sprintf(page, "event=0x%02llx", event);
1722 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1725 ret += sprintf(page + ret, ",edge");
1728 ret += sprintf(page + ret, ",pc");
1731 ret += sprintf(page + ret, ",any");
1734 ret += sprintf(page + ret, ",inv");
1737 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1739 ret += sprintf(page + ret, "\n");
1744 static struct attribute_group x86_pmu_attr_group;
1745 static struct attribute_group x86_pmu_caps_group;
1747 static int __init init_hw_perf_events(void)
1749 struct x86_pmu_quirk *quirk;
1752 pr_info("Performance Events: ");
1754 switch (boot_cpu_data.x86_vendor) {
1755 case X86_VENDOR_INTEL:
1756 err = intel_pmu_init();
1758 case X86_VENDOR_AMD:
1759 err = amd_pmu_init();
1761 case X86_VENDOR_HYGON:
1762 err = amd_pmu_init();
1763 x86_pmu.name = "HYGON";
1769 pr_cont("no PMU driver, software events only.\n");
1775 /* sanity check that the hardware exists or is emulated */
1776 if (!check_hw_exists())
1779 pr_cont("%s PMU driver.\n", x86_pmu.name);
1781 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1783 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1786 if (!x86_pmu.intel_ctrl)
1787 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1789 perf_events_lapic_init();
1790 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1792 unconstrained = (struct event_constraint)
1793 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1794 0, x86_pmu.num_counters, 0, 0);
1796 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1798 if (!x86_pmu.events_sysfs_show)
1799 x86_pmu_events_group.attrs = &empty_attrs;
1801 pmu.attr_update = x86_pmu.attr_update;
1803 pr_info("... version: %d\n", x86_pmu.version);
1804 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1805 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1806 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1807 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1808 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1809 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1812 * Install callbacks. Core will call them for each online
1815 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare",
1816 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
1820 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
1821 "perf/x86:starting", x86_pmu_starting_cpu,
1826 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online",
1827 x86_pmu_online_cpu, NULL);
1831 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1838 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
1840 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
1842 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
1845 early_initcall(init_hw_perf_events);
1847 static inline void x86_pmu_read(struct perf_event *event)
1850 return x86_pmu.read(event);
1851 x86_perf_event_update(event);
1855 * Start group events scheduling transaction
1856 * Set the flag to make pmu::enable() not perform the
1857 * schedulability test, it will be performed at commit time
1859 * We only support PERF_PMU_TXN_ADD transactions. Save the
1860 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1863 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1865 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1867 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */
1869 cpuc->txn_flags = txn_flags;
1870 if (txn_flags & ~PERF_PMU_TXN_ADD)
1873 perf_pmu_disable(pmu);
1874 __this_cpu_write(cpu_hw_events.n_txn, 0);
1878 * Stop group events scheduling transaction
1879 * Clear the flag and pmu::enable() will perform the
1880 * schedulability test.
1882 static void x86_pmu_cancel_txn(struct pmu *pmu)
1884 unsigned int txn_flags;
1885 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1887 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1889 txn_flags = cpuc->txn_flags;
1890 cpuc->txn_flags = 0;
1891 if (txn_flags & ~PERF_PMU_TXN_ADD)
1895 * Truncate collected array by the number of events added in this
1896 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1898 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1899 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1900 perf_pmu_enable(pmu);
1904 * Commit group events scheduling transaction
1905 * Perform the group schedulability test as a whole
1906 * Return 0 if success
1908 * Does not cancel the transaction on failure; expects the caller to do this.
1910 static int x86_pmu_commit_txn(struct pmu *pmu)
1912 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1913 int assign[X86_PMC_IDX_MAX];
1916 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1918 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
1919 cpuc->txn_flags = 0;
1925 if (!x86_pmu_initialized())
1928 ret = x86_pmu.schedule_events(cpuc, n, assign);
1933 * copy new assignment, now we know it is possible
1934 * will be used by hw_perf_enable()
1936 memcpy(cpuc->assign, assign, n*sizeof(int));
1938 cpuc->txn_flags = 0;
1939 perf_pmu_enable(pmu);
1943 * a fake_cpuc is used to validate event groups. Due to
1944 * the extra reg logic, we need to also allocate a fake
1945 * per_core and per_cpu structure. Otherwise, group events
1946 * using extra reg may conflict without the kernel being
1947 * able to catch this when the last event gets added to
1950 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1952 intel_cpuc_finish(cpuc);
1956 static struct cpu_hw_events *allocate_fake_cpuc(void)
1958 struct cpu_hw_events *cpuc;
1959 int cpu = raw_smp_processor_id();
1961 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1963 return ERR_PTR(-ENOMEM);
1966 if (intel_cpuc_prepare(cpuc, cpu))
1971 free_fake_cpuc(cpuc);
1972 return ERR_PTR(-ENOMEM);
1976 * validate that we can schedule this event
1978 static int validate_event(struct perf_event *event)
1980 struct cpu_hw_events *fake_cpuc;
1981 struct event_constraint *c;
1984 fake_cpuc = allocate_fake_cpuc();
1985 if (IS_ERR(fake_cpuc))
1986 return PTR_ERR(fake_cpuc);
1988 c = x86_pmu.get_event_constraints(fake_cpuc, 0, event);
1990 if (!c || !c->weight)
1993 if (x86_pmu.put_event_constraints)
1994 x86_pmu.put_event_constraints(fake_cpuc, event);
1996 free_fake_cpuc(fake_cpuc);
2002 * validate a single event group
2004 * validation include:
2005 * - check events are compatible which each other
2006 * - events do not compete for the same counter
2007 * - number of events <= number of counters
2009 * validation ensures the group can be loaded onto the
2010 * PMU if it was the only group available.
2012 static int validate_group(struct perf_event *event)
2014 struct perf_event *leader = event->group_leader;
2015 struct cpu_hw_events *fake_cpuc;
2016 int ret = -EINVAL, n;
2018 fake_cpuc = allocate_fake_cpuc();
2019 if (IS_ERR(fake_cpuc))
2020 return PTR_ERR(fake_cpuc);
2022 * the event is not yet connected with its
2023 * siblings therefore we must first collect
2024 * existing siblings, then add the new event
2025 * before we can simulate the scheduling
2027 n = collect_events(fake_cpuc, leader, true);
2031 fake_cpuc->n_events = n;
2032 n = collect_events(fake_cpuc, event, false);
2036 fake_cpuc->n_events = 0;
2037 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2040 free_fake_cpuc(fake_cpuc);
2044 static int x86_pmu_event_init(struct perf_event *event)
2049 switch (event->attr.type) {
2051 case PERF_TYPE_HARDWARE:
2052 case PERF_TYPE_HW_CACHE:
2059 err = __x86_pmu_event_init(event);
2062 * we temporarily connect event to its pmu
2063 * such that validate_group() can classify
2064 * it as an x86 event using is_x86_event()
2069 if (event->group_leader != event)
2070 err = validate_group(event);
2072 err = validate_event(event);
2078 event->destroy(event);
2081 if (READ_ONCE(x86_pmu.attr_rdpmc) &&
2082 !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
2083 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
2088 static void refresh_pce(void *ignored)
2090 load_mm_cr4(this_cpu_read(cpu_tlbstate.loaded_mm));
2093 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
2095 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2099 * This function relies on not being called concurrently in two
2100 * tasks in the same mm. Otherwise one task could observe
2101 * perf_rdpmc_allowed > 1 and return all the way back to
2102 * userspace with CR4.PCE clear while another task is still
2103 * doing on_each_cpu_mask() to propagate CR4.PCE.
2105 * For now, this can't happen because all callers hold mmap_sem
2106 * for write. If this changes, we'll need a different solution.
2108 lockdep_assert_held_write(&mm->mmap_sem);
2110 if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1)
2111 on_each_cpu_mask(mm_cpumask(mm), refresh_pce, NULL, 1);
2114 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
2117 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2120 if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed))
2121 on_each_cpu_mask(mm_cpumask(mm), refresh_pce, NULL, 1);
2124 static int x86_pmu_event_idx(struct perf_event *event)
2126 int idx = event->hw.idx;
2128 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2131 if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
2132 idx -= INTEL_PMC_IDX_FIXED;
2139 static ssize_t get_attr_rdpmc(struct device *cdev,
2140 struct device_attribute *attr,
2143 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2146 static ssize_t set_attr_rdpmc(struct device *cdev,
2147 struct device_attribute *attr,
2148 const char *buf, size_t count)
2153 ret = kstrtoul(buf, 0, &val);
2160 if (x86_pmu.attr_rdpmc_broken)
2163 if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
2165 * Changing into or out of always available, aka
2166 * perf-event-bypassing mode. This path is extremely slow,
2167 * but only root can trigger it, so it's okay.
2170 static_branch_inc(&rdpmc_always_available_key);
2172 static_branch_dec(&rdpmc_always_available_key);
2173 on_each_cpu(refresh_pce, NULL, 1);
2176 x86_pmu.attr_rdpmc = val;
2181 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2183 static struct attribute *x86_pmu_attrs[] = {
2184 &dev_attr_rdpmc.attr,
2188 static struct attribute_group x86_pmu_attr_group __ro_after_init = {
2189 .attrs = x86_pmu_attrs,
2192 static ssize_t max_precise_show(struct device *cdev,
2193 struct device_attribute *attr,
2196 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
2199 static DEVICE_ATTR_RO(max_precise);
2201 static struct attribute *x86_pmu_caps_attrs[] = {
2202 &dev_attr_max_precise.attr,
2206 static struct attribute_group x86_pmu_caps_group __ro_after_init = {
2208 .attrs = x86_pmu_caps_attrs,
2211 static const struct attribute_group *x86_pmu_attr_groups[] = {
2212 &x86_pmu_attr_group,
2213 &x86_pmu_format_group,
2214 &x86_pmu_events_group,
2215 &x86_pmu_caps_group,
2219 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2221 if (x86_pmu.sched_task)
2222 x86_pmu.sched_task(ctx, sched_in);
2225 void perf_check_microcode(void)
2227 if (x86_pmu.check_microcode)
2228 x86_pmu.check_microcode();
2231 static int x86_pmu_check_period(struct perf_event *event, u64 value)
2233 if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2236 if (value && x86_pmu.limit_period) {
2237 if (x86_pmu.limit_period(event, value) > value)
2244 static struct pmu pmu = {
2245 .pmu_enable = x86_pmu_enable,
2246 .pmu_disable = x86_pmu_disable,
2248 .attr_groups = x86_pmu_attr_groups,
2250 .event_init = x86_pmu_event_init,
2252 .event_mapped = x86_pmu_event_mapped,
2253 .event_unmapped = x86_pmu_event_unmapped,
2257 .start = x86_pmu_start,
2258 .stop = x86_pmu_stop,
2259 .read = x86_pmu_read,
2261 .start_txn = x86_pmu_start_txn,
2262 .cancel_txn = x86_pmu_cancel_txn,
2263 .commit_txn = x86_pmu_commit_txn,
2265 .event_idx = x86_pmu_event_idx,
2266 .sched_task = x86_pmu_sched_task,
2267 .task_ctx_size = sizeof(struct x86_perf_task_context),
2268 .check_period = x86_pmu_check_period,
2271 void arch_perf_update_userpage(struct perf_event *event,
2272 struct perf_event_mmap_page *userpg, u64 now)
2274 struct cyc2ns_data data;
2277 userpg->cap_user_time = 0;
2278 userpg->cap_user_time_zero = 0;
2279 userpg->cap_user_rdpmc =
2280 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2281 userpg->pmc_width = x86_pmu.cntval_bits;
2283 if (!using_native_sched_clock() || !sched_clock_stable())
2286 cyc2ns_read_begin(&data);
2288 offset = data.cyc2ns_offset + __sched_clock_offset;
2291 * Internal timekeeping for enabled/running/stopped times
2292 * is always in the local_clock domain.
2294 userpg->cap_user_time = 1;
2295 userpg->time_mult = data.cyc2ns_mul;
2296 userpg->time_shift = data.cyc2ns_shift;
2297 userpg->time_offset = offset - now;
2300 * cap_user_time_zero doesn't make sense when we're using a different
2301 * time base for the records.
2303 if (!event->attr.use_clockid) {
2304 userpg->cap_user_time_zero = 1;
2305 userpg->time_zero = offset;
2312 * Determine whether the regs were taken from an irq/exception handler rather
2313 * than from perf_arch_fetch_caller_regs().
2315 static bool perf_hw_regs(struct pt_regs *regs)
2317 return regs->flags & X86_EFLAGS_FIXED;
2321 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2323 struct unwind_state state;
2326 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2327 /* TODO: We don't support guest os callchain now */
2331 if (perf_callchain_store(entry, regs->ip))
2334 if (perf_hw_regs(regs))
2335 unwind_start(&state, current, regs, NULL);
2337 unwind_start(&state, current, NULL, (void *)regs->sp);
2339 for (; !unwind_done(&state); unwind_next_frame(&state)) {
2340 addr = unwind_get_return_address(&state);
2341 if (!addr || perf_callchain_store(entry, addr))
2347 valid_user_frame(const void __user *fp, unsigned long size)
2349 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2352 static unsigned long get_segment_base(unsigned int segment)
2354 struct desc_struct *desc;
2355 unsigned int idx = segment >> 3;
2357 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2358 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2359 struct ldt_struct *ldt;
2361 /* IRQs are off, so this synchronizes with smp_store_release */
2362 ldt = READ_ONCE(current->active_mm->context.ldt);
2363 if (!ldt || idx >= ldt->nr_entries)
2366 desc = &ldt->entries[idx];
2371 if (idx >= GDT_ENTRIES)
2374 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2377 return get_desc_base(desc);
2380 #ifdef CONFIG_IA32_EMULATION
2382 #include <linux/compat.h>
2385 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2387 /* 32-bit process in 64-bit kernel. */
2388 unsigned long ss_base, cs_base;
2389 struct stack_frame_ia32 frame;
2390 const void __user *fp;
2392 if (!test_thread_flag(TIF_IA32))
2395 cs_base = get_segment_base(regs->cs);
2396 ss_base = get_segment_base(regs->ss);
2398 fp = compat_ptr(ss_base + regs->bp);
2399 pagefault_disable();
2400 while (entry->nr < entry->max_stack) {
2401 unsigned long bytes;
2402 frame.next_frame = 0;
2403 frame.return_address = 0;
2405 if (!valid_user_frame(fp, sizeof(frame)))
2408 bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4);
2411 bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4);
2415 perf_callchain_store(entry, cs_base + frame.return_address);
2416 fp = compat_ptr(ss_base + frame.next_frame);
2423 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2430 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2432 struct stack_frame frame;
2433 const unsigned long __user *fp;
2435 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2436 /* TODO: We don't support guest os callchain now */
2441 * We don't know what to do with VM86 stacks.. ignore them for now.
2443 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2446 fp = (unsigned long __user *)regs->bp;
2448 perf_callchain_store(entry, regs->ip);
2450 if (!nmi_uaccess_okay())
2453 if (perf_callchain_user32(regs, entry))
2456 pagefault_disable();
2457 while (entry->nr < entry->max_stack) {
2458 unsigned long bytes;
2460 frame.next_frame = NULL;
2461 frame.return_address = 0;
2463 if (!valid_user_frame(fp, sizeof(frame)))
2466 bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp));
2469 bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp));
2473 perf_callchain_store(entry, frame.return_address);
2474 fp = (void __user *)frame.next_frame;
2480 * Deal with code segment offsets for the various execution modes:
2482 * VM86 - the good olde 16 bit days, where the linear address is
2483 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2485 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2486 * to figure out what the 32bit base address is.
2488 * X32 - has TIF_X32 set, but is running in x86_64
2490 * X86_64 - CS,DS,SS,ES are all zero based.
2492 static unsigned long code_segment_base(struct pt_regs *regs)
2495 * For IA32 we look at the GDT/LDT segment base to convert the
2496 * effective IP to a linear address.
2499 #ifdef CONFIG_X86_32
2501 * If we are in VM86 mode, add the segment offset to convert to a
2504 if (regs->flags & X86_VM_MASK)
2505 return 0x10 * regs->cs;
2507 if (user_mode(regs) && regs->cs != __USER_CS)
2508 return get_segment_base(regs->cs);
2510 if (user_mode(regs) && !user_64bit_mode(regs) &&
2511 regs->cs != __USER32_CS)
2512 return get_segment_base(regs->cs);
2517 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2519 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2520 return perf_guest_cbs->get_guest_ip();
2522 return regs->ip + code_segment_base(regs);
2525 unsigned long perf_misc_flags(struct pt_regs *regs)
2529 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2530 if (perf_guest_cbs->is_user_mode())
2531 misc |= PERF_RECORD_MISC_GUEST_USER;
2533 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2535 if (user_mode(regs))
2536 misc |= PERF_RECORD_MISC_USER;
2538 misc |= PERF_RECORD_MISC_KERNEL;
2541 if (regs->flags & PERF_EFLAGS_EXACT)
2542 misc |= PERF_RECORD_MISC_EXACT_IP;
2547 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2549 cap->version = x86_pmu.version;
2550 cap->num_counters_gp = x86_pmu.num_counters;
2551 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2552 cap->bit_width_gp = x86_pmu.cntval_bits;
2553 cap->bit_width_fixed = x86_pmu.cntval_bits;
2554 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2555 cap->events_mask_len = x86_pmu.events_mask_len;
2557 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);