1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/x86_64/entry.S
5 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
9 * entry.S contains the system-call and fault low-level handling routines.
11 * Some of this is documented in Documentation/arch/x86/entry_64.rst
13 * A note on terminology:
14 * - iret frame: Architecture defined interrupt frame from SS to RIP
15 * at the top of the kernel process stack.
18 * - SYM_FUNC_START/END:Define functions in the symbol table.
19 * - idtentry: Define exception entry points.
21 #include <linux/export.h>
22 #include <linux/linkage.h>
23 #include <asm/segment.h>
24 #include <asm/cache.h>
25 #include <asm/errno.h>
26 #include <asm/asm-offsets.h>
28 #include <asm/unistd.h>
29 #include <asm/thread_info.h>
30 #include <asm/hw_irq.h>
31 #include <asm/page_types.h>
32 #include <asm/irqflags.h>
33 #include <asm/paravirt.h>
34 #include <asm/percpu.h>
37 #include <asm/pgtable_types.h>
38 #include <asm/frame.h>
39 #include <asm/trapnr.h>
40 #include <asm/nospec-branch.h>
41 #include <asm/fsgsbase.h>
42 #include <linux/err.h>
47 .section .entry.text, "ax"
50 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
52 * This is the only entry point used for 64-bit system calls. The
53 * hardware interface is reasonably well designed and the register to
54 * argument mapping Linux uses fits well with the registers that are
55 * available when SYSCALL is used.
57 * SYSCALL instructions can be found inlined in libc implementations as
58 * well as some other programs and libraries. There are also a handful
59 * of SYSCALL instructions in the vDSO used, for example, as a
60 * clock_gettimeofday fallback.
62 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
63 * then loads new ss, cs, and rip from previously programmed MSRs.
64 * rflags gets masked by a value from another MSR (so CLD and CLAC
65 * are not needed). SYSCALL does not save anything on the stack
66 * and does not change rsp.
69 * rax system call number
71 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI)
75 * r10 arg3 (needs to be moved to rcx to conform to C ABI)
78 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
80 * Only called from user space.
82 * When user can change pt_regs->foo always force IRET. That is because
83 * it deals with uncanonical addresses better. SYSRET has trouble
84 * with them due to bugs in both AMD and Intel CPUs.
87 SYM_CODE_START(entry_SYSCALL_64)
92 /* tss.sp2 is scratch space. */
93 movq %rsp, PER_CPU_VAR(cpu_tss_rw + TSS_sp2)
94 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
95 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rsp
97 SYM_INNER_LABEL(entry_SYSCALL_64_safe_stack, SYM_L_GLOBAL)
100 /* Construct struct pt_regs on stack */
101 pushq $__USER_DS /* pt_regs->ss */
102 pushq PER_CPU_VAR(cpu_tss_rw + TSS_sp2) /* pt_regs->sp */
103 pushq %r11 /* pt_regs->flags */
104 pushq $__USER_CS /* pt_regs->cs */
105 pushq %rcx /* pt_regs->ip */
106 SYM_INNER_LABEL(entry_SYSCALL_64_after_hwframe, SYM_L_GLOBAL)
107 pushq %rax /* pt_regs->orig_ax */
109 PUSH_AND_CLEAR_REGS rax=$-ENOSYS
113 /* Sign extend the lower 32bit as syscall numbers are treated as int */
116 /* clobbers %rax, make sure it is after saving the syscall nr */
121 call do_syscall_64 /* returns with IRQs disabled */
124 * Try to use SYSRET instead of IRET if we're returning to
125 * a completely clean 64-bit userspace context. If we're not,
126 * go to the slow exit path.
127 * In the Xen PV case we must use iret anyway.
130 ALTERNATIVE "testb %al, %al; jz swapgs_restore_regs_and_return_to_usermode", \
131 "jmp swapgs_restore_regs_and_return_to_usermode", X86_FEATURE_XENPV
134 * We win! This label is here just for ease of understanding
135 * perf profiles. Nothing jumps here.
137 syscall_return_via_sysret:
142 * Now all regs are restored except RSP and RDI.
143 * Save old stack pointer and switch to trampoline stack.
146 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
147 UNWIND_HINT_END_OF_STACK
149 pushq RSP-RDI(%rdi) /* RSP */
150 pushq (%rdi) /* RDI */
153 * We are on the trampoline stack. All regs except RDI are live.
154 * We can do future final exit work right here.
156 STACKLEAK_ERASE_NOCLOBBER
158 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
162 SYM_INNER_LABEL(entry_SYSRETQ_unsafe_stack, SYM_L_GLOBAL)
167 SYM_INNER_LABEL(entry_SYSRETQ_end, SYM_L_GLOBAL)
170 SYM_CODE_END(entry_SYSCALL_64)
176 .pushsection .text, "ax"
177 SYM_FUNC_START(__switch_to_asm)
179 * Save callee-saved registers
180 * This must match the order in inactive_task_frame
190 movq %rsp, TASK_threadsp(%rdi)
191 movq TASK_threadsp(%rsi), %rsp
193 #ifdef CONFIG_STACKPROTECTOR
194 movq TASK_stack_canary(%rsi), %rbx
195 movq %rbx, PER_CPU_VAR(fixed_percpu_data + FIXED_stack_canary)
199 * When switching from a shallower to a deeper call stack
200 * the RSB may either underflow or use entries populated
201 * with userspace addresses. On CPUs where those concerns
202 * exist, overwrite the RSB with entries which capture
203 * speculative execution to prevent attack.
205 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
207 /* restore callee-saved registers */
216 SYM_FUNC_END(__switch_to_asm)
220 * A newly forked process directly context switches into this address.
222 * rax: prev task we switched from
223 * rbx: kernel thread func (NULL for user thread)
224 * r12: kernel thread arg
226 .pushsection .text, "ax"
227 SYM_CODE_START(ret_from_fork_asm)
229 * This is the start of the kernel stack; even through there's a
230 * register set at the top, the regset isn't necessarily coherent
231 * (consider kthreads) and one cannot unwind further.
233 * This ensures stack unwinds of kernel threads terminate in a known
236 UNWIND_HINT_END_OF_STACK
237 ANNOTATE_NOENDBR // copy_thread
240 movq %rax, %rdi /* prev */
241 movq %rsp, %rsi /* regs */
242 movq %rbx, %rdx /* fn */
243 movq %r12, %rcx /* fn_arg */
247 * Set the stack state to what is expected for the target function
248 * -- at this point the register set should be a valid user set
249 * and unwind should work normally.
253 #ifdef CONFIG_X86_FRED
254 ALTERNATIVE "jmp swapgs_restore_regs_and_return_to_usermode", \
255 "jmp asm_fred_exit_user", X86_FEATURE_FRED
257 jmp swapgs_restore_regs_and_return_to_usermode
259 SYM_CODE_END(ret_from_fork_asm)
262 .macro DEBUG_ENTRY_ASSERT_IRQS_OFF
263 #ifdef CONFIG_DEBUG_ENTRY
266 testl $X86_EFLAGS_IF, %eax
274 SYM_CODE_START(xen_error_entry)
277 PUSH_AND_CLEAR_REGS save_ret=1
278 ENCODE_FRAME_POINTER 8
279 UNTRAIN_RET_FROM_CALL
281 SYM_CODE_END(xen_error_entry)
284 * idtentry_body - Macro to emit code calling the C function
285 * @cfunc: C function to be called
286 * @has_error_code: Hardware pushed error code on stack
288 .macro idtentry_body cfunc has_error_code:req
291 * Call error_entry() and switch to the task stack if from userspace.
293 * When in XENPV, it is already in the task stack, and it can't fault
294 * for native_iret() nor native_load_gs_index() since XENPV uses its
295 * own pvops for IRET and load_gs_index(). And it doesn't need to
296 * switch the CR3. So it can skip invoking error_entry().
298 ALTERNATIVE "call error_entry; movq %rax, %rsp", \
299 "call xen_error_entry", X86_FEATURE_XENPV
304 movq %rsp, %rdi /* pt_regs pointer into 1st argument*/
306 .if \has_error_code == 1
307 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/
308 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
313 /* For some configurations \cfunc ends up being a noreturn. */
320 * idtentry - Macro to generate entry stubs for simple IDT entries
321 * @vector: Vector number
322 * @asmsym: ASM symbol for the entry point
323 * @cfunc: C function to be called
324 * @has_error_code: Hardware pushed error code on stack
326 * The macro emits code to set up the kernel context for straight forward
327 * and simple IDT entries. No IST stack, no paranoid entry checks.
329 .macro idtentry vector asmsym cfunc has_error_code:req
330 SYM_CODE_START(\asmsym)
332 .if \vector == X86_TRAP_BP
333 /* #BP advances %rip to the next instruction */
334 UNWIND_HINT_IRET_ENTRY offset=\has_error_code*8 signal=0
336 UNWIND_HINT_IRET_ENTRY offset=\has_error_code*8
343 .if \has_error_code == 0
344 pushq $-1 /* ORIG_RAX: no syscall to restart */
347 .if \vector == X86_TRAP_BP
349 * If coming from kernel space, create a 6-word gap to allow the
350 * int3 handler to emulate a call instruction.
352 testb $3, CS-ORIG_RAX(%rsp)
353 jnz .Lfrom_usermode_no_gap_\@
357 UNWIND_HINT_IRET_REGS offset=8
358 .Lfrom_usermode_no_gap_\@:
361 idtentry_body \cfunc \has_error_code
363 _ASM_NOKPROBE(\asmsym)
364 SYM_CODE_END(\asmsym)
368 * Interrupt entry/exit.
370 + The interrupt stubs push (vector) onto the stack, which is the error_code
371 * position of idtentry exceptions, and jump to one of the two idtentry points
374 * common_interrupt is a hotpath, align it to a cache line
376 .macro idtentry_irq vector cfunc
377 .p2align CONFIG_X86_L1_CACHE_SHIFT
378 idtentry \vector asm_\cfunc \cfunc has_error_code=1
382 * idtentry_mce_db - Macro to generate entry stubs for #MC and #DB
383 * @vector: Vector number
384 * @asmsym: ASM symbol for the entry point
385 * @cfunc: C function to be called
387 * The macro emits code to set up the kernel context for #MC and #DB
389 * If the entry comes from user space it uses the normal entry path
390 * including the return to user space work and preemption checks on
393 * If hits in kernel mode then it needs to go through the paranoid
394 * entry as the exception can hit any random state. No preemption
395 * check on exit to keep the paranoid path simple.
397 .macro idtentry_mce_db vector asmsym cfunc
398 SYM_CODE_START(\asmsym)
399 UNWIND_HINT_IRET_ENTRY
404 pushq $-1 /* ORIG_RAX: no syscall to restart */
407 * If the entry is from userspace, switch stacks and treat it as
410 testb $3, CS-ORIG_RAX(%rsp)
411 jnz .Lfrom_usermode_switch_stack_\@
413 /* paranoid_entry returns GS information for paranoid_exit in EBX. */
418 movq %rsp, %rdi /* pt_regs pointer */
424 /* Switch to the regular task stack and use the noist entry point */
425 .Lfrom_usermode_switch_stack_\@:
426 idtentry_body noist_\cfunc, has_error_code=0
428 _ASM_NOKPROBE(\asmsym)
429 SYM_CODE_END(\asmsym)
432 #ifdef CONFIG_AMD_MEM_ENCRYPT
434 * idtentry_vc - Macro to generate entry stub for #VC
435 * @vector: Vector number
436 * @asmsym: ASM symbol for the entry point
437 * @cfunc: C function to be called
439 * The macro emits code to set up the kernel context for #VC. The #VC handler
440 * runs on an IST stack and needs to be able to cause nested #VC exceptions.
442 * To make this work the #VC entry code tries its best to pretend it doesn't use
443 * an IST stack by switching to the task stack if coming from user-space (which
444 * includes early SYSCALL entry path) or back to the stack in the IRET frame if
445 * entered from kernel-mode.
447 * If entered from kernel-mode the return stack is validated first, and if it is
448 * not safe to use (e.g. because it points to the entry stack) the #VC handler
449 * will switch to a fall-back stack (VC2) and call a special handler function.
451 * The macro is only used for one vector, but it is planned to be extended in
452 * the future for the #HV exception.
454 .macro idtentry_vc vector asmsym cfunc
455 SYM_CODE_START(\asmsym)
456 UNWIND_HINT_IRET_ENTRY
462 * If the entry is from userspace, switch stacks and treat it as
465 testb $3, CS-ORIG_RAX(%rsp)
466 jnz .Lfrom_usermode_switch_stack_\@
469 * paranoid_entry returns SWAPGS flag for paranoid_exit in EBX.
470 * EBX == 0 -> SWAPGS, EBX == 1 -> no SWAPGS
477 * Switch off the IST stack to make it free for nested exceptions. The
478 * vc_switch_off_ist() function will switch back to the interrupted
479 * stack if it is safe to do so. If not it switches to the VC fall-back
482 movq %rsp, %rdi /* pt_regs pointer */
483 call vc_switch_off_ist
484 movq %rax, %rsp /* Switch to new stack */
490 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/
491 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
493 movq %rsp, %rdi /* pt_regs pointer */
498 * No need to switch back to the IST stack. The current stack is either
499 * identical to the stack in the IRET frame or the VC fall-back stack,
500 * so it is definitely mapped even with PTI enabled.
504 /* Switch to the regular task stack */
505 .Lfrom_usermode_switch_stack_\@:
506 idtentry_body user_\cfunc, has_error_code=1
508 _ASM_NOKPROBE(\asmsym)
509 SYM_CODE_END(\asmsym)
514 * Double fault entry. Straight paranoid. No checks from which context
515 * this comes because for the espfix induced #DF this would do the wrong
518 .macro idtentry_df vector asmsym cfunc
519 SYM_CODE_START(\asmsym)
520 UNWIND_HINT_IRET_ENTRY offset=8
525 /* paranoid_entry returns GS information for paranoid_exit in EBX. */
529 movq %rsp, %rdi /* pt_regs pointer into first argument */
530 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/
531 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
534 /* For some configurations \cfunc ends up being a noreturn. */
539 _ASM_NOKPROBE(\asmsym)
540 SYM_CODE_END(\asmsym)
544 * Include the defines which emit the idt entries which are shared
545 * shared between 32 and 64 bit and emit the __irqentry_text_* markers
546 * so the stacktrace boundary checks work.
549 .globl __irqentry_text_start
550 __irqentry_text_start:
552 #include <asm/idtentry.h>
555 .globl __irqentry_text_end
559 SYM_CODE_START_LOCAL(common_interrupt_return)
560 SYM_INNER_LABEL(swapgs_restore_regs_and_return_to_usermode, SYM_L_GLOBAL)
563 ALTERNATIVE "", "jmp xenpv_restore_regs_and_return_to_usermode", X86_FEATURE_XENPV
565 #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
566 ALTERNATIVE "", "jmp .Lpti_restore_regs_and_return_to_usermode", X86_FEATURE_PTI
571 add $8, %rsp /* orig_ax */
572 UNWIND_HINT_IRET_REGS
577 /* Assert that the IRET frame indicates user mode. */
582 #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
583 .Lpti_restore_regs_and_return_to_usermode:
587 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS.
588 * Save old stack pointer and switch to trampoline stack.
591 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
592 UNWIND_HINT_END_OF_STACK
594 /* Copy the IRET frame to the trampoline stack. */
595 pushq 6*8(%rdi) /* SS */
596 pushq 5*8(%rdi) /* RSP */
597 pushq 4*8(%rdi) /* EFLAGS */
598 pushq 3*8(%rdi) /* CS */
599 pushq 2*8(%rdi) /* RIP */
601 /* Push user RDI on the trampoline stack. */
605 * We are on the trampoline stack. All regs except RDI are live.
606 * We can do future final exit work right here.
608 STACKLEAK_ERASE_NOCLOBBER
611 SWITCH_TO_USER_CR3 scratch_reg=%rdi scratch_reg2=%rax
616 jmp .Lswapgs_and_iret
619 SYM_INNER_LABEL(restore_regs_and_return_to_kernel, SYM_L_GLOBAL)
620 #ifdef CONFIG_DEBUG_ENTRY
621 /* Assert that pt_regs indicates kernel mode. */
628 addq $8, %rsp /* skip regs->orig_ax */
630 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
631 * when returning from IPI handler.
634 SYM_INNER_LABEL(early_xen_iret_patch, SYM_L_GLOBAL)
637 .long .Lnative_iret - (. + 4)
641 UNWIND_HINT_IRET_REGS
643 * Are we returning to a stack segment from the LDT? Note: in
644 * 64-bit mode SS:RSP on the exception stack is always valid.
646 #ifdef CONFIG_X86_ESPFIX64
647 testb $4, (SS-RIP)(%rsp)
648 jnz native_irq_return_ldt
651 SYM_INNER_LABEL(native_irq_return_iret, SYM_L_GLOBAL)
652 ANNOTATE_NOENDBR // exc_double_fault
654 * This may fault. Non-paranoid faults on return to userspace are
655 * handled by fixup_bad_iret. These include #SS, #GP, and #NP.
656 * Double-faults due to espfix64 are handled in exc_double_fault.
657 * Other faults here are fatal.
661 #ifdef CONFIG_X86_ESPFIX64
662 native_irq_return_ldt:
664 * We are running with user GSBASE. All GPRs contain their user
665 * values. We have a percpu ESPFIX stack that is eight slots
666 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom
667 * of the ESPFIX stack.
669 * We clobber RAX and RDI in this code. We stash RDI on the
670 * normal stack and RAX on the ESPFIX stack.
672 * The ESPFIX stack layout we set up looks like this:
674 * --- top of ESPFIX stack ---
679 * RIP <-- RSP points here when we're done
680 * RAX <-- espfix_waddr points here
681 * --- bottom of ESPFIX stack ---
684 pushq %rdi /* Stash user RDI */
685 swapgs /* to kernel GS */
686 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */
688 movq PER_CPU_VAR(espfix_waddr), %rdi
689 movq %rax, (0*8)(%rdi) /* user RAX */
690 movq (1*8)(%rsp), %rax /* user RIP */
691 movq %rax, (1*8)(%rdi)
692 movq (2*8)(%rsp), %rax /* user CS */
693 movq %rax, (2*8)(%rdi)
694 movq (3*8)(%rsp), %rax /* user RFLAGS */
695 movq %rax, (3*8)(%rdi)
696 movq (5*8)(%rsp), %rax /* user SS */
697 movq %rax, (5*8)(%rdi)
698 movq (4*8)(%rsp), %rax /* user RSP */
699 movq %rax, (4*8)(%rdi)
700 /* Now RAX == RSP. */
702 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */
705 * espfix_stack[31:16] == 0. The page tables are set up such that
706 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of
707 * espfix_waddr for any X. That is, there are 65536 RO aliases of
708 * the same page. Set up RSP so that RSP[31:16] contains the
709 * respective 16 bits of the /userspace/ RSP and RSP nonetheless
710 * still points to an RO alias of the ESPFIX stack.
712 orq PER_CPU_VAR(espfix_stack), %rax
714 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
715 swapgs /* to user GS */
716 popq %rdi /* Restore user RDI */
719 UNWIND_HINT_IRET_REGS offset=8
722 * At this point, we cannot write to the stack any more, but we can
725 popq %rax /* Restore user RAX */
730 * RSP now points to an ordinary IRET frame, except that the page
731 * is read-only and RSP[31:16] are preloaded with the userspace
732 * values. We can now IRET back to userspace.
734 jmp native_irq_return_iret
736 SYM_CODE_END(common_interrupt_return)
737 _ASM_NOKPROBE(common_interrupt_return)
740 * Reload gs selector with exception handling
743 * Is in entry.text as it shouldn't be instrumented.
745 SYM_FUNC_START(asm_load_gs_index)
749 ANNOTATE_NOENDBR // error_entry
751 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
756 /* running with kernelgs */
758 swapgs /* switch back to user gs */
760 /* This can't be a string because the preprocessor needs to see it. */
761 movl $__USER_DS, %eax
764 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
769 _ASM_EXTABLE(.Lgs_change, .Lbad_gs)
771 SYM_FUNC_END(asm_load_gs_index)
772 EXPORT_SYMBOL(asm_load_gs_index)
776 * A note on the "critical region" in our callback handler.
777 * We want to avoid stacking callback handlers due to events occurring
778 * during handling of the last event. To do this, we keep events disabled
779 * until we've done all processing. HOWEVER, we must enable events before
780 * popping the stack frame (can't be done atomically) and so it would still
781 * be possible to get enough handler activations to overflow the stack.
782 * Although unlikely, bugs of that kind are hard to track down, so we'd
783 * like to avoid the possibility.
784 * So, on entry to the handler we detect whether we interrupted an
785 * existing activation in its critical region -- if so, we pop the current
786 * activation and restart the handler using the previous one.
788 * C calling convention: exc_xen_hypervisor_callback(struct *pt_regs)
791 SYM_CODE_START_LOCAL_NOALIGN(exc_xen_hypervisor_callback)
794 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
795 * see the correct pointer to the pt_regs
798 movq %rdi, %rsp /* we don't return, adjust the stack frame */
801 call xen_pv_evtchn_do_upcall
804 SYM_CODE_END(exc_xen_hypervisor_callback)
807 * Hypervisor uses this for application faults while it executes.
808 * We get here for two reasons:
809 * 1. Fault while reloading DS, ES, FS or GS
810 * 2. Fault while executing IRET
811 * Category 1 we do not need to fix up as Xen has already reloaded all segment
812 * registers that could be reloaded and zeroed the others.
813 * Category 2 we fix up by killing the current process. We cannot use the
814 * normal Linux return path in this case because if we use the IRET hypercall
815 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
816 * We distinguish between categories by comparing each saved segment register
817 * with its current contents: any discrepancy means we in category 1.
820 SYM_CODE_START_NOALIGN(xen_failsafe_callback)
821 UNWIND_HINT_UNDEFINED
835 /* All segments match their saved values => Category 2 (Bad IRET). */
840 UNWIND_HINT_IRET_REGS offset=8
841 jmp asm_exc_general_protection
842 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
846 UNWIND_HINT_IRET_REGS
847 pushq $-1 /* orig_ax = -1 => not a system call */
851 SYM_CODE_END(xen_failsafe_callback)
852 #endif /* CONFIG_XEN_PV */
855 * Save all registers in pt_regs. Return GSBASE related information
856 * in EBX depending on the availability of the FSGSBASE instructions:
859 * N 0 -> SWAPGS on exit
860 * 1 -> no SWAPGS on exit
862 * Y GSBASE value at entry, must be restored in paranoid_exit
865 * R15 - old SPEC_CTRL
867 SYM_CODE_START(paranoid_entry)
870 PUSH_AND_CLEAR_REGS save_ret=1
871 ENCODE_FRAME_POINTER 8
874 * Always stash CR3 in %r14. This value will be restored,
875 * verbatim, at exit. Needed if paranoid_entry interrupted
876 * another entry that already switched to the user CR3 value
877 * but has not yet returned to userspace.
879 * This is also why CS (stashed in the "iret frame" by the
880 * hardware at entry) can not be used: this may be a return
881 * to kernel code, but with a user CR3 value.
883 * Switching CR3 does not depend on kernel GSBASE so it can
884 * be done before switching to the kernel GSBASE. This is
885 * required for FSGSBASE because the kernel GSBASE has to
886 * be retrieved from a kernel internal table.
888 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
891 * Handling GSBASE depends on the availability of FSGSBASE.
893 * Without FSGSBASE the kernel enforces that negative GSBASE
894 * values indicate kernel GSBASE. With FSGSBASE no assumptions
895 * can be made about the GSBASE value when entering from user
898 ALTERNATIVE "jmp .Lparanoid_entry_checkgs", "", X86_FEATURE_FSGSBASE
901 * Read the current GSBASE and store it in %rbx unconditionally,
902 * retrieve and set the current CPUs kernel GSBASE. The stored value
903 * has to be restored in paranoid_exit unconditionally.
905 * The unconditional write to GS base below ensures that no subsequent
906 * loads based on a mispredicted GS base can happen, therefore no LFENCE
909 SAVE_AND_SET_GSBASE scratch_reg=%rax save_reg=%rbx
910 jmp .Lparanoid_gsbase_done
912 .Lparanoid_entry_checkgs:
913 /* EBX = 1 -> kernel GSBASE active, no restore required */
917 * The kernel-enforced convention is a negative GSBASE indicates
918 * a kernel value. No SWAPGS needed on entry and exit.
920 movl $MSR_GS_BASE, %ecx
923 js .Lparanoid_kernel_gsbase
925 /* EBX = 0 -> SWAPGS required on exit */
928 .Lparanoid_kernel_gsbase:
929 FENCE_SWAPGS_KERNEL_ENTRY
930 .Lparanoid_gsbase_done:
933 * Once we have CR3 and %GS setup save and set SPEC_CTRL. Just like
934 * CR3 above, keep the old value in a callee saved register.
936 IBRS_ENTER save_reg=%r15
937 UNTRAIN_RET_FROM_CALL
940 SYM_CODE_END(paranoid_entry)
943 * "Paranoid" exit path from exception stack. This is invoked
944 * only on return from non-NMI IST interrupts that came
947 * We may be returning to very strange contexts (e.g. very early
948 * in syscall entry), so checking for preemption here would
949 * be complicated. Fortunately, there's no good reason to try
950 * to handle preemption here.
952 * R/EBX contains the GSBASE related information depending on the
953 * availability of the FSGSBASE instructions:
956 * N 0 -> SWAPGS on exit
957 * 1 -> no SWAPGS on exit
959 * Y User space GSBASE, must be restored unconditionally
962 * R15 - old SPEC_CTRL
964 SYM_CODE_START_LOCAL(paranoid_exit)
968 * Must restore IBRS state before both CR3 and %GS since we need access
969 * to the per-CPU x86_spec_ctrl_shadow variable.
971 IBRS_EXIT save_reg=%r15
974 * The order of operations is important. PARANOID_RESTORE_CR3 requires
977 * NB to anyone to try to optimize this code: this code does
978 * not execute at all for exceptions from user mode. Those
979 * exceptions go through error_return instead.
981 PARANOID_RESTORE_CR3 scratch_reg=%rax save_reg=%r14
983 /* Handle the three GSBASE cases */
984 ALTERNATIVE "jmp .Lparanoid_exit_checkgs", "", X86_FEATURE_FSGSBASE
986 /* With FSGSBASE enabled, unconditionally restore GSBASE */
988 jmp restore_regs_and_return_to_kernel
990 .Lparanoid_exit_checkgs:
991 /* On non-FSGSBASE systems, conditionally do SWAPGS */
993 jnz restore_regs_and_return_to_kernel
995 /* We are returning to a context with user GSBASE */
997 jmp restore_regs_and_return_to_kernel
998 SYM_CODE_END(paranoid_exit)
1001 * Switch GS and CR3 if needed.
1003 SYM_CODE_START(error_entry)
1007 PUSH_AND_CLEAR_REGS save_ret=1
1008 ENCODE_FRAME_POINTER 8
1010 testb $3, CS+8(%rsp)
1011 jz .Lerror_kernelspace
1014 * We entered from user mode or we're pretending to have entered
1015 * from user mode due to an IRET fault.
1018 FENCE_SWAPGS_USER_ENTRY
1019 /* We have user CR3. Change to kernel CR3. */
1020 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1022 UNTRAIN_RET_FROM_CALL
1024 leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */
1025 /* Put us onto the real thread stack. */
1029 * There are two places in the kernel that can potentially fault with
1030 * usergs. Handle them here. B stepping K8s sometimes report a
1031 * truncated RIP for IRET exceptions returning to compat mode. Check
1032 * for these here too.
1034 .Lerror_kernelspace:
1035 leaq native_irq_return_iret(%rip), %rcx
1036 cmpq %rcx, RIP+8(%rsp)
1038 movl %ecx, %eax /* zero extend */
1039 cmpq %rax, RIP+8(%rsp)
1041 cmpq $.Lgs_change, RIP+8(%rsp)
1042 jne .Lerror_entry_done_lfence
1045 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up
1046 * gsbase and proceed. We'll fix up the exception and land in
1047 * .Lgs_change's error handler with kernel gsbase.
1052 * Issue an LFENCE to prevent GS speculation, regardless of whether it is a
1053 * kernel or user gsbase.
1055 .Lerror_entry_done_lfence:
1056 FENCE_SWAPGS_KERNEL_ENTRY
1058 leaq 8(%rsp), %rax /* return pt_regs pointer */
1063 /* Fix truncated RIP */
1064 movq %rcx, RIP+8(%rsp)
1069 * We came from an IRET to user mode, so we have user
1070 * gsbase and CR3. Switch to kernel gsbase and CR3:
1073 FENCE_SWAPGS_USER_ENTRY
1074 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1076 UNTRAIN_RET_FROM_CALL
1079 * Pretend that the exception came from user mode: set up pt_regs
1080 * as if we faulted immediately after IRET.
1082 leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */
1086 SYM_CODE_END(error_entry)
1088 SYM_CODE_START_LOCAL(error_return)
1090 DEBUG_ENTRY_ASSERT_IRQS_OFF
1092 jz restore_regs_and_return_to_kernel
1093 jmp swapgs_restore_regs_and_return_to_usermode
1094 SYM_CODE_END(error_return)
1097 * Runs on exception stack. Xen PV does not go through this path at all,
1098 * so we can use real assembly here.
1101 * %r14: Used to save/restore the CR3 of the interrupted context
1102 * when MITIGATION_PAGE_TABLE_ISOLATION is in use. Do not clobber.
1104 SYM_CODE_START(asm_exc_nmi)
1105 UNWIND_HINT_IRET_ENTRY
1109 * We allow breakpoints in NMIs. If a breakpoint occurs, then
1110 * the iretq it performs will take us out of NMI context.
1111 * This means that we can have nested NMIs where the next
1112 * NMI is using the top of the stack of the previous NMI. We
1113 * can't let it execute because the nested NMI will corrupt the
1114 * stack of the previous NMI. NMI handlers are not re-entrant
1117 * To handle this case we do the following:
1118 * Check a special location on the stack that contains a
1119 * variable that is set when NMIs are executing.
1120 * The interrupted task's stack is also checked to see if it
1122 * If the variable is not set and the stack is not the NMI
1124 * o Set the special variable on the stack
1125 * o Copy the interrupt frame into an "outermost" location on the
1127 * o Copy the interrupt frame into an "iret" location on the stack
1128 * o Continue processing the NMI
1129 * If the variable is set or the previous stack is the NMI stack:
1130 * o Modify the "iret" location to jump to the repeat_nmi
1131 * o return back to the first NMI
1133 * Now on exit of the first NMI, we first clear the stack variable
1134 * The NMI stack will tell any nested NMIs at that point that it is
1135 * nested. Then we pop the stack normally with iret, and if there was
1136 * a nested NMI that updated the copy interrupt stack frame, a
1137 * jump will be made to the repeat_nmi code that will handle the second
1140 * However, espfix prevents us from directly returning to userspace
1141 * with a single IRET instruction. Similarly, IRET to user mode
1142 * can fault. We therefore handle NMIs from user space like
1143 * other IST entries.
1149 /* Use %rdx as our temp variable throughout */
1152 testb $3, CS-RIP+8(%rsp)
1153 jz .Lnmi_from_kernel
1156 * NMI from user mode. We need to run on the thread stack, but we
1157 * can't go through the normal entry paths: NMIs are masked, and
1158 * we don't want to enable interrupts, because then we'll end
1159 * up in an awkward situation in which IRQs are on but NMIs
1162 * We also must not push anything to the stack before switching
1163 * stacks lest we corrupt the "NMI executing" variable.
1167 FENCE_SWAPGS_USER_ENTRY
1168 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx
1170 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rsp
1171 UNWIND_HINT_IRET_REGS base=%rdx offset=8
1172 pushq 5*8(%rdx) /* pt_regs->ss */
1173 pushq 4*8(%rdx) /* pt_regs->rsp */
1174 pushq 3*8(%rdx) /* pt_regs->flags */
1175 pushq 2*8(%rdx) /* pt_regs->cs */
1176 pushq 1*8(%rdx) /* pt_regs->rip */
1177 UNWIND_HINT_IRET_REGS
1178 pushq $-1 /* pt_regs->orig_ax */
1179 PUSH_AND_CLEAR_REGS rdx=(%rdx)
1180 ENCODE_FRAME_POINTER
1186 * At this point we no longer need to worry about stack damage
1187 * due to nesting -- we're on the normal thread stack and we're
1188 * done with the NMI stack.
1195 * Return back to user mode. We must *not* do the normal exit
1196 * work, because we don't want to enable interrupts.
1198 jmp swapgs_restore_regs_and_return_to_usermode
1202 * Here's what our stack frame will look like:
1203 * +---------------------------------------------------------+
1205 * | original Return RSP |
1206 * | original RFLAGS |
1209 * +---------------------------------------------------------+
1210 * | temp storage for rdx |
1211 * +---------------------------------------------------------+
1212 * | "NMI executing" variable |
1213 * +---------------------------------------------------------+
1214 * | iret SS } Copied from "outermost" frame |
1215 * | iret Return RSP } on each loop iteration; overwritten |
1216 * | iret RFLAGS } by a nested NMI to force another |
1217 * | iret CS } iteration if needed. |
1219 * +---------------------------------------------------------+
1220 * | outermost SS } initialized in first_nmi; |
1221 * | outermost Return RSP } will not be changed before |
1222 * | outermost RFLAGS } NMI processing is done. |
1223 * | outermost CS } Copied to "iret" frame on each |
1224 * | outermost RIP } iteration. |
1225 * +---------------------------------------------------------+
1227 * +---------------------------------------------------------+
1229 * The "original" frame is used by hardware. Before re-enabling
1230 * NMIs, we need to be done with it, and we need to leave enough
1231 * space for the asm code here.
1233 * We return by executing IRET while RSP points to the "iret" frame.
1234 * That will either return for real or it will loop back into NMI
1237 * The "outermost" frame is copied to the "iret" frame on each
1238 * iteration of the loop, so each iteration starts with the "iret"
1239 * frame pointing to the final return target.
1243 * Determine whether we're a nested NMI.
1245 * If we interrupted kernel code between repeat_nmi and
1246 * end_repeat_nmi, then we are a nested NMI. We must not
1247 * modify the "iret" frame because it's being written by
1248 * the outer NMI. That's okay; the outer NMI handler is
1249 * about to call exc_nmi() anyway, so we can just resume
1253 movq $repeat_nmi, %rdx
1256 movq $end_repeat_nmi, %rdx
1262 * Now check "NMI executing". If it's set, then we're nested.
1263 * This will not detect if we interrupted an outer NMI just
1270 * Now test if the previous stack was an NMI stack. This covers
1271 * the case where we interrupt an outer NMI after it clears
1272 * "NMI executing" but before IRET. We need to be careful, though:
1273 * there is one case in which RSP could point to the NMI stack
1274 * despite there being no NMI active: naughty userspace controls
1275 * RSP at the very beginning of the SYSCALL targets. We can
1276 * pull a fast one on naughty userspace, though: we program
1277 * SYSCALL to mask DF, so userspace cannot cause DF to be set
1278 * if it controls the kernel's RSP. We set DF before we clear
1282 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */
1283 cmpq %rdx, 4*8(%rsp)
1284 /* If the stack pointer is above the NMI stack, this is a normal NMI */
1287 subq $EXCEPTION_STKSZ, %rdx
1288 cmpq %rdx, 4*8(%rsp)
1289 /* If it is below the NMI stack, it is a normal NMI */
1292 /* Ah, it is within the NMI stack. */
1294 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp)
1295 jz first_nmi /* RSP was user controlled. */
1297 /* This is a nested NMI. */
1301 * Modify the "iret" frame to point to repeat_nmi, forcing another
1302 * iteration of NMI handling.
1305 leaq -10*8(%rsp), %rdx
1312 /* Put stack back */
1318 /* We are returning to kernel mode, so this cannot result in a fault. */
1325 /* Make room for "NMI executing". */
1328 /* Leave room for the "iret" frame */
1331 /* Copy the "original" frame to the "outermost" frame */
1335 UNWIND_HINT_IRET_REGS
1337 /* Everything up to here is safe from nested NMIs */
1339 #ifdef CONFIG_DEBUG_ENTRY
1341 * For ease of testing, unmask NMIs right away. Disabled by
1342 * default because IRET is very expensive.
1345 pushq %rsp /* RSP (minus 8 because of the previous push) */
1346 addq $8, (%rsp) /* Fix up RSP */
1348 pushq $__KERNEL_CS /* CS */
1350 iretq /* continues at repeat_nmi below */
1351 UNWIND_HINT_IRET_REGS
1356 ANNOTATE_NOENDBR // this code
1358 * If there was a nested NMI, the first NMI's iret will return
1359 * here. But NMIs are still enabled and we can take another
1360 * nested NMI. The nested NMI checks the interrupted RIP to see
1361 * if it is between repeat_nmi and end_repeat_nmi, and if so
1362 * it will just return, as we are about to repeat an NMI anyway.
1363 * This makes it safe to copy to the stack frame that a nested
1366 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if
1367 * we're repeating an NMI, gsbase has the same value that it had on
1368 * the first iteration. paranoid_entry will load the kernel
1369 * gsbase if needed before we call exc_nmi(). "NMI executing"
1372 movq $1, 10*8(%rsp) /* Set "NMI executing". */
1375 * Copy the "outermost" frame to the "iret" frame. NMIs that nest
1376 * here must not modify the "iret" frame while we're writing to
1377 * it or it will end up containing garbage.
1385 ANNOTATE_NOENDBR // this code
1388 * Everything below this point can be preempted by a nested NMI.
1389 * If this happens, then the inner NMI will change the "iret"
1390 * frame to point back to repeat_nmi.
1392 pushq $-1 /* ORIG_RAX: no syscall to restart */
1395 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit
1396 * as we should not be calling schedule in NMI context.
1397 * Even with normal interrupts enabled. An NMI should not be
1398 * setting NEED_RESCHED or anything that normal interrupts and
1399 * exceptions might do.
1407 /* Always restore stashed SPEC_CTRL value (see paranoid_entry) */
1408 IBRS_EXIT save_reg=%r15
1410 PARANOID_RESTORE_CR3 scratch_reg=%r15 save_reg=%r14
1413 * The above invocation of paranoid_entry stored the GSBASE
1414 * related information in R/EBX depending on the availability
1417 * If FSGSBASE is enabled, restore the saved GSBASE value
1418 * unconditionally, otherwise take the conditional SWAPGS path.
1420 ALTERNATIVE "jmp nmi_no_fsgsbase", "", X86_FEATURE_FSGSBASE
1426 /* EBX == 0 -> invoke SWAPGS */
1437 * Skip orig_ax and the "outermost" frame to point RSP at the "iret"
1438 * at the "iret" frame.
1443 * Clear "NMI executing". Set DF first so that we can easily
1444 * distinguish the remaining code between here and IRET from
1445 * the SYSCALL entry and exit paths.
1447 * We arguably should just inspect RIP instead, but I (Andy) wrote
1448 * this code when I had the misapprehension that Xen PV supported
1449 * NMIs, and Xen PV would break that approach.
1452 movq $0, 5*8(%rsp) /* clear "NMI executing" */
1455 * Skip CLEAR_CPU_BUFFERS here, since it only helps in rare cases like
1456 * NMI in kernel after user state is restored. For an unprivileged user
1457 * these conditions are hard to meet.
1461 * iretq reads the "iret" frame and exits the NMI stack in a
1462 * single instruction. We are returning to kernel mode, so this
1463 * cannot result in a fault. Similarly, we don't need to worry
1464 * about espfix64 on the way back to kernel mode.
1467 SYM_CODE_END(asm_exc_nmi)
1470 * This handles SYSCALL from 32-bit code. There is no way to program
1471 * MSRs to fully disable 32-bit SYSCALL.
1473 SYM_CODE_START(entry_SYSCALL32_ignore)
1474 UNWIND_HINT_END_OF_STACK
1479 SYM_CODE_END(entry_SYSCALL32_ignore)
1481 .pushsection .text, "ax"
1483 SYM_CODE_START_NOALIGN(rewind_stack_and_make_dead)
1485 /* Prevent any naive code from trying to unwind to our caller. */
1488 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rax
1489 leaq -PTREGS_SIZE(%rax), %rsp
1493 SYM_CODE_END(rewind_stack_and_make_dead)
1497 * This sequence executes branches in order to remove user branch information
1498 * from the branch history tracker in the Branch Predictor, therefore removing
1499 * user influence on subsequent BTB lookups.
1501 * It should be used on parts prior to Alder Lake. Newer parts should use the
1502 * BHI_DIS_S hardware control instead. If a pre-Alder Lake part is being
1503 * virtualized on newer hardware the VMM should protect against BHI attacks by
1504 * setting BHI_DIS_S for the guests.
1506 * CALLs/RETs are necessary to prevent Loop Stream Detector(LSD) from engaging
1507 * and not clearing the branch history. The call tree looks like:
1522 * This means that the stack is non-constant and ORC can't unwind it with %rsp
1523 * alone. Therefore we unconditionally set up the frame pointer, which allows
1524 * ORC to unwind properly.
1526 * The alignment is for performance and not for safety, and may be safely
1527 * refactored in the future if needed.
1529 SYM_FUNC_START(clear_bhb_loop)
1533 ANNOTATE_INTRA_FUNCTION_CALL
1537 ANNOTATE_INTRA_FUNCTION_CALL
1552 SYM_FUNC_END(clear_bhb_loop)
1553 EXPORT_SYMBOL_GPL(clear_bhb_loop)
1554 STACK_FRAME_NON_STANDARD(clear_bhb_loop)