1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/x86_64/entry.S
5 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
9 * entry.S contains the system-call and fault low-level handling routines.
11 * Some of this is documented in Documentation/x86/entry_64.txt
13 * A note on terminology:
14 * - iret frame: Architecture defined interrupt frame from SS to RIP
15 * at the top of the kernel process stack.
18 * - ENTRY/END: Define functions in the symbol table.
19 * - TRACE_IRQ_*: Trace hardirq state for lock debugging.
20 * - idtentry: Define exception entry points.
22 #include <linux/linkage.h>
23 #include <asm/segment.h>
24 #include <asm/cache.h>
25 #include <asm/errno.h>
26 #include <asm/asm-offsets.h>
28 #include <asm/unistd.h>
29 #include <asm/thread_info.h>
30 #include <asm/hw_irq.h>
31 #include <asm/page_types.h>
32 #include <asm/irqflags.h>
33 #include <asm/paravirt.h>
34 #include <asm/percpu.h>
37 #include <asm/pgtable_types.h>
38 #include <asm/export.h>
39 #include <asm/frame.h>
40 #include <asm/nospec-branch.h>
41 #include <linux/err.h>
46 .section .entry.text, "ax"
48 #ifdef CONFIG_PARAVIRT
49 ENTRY(native_usergs_sysret64)
53 END(native_usergs_sysret64)
54 #endif /* CONFIG_PARAVIRT */
56 .macro TRACE_IRQS_FLAGS flags:req
57 #ifdef CONFIG_TRACE_IRQFLAGS
58 btl $9, \flags /* interrupts off? */
65 .macro TRACE_IRQS_IRETQ
66 TRACE_IRQS_FLAGS EFLAGS(%rsp)
70 * When dynamic function tracer is enabled it will add a breakpoint
71 * to all locations that it is about to modify, sync CPUs, update
72 * all the code, sync CPUs, then remove the breakpoints. In this time
73 * if lockdep is enabled, it might jump back into the debug handler
74 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF).
76 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to
77 * make sure the stack pointer does not get reset back to the top
78 * of the debug stack, and instead just reuses the current stack.
80 #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS)
82 .macro TRACE_IRQS_OFF_DEBUG
83 call debug_stack_set_zero
85 call debug_stack_reset
88 .macro TRACE_IRQS_ON_DEBUG
89 call debug_stack_set_zero
91 call debug_stack_reset
94 .macro TRACE_IRQS_IRETQ_DEBUG
95 btl $9, EFLAGS(%rsp) /* interrupts off? */
102 # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF
103 # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON
104 # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ
108 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
110 * This is the only entry point used for 64-bit system calls. The
111 * hardware interface is reasonably well designed and the register to
112 * argument mapping Linux uses fits well with the registers that are
113 * available when SYSCALL is used.
115 * SYSCALL instructions can be found inlined in libc implementations as
116 * well as some other programs and libraries. There are also a handful
117 * of SYSCALL instructions in the vDSO used, for example, as a
118 * clock_gettimeofday fallback.
120 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
121 * then loads new ss, cs, and rip from previously programmed MSRs.
122 * rflags gets masked by a value from another MSR (so CLD and CLAC
123 * are not needed). SYSCALL does not save anything on the stack
124 * and does not change rsp.
126 * Registers on entry:
127 * rax system call number
129 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI)
133 * r10 arg3 (needs to be moved to rcx to conform to C ABI)
136 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
138 * Only called from user space.
140 * When user can change pt_regs->foo always force IRET. That is because
141 * it deals with uncanonical addresses better. SYSRET has trouble
142 * with them due to bugs in both AMD and Intel CPUs.
145 .pushsection .entry_trampoline, "ax"
148 * The code in here gets remapped into cpu_entry_area's trampoline. This means
149 * that the assembler and linker have the wrong idea as to where this code
150 * lives (and, in fact, it's mapped more than once, so it's not even at a
151 * fixed address). So we can't reference any symbols outside the entry
152 * trampoline and expect it to work.
154 * Instead, we carefully abuse %rip-relative addressing.
155 * _entry_trampoline(%rip) refers to the start of the remapped) entry
156 * trampoline. We can thus find cpu_entry_area with this macro:
159 #define CPU_ENTRY_AREA \
160 _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip)
162 /* The top word of the SYSENTER stack is hot and is usable as scratch space. */
163 #define RSP_SCRATCH CPU_ENTRY_AREA_entry_stack + \
164 SIZEOF_entry_stack - 8 + CPU_ENTRY_AREA
166 ENTRY(entry_SYSCALL_64_trampoline)
170 /* Stash the user RSP. */
171 movq %rsp, RSP_SCRATCH
173 /* Note: using %rsp as a scratch reg. */
174 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
176 /* Load the top of the task stack into RSP */
177 movq CPU_ENTRY_AREA_tss + TSS_sp1 + CPU_ENTRY_AREA, %rsp
179 /* Start building the simulated IRET frame. */
180 pushq $__USER_DS /* pt_regs->ss */
181 pushq RSP_SCRATCH /* pt_regs->sp */
182 pushq %r11 /* pt_regs->flags */
183 pushq $__USER_CS /* pt_regs->cs */
184 pushq %rcx /* pt_regs->ip */
187 * x86 lacks a near absolute jump, and we can't jump to the real
188 * entry text with a relative jump. We could push the target
189 * address and then use retq, but this destroys the pipeline on
190 * many CPUs (wasting over 20 cycles on Sandy Bridge). Instead,
191 * spill RDI and restore it in a second-stage trampoline.
194 movq $entry_SYSCALL_64_stage2, %rdi
196 END(entry_SYSCALL_64_trampoline)
200 ENTRY(entry_SYSCALL_64_stage2)
203 jmp entry_SYSCALL_64_after_hwframe
204 END(entry_SYSCALL_64_stage2)
206 ENTRY(entry_SYSCALL_64)
209 * Interrupts are off on entry.
210 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON,
211 * it is too small to ever cause noticeable irq latency.
216 * This path is only taken when PAGE_TABLE_ISOLATION is disabled so it
217 * is not required to switch CR3.
219 movq %rsp, PER_CPU_VAR(rsp_scratch)
220 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
222 /* Construct struct pt_regs on stack */
223 pushq $__USER_DS /* pt_regs->ss */
224 pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */
225 pushq %r11 /* pt_regs->flags */
226 pushq $__USER_CS /* pt_regs->cs */
227 pushq %rcx /* pt_regs->ip */
228 GLOBAL(entry_SYSCALL_64_after_hwframe)
229 pushq %rax /* pt_regs->orig_ax */
231 PUSH_AND_CLEAR_REGS rax=$-ENOSYS
238 call do_syscall_64 /* returns with IRQs disabled */
240 TRACE_IRQS_IRETQ /* we're about to change IF */
243 * Try to use SYSRET instead of IRET if we're returning to
244 * a completely clean 64-bit userspace context. If we're not,
245 * go to the slow exit path.
250 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */
251 jne swapgs_restore_regs_and_return_to_usermode
254 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP
255 * in kernel space. This essentially lets the user take over
256 * the kernel, since userspace controls RSP.
258 * If width of "canonical tail" ever becomes variable, this will need
259 * to be updated to remain correct on both old and new CPUs.
261 * Change top bits to match most significant bit (47th or 56th bit
262 * depending on paging mode) in the address.
264 #ifdef CONFIG_X86_5LEVEL
265 ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \
266 "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57
268 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
269 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
272 /* If this changed %rcx, it was not canonical */
274 jne swapgs_restore_regs_and_return_to_usermode
276 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
277 jne swapgs_restore_regs_and_return_to_usermode
280 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */
281 jne swapgs_restore_regs_and_return_to_usermode
284 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot
285 * restore RF properly. If the slowpath sets it for whatever reason, we
286 * need to restore it correctly.
288 * SYSRET can restore TF, but unlike IRET, restoring TF results in a
289 * trap from userspace immediately after SYSRET. This would cause an
290 * infinite loop whenever #DB happens with register state that satisfies
291 * the opportunistic SYSRET conditions. For example, single-stepping
294 * movq $stuck_here, %rcx
299 * would never get past 'stuck_here'.
301 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11
302 jnz swapgs_restore_regs_and_return_to_usermode
304 /* nothing to check for RSP */
306 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */
307 jne swapgs_restore_regs_and_return_to_usermode
310 * We win! This label is here just for ease of understanding
311 * perf profiles. Nothing jumps here.
313 syscall_return_via_sysret:
314 /* rcx and r11 are already restored (see code above) */
316 POP_REGS pop_rdi=0 skip_r11rcx=1
319 * Now all regs are restored except RSP and RDI.
320 * Save old stack pointer and switch to trampoline stack.
323 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
325 pushq RSP-RDI(%rdi) /* RSP */
326 pushq (%rdi) /* RDI */
329 * We are on the trampoline stack. All regs except RDI are live.
330 * We can do future final exit work right here.
332 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
337 END(entry_SYSCALL_64)
343 ENTRY(__switch_to_asm)
346 * Save callee-saved registers
347 * This must match the order in inactive_task_frame
357 movq %rsp, TASK_threadsp(%rdi)
358 movq TASK_threadsp(%rsi), %rsp
360 #ifdef CONFIG_STACKPROTECTOR
361 movq TASK_stack_canary(%rsi), %rbx
362 movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset
365 #ifdef CONFIG_RETPOLINE
367 * When switching from a shallower to a deeper call stack
368 * the RSB may either underflow or use entries populated
369 * with userspace addresses. On CPUs where those concerns
370 * exist, overwrite the RSB with entries which capture
371 * speculative execution to prevent attack.
373 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
376 /* restore callee-saved registers */
388 * A newly forked process directly context switches into this address.
390 * rax: prev task we switched from
391 * rbx: kernel thread func (NULL for user thread)
392 * r12: kernel thread arg
397 call schedule_tail /* rdi: 'prev' task parameter */
399 testq %rbx, %rbx /* from kernel_thread? */
400 jnz 1f /* kernel threads are uncommon */
405 call syscall_return_slowpath /* returns with IRQs disabled */
406 TRACE_IRQS_ON /* user mode is traced as IRQS on */
407 jmp swapgs_restore_regs_and_return_to_usermode
415 * A kernel thread is allowed to return here after successfully
416 * calling do_execve(). Exit to userspace to complete the execve()
424 * Build the entry stubs with some assembler magic.
425 * We pack 1 stub into every 8-byte block.
428 ENTRY(irq_entries_start)
429 vector=FIRST_EXTERNAL_VECTOR
430 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
431 UNWIND_HINT_IRET_REGS
432 pushq $(~vector+0x80) /* Note: always in signed byte range */
437 END(irq_entries_start)
439 .macro DEBUG_ENTRY_ASSERT_IRQS_OFF
440 #ifdef CONFIG_DEBUG_ENTRY
443 testl $X86_EFLAGS_IF, %eax
452 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers
453 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone.
454 * Requires kernel GSBASE.
456 * The invariant is that, if irq_count != -1, then the IRQ stack is in use.
458 .macro ENTER_IRQ_STACK regs=1 old_rsp save_ret=0
459 DEBUG_ENTRY_ASSERT_IRQS_OFF
463 * If save_ret is set, the original stack contains one additional
464 * entry -- the return address. Therefore, move the address one
465 * entry below %rsp to \old_rsp.
467 leaq 8(%rsp), \old_rsp
473 UNWIND_HINT_REGS base=\old_rsp
476 incl PER_CPU_VAR(irq_count)
477 jnz .Lirq_stack_push_old_rsp_\@
480 * Right now, if we just incremented irq_count to zero, we've
481 * claimed the IRQ stack but we haven't switched to it yet.
483 * If anything is added that can interrupt us here without using IST,
484 * it must be *extremely* careful to limit its stack usage. This
485 * could include kprobes and a hypothetical future IST-less #DB
488 * The OOPS unwinder relies on the word at the top of the IRQ
489 * stack linking back to the previous RSP for the entire time we're
490 * on the IRQ stack. For this to work reliably, we need to write
491 * it before we actually move ourselves to the IRQ stack.
494 movq \old_rsp, PER_CPU_VAR(irq_stack_union + IRQ_STACK_SIZE - 8)
495 movq PER_CPU_VAR(irq_stack_ptr), %rsp
497 #ifdef CONFIG_DEBUG_ENTRY
499 * If the first movq above becomes wrong due to IRQ stack layout
500 * changes, the only way we'll notice is if we try to unwind right
501 * here. Assert that we set up the stack right to catch this type
504 cmpq -8(%rsp), \old_rsp
505 je .Lirq_stack_okay\@
510 .Lirq_stack_push_old_rsp_\@:
514 UNWIND_HINT_REGS indirect=1
519 * Push the return address to the stack. This return address can
520 * be found at the "real" original RSP, which was offset by 8 at
521 * the beginning of this macro.
528 * Undoes ENTER_IRQ_STACK.
530 .macro LEAVE_IRQ_STACK regs=1
531 DEBUG_ENTRY_ASSERT_IRQS_OFF
532 /* We need to be off the IRQ stack before decrementing irq_count. */
540 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming
541 * the irq stack but we're not on it.
544 decl PER_CPU_VAR(irq_count)
548 * Interrupt entry helper function.
550 * Entry runs with interrupts off. Stack layout at entry:
551 * +----------------------------------------------------+
557 * +----------------------------------------------------+
558 * | regs->orig_ax = ~(interrupt number) |
559 * +----------------------------------------------------+
561 * +----------------------------------------------------+
563 ENTRY(interrupt_entry)
568 testb $3, CS-ORIG_RAX+8(%rsp)
573 * Switch to the thread stack. The IRET frame and orig_ax are
574 * on the stack, as well as the return address. RDI..R12 are
575 * not (yet) on the stack and space has not (yet) been
576 * allocated for them.
580 /* Need to switch before accessing the thread stack. */
581 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi
583 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
586 * We have RDI, return address, and orig_ax on the stack on
587 * top of the IRET frame. That means offset=24
589 UNWIND_HINT_IRET_REGS base=%rdi offset=24
591 pushq 7*8(%rdi) /* regs->ss */
592 pushq 6*8(%rdi) /* regs->rsp */
593 pushq 5*8(%rdi) /* regs->eflags */
594 pushq 4*8(%rdi) /* regs->cs */
595 pushq 3*8(%rdi) /* regs->ip */
596 pushq 2*8(%rdi) /* regs->orig_ax */
597 pushq 8(%rdi) /* return address */
603 PUSH_AND_CLEAR_REGS save_ret=1
604 ENCODE_FRAME_POINTER 8
610 * IRQ from user mode.
612 * We need to tell lockdep that IRQs are off. We can't do this until
613 * we fix gsbase, and we should do it before enter_from_user_mode
614 * (which can take locks). Since TRACE_IRQS_OFF is idempotent,
615 * the simplest way to handle it is to just call it twice if
616 * we enter from user mode. There's no reason to optimize this since
617 * TRACE_IRQS_OFF is a no-op if lockdep is off.
621 CALL_enter_from_user_mode
624 ENTER_IRQ_STACK old_rsp=%rdi save_ret=1
625 /* We entered an interrupt context - irqs are off: */
632 /* Interrupt entry/exit. */
635 * The interrupt stubs push (~vector+0x80) onto the stack and
636 * then jump to common_interrupt.
638 .p2align CONFIG_X86_L1_CACHE_SHIFT
640 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */
642 UNWIND_HINT_REGS indirect=1
643 call do_IRQ /* rdi points to pt_regs */
644 /* 0(%rsp): old RSP */
646 DISABLE_INTERRUPTS(CLBR_ANY)
654 /* Interrupt came from user space */
657 call prepare_exit_to_usermode
660 GLOBAL(swapgs_restore_regs_and_return_to_usermode)
661 #ifdef CONFIG_DEBUG_ENTRY
662 /* Assert that pt_regs indicates user mode. */
671 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS.
672 * Save old stack pointer and switch to trampoline stack.
675 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
677 /* Copy the IRET frame to the trampoline stack. */
678 pushq 6*8(%rdi) /* SS */
679 pushq 5*8(%rdi) /* RSP */
680 pushq 4*8(%rdi) /* EFLAGS */
681 pushq 3*8(%rdi) /* CS */
682 pushq 2*8(%rdi) /* RIP */
684 /* Push user RDI on the trampoline stack. */
688 * We are on the trampoline stack. All regs except RDI are live.
689 * We can do future final exit work right here.
692 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
700 /* Returning to kernel space */
702 #ifdef CONFIG_PREEMPT
703 /* Interrupts are off */
704 /* Check if we need preemption */
705 btl $9, EFLAGS(%rsp) /* were interrupts off? */
707 0: cmpl $0, PER_CPU_VAR(__preempt_count)
709 call preempt_schedule_irq
714 * The iretq could re-enable interrupts:
718 GLOBAL(restore_regs_and_return_to_kernel)
719 #ifdef CONFIG_DEBUG_ENTRY
720 /* Assert that pt_regs indicates kernel mode. */
727 addq $8, %rsp /* skip regs->orig_ax */
729 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
730 * when returning from IPI handler.
735 UNWIND_HINT_IRET_REGS
737 * Are we returning to a stack segment from the LDT? Note: in
738 * 64-bit mode SS:RSP on the exception stack is always valid.
740 #ifdef CONFIG_X86_ESPFIX64
741 testb $4, (SS-RIP)(%rsp)
742 jnz native_irq_return_ldt
745 .global native_irq_return_iret
746 native_irq_return_iret:
748 * This may fault. Non-paranoid faults on return to userspace are
749 * handled by fixup_bad_iret. These include #SS, #GP, and #NP.
750 * Double-faults due to espfix64 are handled in do_double_fault.
751 * Other faults here are fatal.
755 #ifdef CONFIG_X86_ESPFIX64
756 native_irq_return_ldt:
758 * We are running with user GSBASE. All GPRs contain their user
759 * values. We have a percpu ESPFIX stack that is eight slots
760 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom
761 * of the ESPFIX stack.
763 * We clobber RAX and RDI in this code. We stash RDI on the
764 * normal stack and RAX on the ESPFIX stack.
766 * The ESPFIX stack layout we set up looks like this:
768 * --- top of ESPFIX stack ---
773 * RIP <-- RSP points here when we're done
774 * RAX <-- espfix_waddr points here
775 * --- bottom of ESPFIX stack ---
778 pushq %rdi /* Stash user RDI */
779 SWAPGS /* to kernel GS */
780 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */
782 movq PER_CPU_VAR(espfix_waddr), %rdi
783 movq %rax, (0*8)(%rdi) /* user RAX */
784 movq (1*8)(%rsp), %rax /* user RIP */
785 movq %rax, (1*8)(%rdi)
786 movq (2*8)(%rsp), %rax /* user CS */
787 movq %rax, (2*8)(%rdi)
788 movq (3*8)(%rsp), %rax /* user RFLAGS */
789 movq %rax, (3*8)(%rdi)
790 movq (5*8)(%rsp), %rax /* user SS */
791 movq %rax, (5*8)(%rdi)
792 movq (4*8)(%rsp), %rax /* user RSP */
793 movq %rax, (4*8)(%rdi)
794 /* Now RAX == RSP. */
796 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */
799 * espfix_stack[31:16] == 0. The page tables are set up such that
800 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of
801 * espfix_waddr for any X. That is, there are 65536 RO aliases of
802 * the same page. Set up RSP so that RSP[31:16] contains the
803 * respective 16 bits of the /userspace/ RSP and RSP nonetheless
804 * still points to an RO alias of the ESPFIX stack.
806 orq PER_CPU_VAR(espfix_stack), %rax
808 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
809 SWAPGS /* to user GS */
810 popq %rdi /* Restore user RDI */
813 UNWIND_HINT_IRET_REGS offset=8
816 * At this point, we cannot write to the stack any more, but we can
819 popq %rax /* Restore user RAX */
822 * RSP now points to an ordinary IRET frame, except that the page
823 * is read-only and RSP[31:16] are preloaded with the userspace
824 * values. We can now IRET back to userspace.
826 jmp native_irq_return_iret
828 END(common_interrupt)
833 .macro apicinterrupt3 num sym do_sym
835 UNWIND_HINT_IRET_REGS
839 UNWIND_HINT_REGS indirect=1
840 call \do_sym /* rdi points to pt_regs */
845 /* Make sure APIC interrupt handlers end up in the irqentry section: */
846 #define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax"
847 #define POP_SECTION_IRQENTRY .popsection
849 .macro apicinterrupt num sym do_sym
850 PUSH_SECTION_IRQENTRY
851 apicinterrupt3 \num \sym \do_sym
856 apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt
857 apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt
861 apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt
864 apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt
865 apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi
867 #ifdef CONFIG_HAVE_KVM
868 apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi
869 apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi
870 apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi
873 #ifdef CONFIG_X86_MCE_THRESHOLD
874 apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt
877 #ifdef CONFIG_X86_MCE_AMD
878 apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt
881 #ifdef CONFIG_X86_THERMAL_VECTOR
882 apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt
886 apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt
887 apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt
888 apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt
891 apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt
892 apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt
894 #ifdef CONFIG_IRQ_WORK
895 apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt
899 * Exception entry points.
901 #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8)
903 .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1
905 UNWIND_HINT_IRET_REGS offset=\has_error_code*8
908 .if \shift_ist != -1 && \paranoid == 0
909 .error "using shift_ist requires paranoid=1"
914 .if \has_error_code == 0
915 pushq $-1 /* ORIG_RAX: no syscall to restart */
919 testb $3, CS-ORIG_RAX(%rsp) /* If coming from userspace, switch stacks */
920 jnz .Lfrom_usermode_switch_stack_\@
929 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */
933 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */
939 movq %rsp, %rdi /* pt_regs pointer */
942 movq ORIG_RAX(%rsp), %rsi /* get error code */
943 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
945 xorl %esi, %esi /* no error code */
949 subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
955 addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
958 /* these procedures expect "no swapgs" flag in ebx */
967 * Entry from userspace. Switch stacks and treat it
968 * as a normal entry. This means that paranoid handlers
969 * run in real process context if user_mode(regs).
971 .Lfrom_usermode_switch_stack_\@:
974 movq %rsp, %rdi /* pt_regs pointer */
977 movq ORIG_RAX(%rsp), %rsi /* get error code */
978 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
980 xorl %esi, %esi /* no error code */
990 idtentry divide_error do_divide_error has_error_code=0
991 idtentry overflow do_overflow has_error_code=0
992 idtentry bounds do_bounds has_error_code=0
993 idtentry invalid_op do_invalid_op has_error_code=0
994 idtentry device_not_available do_device_not_available has_error_code=0
995 idtentry double_fault do_double_fault has_error_code=1 paranoid=2
996 idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0
997 idtentry invalid_TSS do_invalid_TSS has_error_code=1
998 idtentry segment_not_present do_segment_not_present has_error_code=1
999 idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0
1000 idtentry coprocessor_error do_coprocessor_error has_error_code=0
1001 idtentry alignment_check do_alignment_check has_error_code=1
1002 idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0
1006 * Reload gs selector with exception handling
1009 ENTRY(native_load_gs_index)
1012 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI)
1017 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
1019 TRACE_IRQS_FLAGS (%rsp)
1023 ENDPROC(native_load_gs_index)
1024 EXPORT_SYMBOL(native_load_gs_index)
1026 _ASM_EXTABLE(.Lgs_change, bad_gs)
1027 .section .fixup, "ax"
1028 /* running with kernelgs */
1030 SWAPGS /* switch back to user gs */
1032 /* This can't be a string because the preprocessor needs to see it. */
1033 movl $__USER_DS, %eax
1036 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
1042 /* Call softirq on interrupt stack. Interrupts are off. */
1043 ENTRY(do_softirq_own_stack)
1046 ENTER_IRQ_STACK regs=0 old_rsp=%r11
1048 LEAVE_IRQ_STACK regs=0
1051 ENDPROC(do_softirq_own_stack)
1054 idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0
1057 * A note on the "critical region" in our callback handler.
1058 * We want to avoid stacking callback handlers due to events occurring
1059 * during handling of the last event. To do this, we keep events disabled
1060 * until we've done all processing. HOWEVER, we must enable events before
1061 * popping the stack frame (can't be done atomically) and so it would still
1062 * be possible to get enough handler activations to overflow the stack.
1063 * Although unlikely, bugs of that kind are hard to track down, so we'd
1064 * like to avoid the possibility.
1065 * So, on entry to the handler we detect whether we interrupted an
1066 * existing activation in its critical region -- if so, we pop the current
1067 * activation and restart the handler using the previous one.
1069 ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */
1072 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
1073 * see the correct pointer to the pt_regs
1076 movq %rdi, %rsp /* we don't return, adjust the stack frame */
1079 ENTER_IRQ_STACK old_rsp=%r10
1080 call xen_evtchn_do_upcall
1083 #ifndef CONFIG_PREEMPT
1084 call xen_maybe_preempt_hcall
1087 END(xen_do_hypervisor_callback)
1090 * Hypervisor uses this for application faults while it executes.
1091 * We get here for two reasons:
1092 * 1. Fault while reloading DS, ES, FS or GS
1093 * 2. Fault while executing IRET
1094 * Category 1 we do not need to fix up as Xen has already reloaded all segment
1095 * registers that could be reloaded and zeroed the others.
1096 * Category 2 we fix up by killing the current process. We cannot use the
1097 * normal Linux return path in this case because if we use the IRET hypercall
1098 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
1099 * We distinguish between categories by comparing each saved segment register
1100 * with its current contents: any discrepancy means we in category 1.
1102 ENTRY(xen_failsafe_callback)
1105 cmpw %cx, 0x10(%rsp)
1108 cmpw %cx, 0x18(%rsp)
1111 cmpw %cx, 0x20(%rsp)
1114 cmpw %cx, 0x28(%rsp)
1116 /* All segments match their saved values => Category 2 (Bad IRET). */
1121 UNWIND_HINT_IRET_REGS offset=8
1122 jmp general_protection
1123 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
1127 UNWIND_HINT_IRET_REGS
1128 pushq $-1 /* orig_ax = -1 => not a system call */
1130 ENCODE_FRAME_POINTER
1132 END(xen_failsafe_callback)
1134 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1135 xen_hvm_callback_vector xen_evtchn_do_upcall
1137 #endif /* CONFIG_XEN */
1139 #if IS_ENABLED(CONFIG_HYPERV)
1140 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1141 hyperv_callback_vector hyperv_vector_handler
1143 apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \
1144 hyperv_reenlightenment_vector hyperv_reenlightenment_intr
1146 apicinterrupt3 HYPERV_STIMER0_VECTOR \
1147 hv_stimer0_callback_vector hv_stimer0_vector_handler
1148 #endif /* CONFIG_HYPERV */
1150 idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
1151 idtentry int3 do_int3 has_error_code=0
1152 idtentry stack_segment do_stack_segment has_error_code=1
1155 idtentry xennmi do_nmi has_error_code=0
1156 idtentry xendebug do_debug has_error_code=0
1157 idtentry xenint3 do_int3 has_error_code=0
1160 idtentry general_protection do_general_protection has_error_code=1
1161 idtentry page_fault do_page_fault has_error_code=1
1163 #ifdef CONFIG_KVM_GUEST
1164 idtentry async_page_fault do_async_page_fault has_error_code=1
1167 #ifdef CONFIG_X86_MCE
1168 idtentry machine_check do_mce has_error_code=0 paranoid=1
1172 * Save all registers in pt_regs, and switch gs if needed.
1173 * Use slow, but surefire "are we in kernel?" check.
1174 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise
1176 ENTRY(paranoid_entry)
1179 PUSH_AND_CLEAR_REGS save_ret=1
1180 ENCODE_FRAME_POINTER 8
1182 movl $MSR_GS_BASE, %ecx
1185 js 1f /* negative -> in kernel */
1191 * Always stash CR3 in %r14. This value will be restored,
1192 * verbatim, at exit. Needed if paranoid_entry interrupted
1193 * another entry that already switched to the user CR3 value
1194 * but has not yet returned to userspace.
1196 * This is also why CS (stashed in the "iret frame" by the
1197 * hardware at entry) can not be used: this may be a return
1198 * to kernel code, but with a user CR3 value.
1200 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
1206 * "Paranoid" exit path from exception stack. This is invoked
1207 * only on return from non-NMI IST interrupts that came
1208 * from kernel space.
1210 * We may be returning to very strange contexts (e.g. very early
1211 * in syscall entry), so checking for preemption here would
1212 * be complicated. Fortunately, we there's no good reason
1213 * to try to handle preemption here.
1215 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it)
1217 ENTRY(paranoid_exit)
1219 DISABLE_INTERRUPTS(CLBR_ANY)
1220 TRACE_IRQS_OFF_DEBUG
1221 testl %ebx, %ebx /* swapgs needed? */
1222 jnz .Lparanoid_exit_no_swapgs
1224 /* Always restore stashed CR3 value (see paranoid_entry) */
1225 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14
1227 jmp .Lparanoid_exit_restore
1228 .Lparanoid_exit_no_swapgs:
1229 TRACE_IRQS_IRETQ_DEBUG
1230 /* Always restore stashed CR3 value (see paranoid_entry) */
1231 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14
1232 .Lparanoid_exit_restore:
1233 jmp restore_regs_and_return_to_kernel
1237 * Save all registers in pt_regs, and switch GS if needed.
1242 PUSH_AND_CLEAR_REGS save_ret=1
1243 ENCODE_FRAME_POINTER 8
1244 testb $3, CS+8(%rsp)
1245 jz .Lerror_kernelspace
1248 * We entered from user mode or we're pretending to have entered
1249 * from user mode due to an IRET fault.
1252 /* We have user CR3. Change to kernel CR3. */
1253 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1255 .Lerror_entry_from_usermode_after_swapgs:
1256 /* Put us onto the real thread stack. */
1257 popq %r12 /* save return addr in %12 */
1258 movq %rsp, %rdi /* arg0 = pt_regs pointer */
1260 movq %rax, %rsp /* switch stack */
1261 ENCODE_FRAME_POINTER
1265 * We need to tell lockdep that IRQs are off. We can't do this until
1266 * we fix gsbase, and we should do it before enter_from_user_mode
1267 * (which can take locks).
1270 CALL_enter_from_user_mode
1278 * There are two places in the kernel that can potentially fault with
1279 * usergs. Handle them here. B stepping K8s sometimes report a
1280 * truncated RIP for IRET exceptions returning to compat mode. Check
1281 * for these here too.
1283 .Lerror_kernelspace:
1284 leaq native_irq_return_iret(%rip), %rcx
1285 cmpq %rcx, RIP+8(%rsp)
1287 movl %ecx, %eax /* zero extend */
1288 cmpq %rax, RIP+8(%rsp)
1290 cmpq $.Lgs_change, RIP+8(%rsp)
1291 jne .Lerror_entry_done
1294 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up
1295 * gsbase and proceed. We'll fix up the exception and land in
1296 * .Lgs_change's error handler with kernel gsbase.
1299 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1300 jmp .Lerror_entry_done
1303 /* Fix truncated RIP */
1304 movq %rcx, RIP+8(%rsp)
1309 * We came from an IRET to user mode, so we have user
1310 * gsbase and CR3. Switch to kernel gsbase and CR3:
1313 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1316 * Pretend that the exception came from user mode: set up pt_regs
1317 * as if we faulted immediately after IRET.
1322 jmp .Lerror_entry_from_usermode_after_swapgs
1327 DISABLE_INTERRUPTS(CLBR_ANY)
1335 * Runs on exception stack. Xen PV does not go through this path at all,
1336 * so we can use real assembly here.
1339 * %r14: Used to save/restore the CR3 of the interrupted context
1340 * when PAGE_TABLE_ISOLATION is in use. Do not clobber.
1343 UNWIND_HINT_IRET_REGS
1346 * We allow breakpoints in NMIs. If a breakpoint occurs, then
1347 * the iretq it performs will take us out of NMI context.
1348 * This means that we can have nested NMIs where the next
1349 * NMI is using the top of the stack of the previous NMI. We
1350 * can't let it execute because the nested NMI will corrupt the
1351 * stack of the previous NMI. NMI handlers are not re-entrant
1354 * To handle this case we do the following:
1355 * Check the a special location on the stack that contains
1356 * a variable that is set when NMIs are executing.
1357 * The interrupted task's stack is also checked to see if it
1359 * If the variable is not set and the stack is not the NMI
1361 * o Set the special variable on the stack
1362 * o Copy the interrupt frame into an "outermost" location on the
1364 * o Copy the interrupt frame into an "iret" location on the stack
1365 * o Continue processing the NMI
1366 * If the variable is set or the previous stack is the NMI stack:
1367 * o Modify the "iret" location to jump to the repeat_nmi
1368 * o return back to the first NMI
1370 * Now on exit of the first NMI, we first clear the stack variable
1371 * The NMI stack will tell any nested NMIs at that point that it is
1372 * nested. Then we pop the stack normally with iret, and if there was
1373 * a nested NMI that updated the copy interrupt stack frame, a
1374 * jump will be made to the repeat_nmi code that will handle the second
1377 * However, espfix prevents us from directly returning to userspace
1378 * with a single IRET instruction. Similarly, IRET to user mode
1379 * can fault. We therefore handle NMIs from user space like
1380 * other IST entries.
1385 /* Use %rdx as our temp variable throughout */
1388 testb $3, CS-RIP+8(%rsp)
1389 jz .Lnmi_from_kernel
1392 * NMI from user mode. We need to run on the thread stack, but we
1393 * can't go through the normal entry paths: NMIs are masked, and
1394 * we don't want to enable interrupts, because then we'll end
1395 * up in an awkward situation in which IRQs are on but NMIs
1398 * We also must not push anything to the stack before switching
1399 * stacks lest we corrupt the "NMI executing" variable.
1404 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx
1406 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
1407 UNWIND_HINT_IRET_REGS base=%rdx offset=8
1408 pushq 5*8(%rdx) /* pt_regs->ss */
1409 pushq 4*8(%rdx) /* pt_regs->rsp */
1410 pushq 3*8(%rdx) /* pt_regs->flags */
1411 pushq 2*8(%rdx) /* pt_regs->cs */
1412 pushq 1*8(%rdx) /* pt_regs->rip */
1413 UNWIND_HINT_IRET_REGS
1414 pushq $-1 /* pt_regs->orig_ax */
1415 PUSH_AND_CLEAR_REGS rdx=(%rdx)
1416 ENCODE_FRAME_POINTER
1419 * At this point we no longer need to worry about stack damage
1420 * due to nesting -- we're on the normal thread stack and we're
1421 * done with the NMI stack.
1429 * Return back to user mode. We must *not* do the normal exit
1430 * work, because we don't want to enable interrupts.
1432 jmp swapgs_restore_regs_and_return_to_usermode
1436 * Here's what our stack frame will look like:
1437 * +---------------------------------------------------------+
1439 * | original Return RSP |
1440 * | original RFLAGS |
1443 * +---------------------------------------------------------+
1444 * | temp storage for rdx |
1445 * +---------------------------------------------------------+
1446 * | "NMI executing" variable |
1447 * +---------------------------------------------------------+
1448 * | iret SS } Copied from "outermost" frame |
1449 * | iret Return RSP } on each loop iteration; overwritten |
1450 * | iret RFLAGS } by a nested NMI to force another |
1451 * | iret CS } iteration if needed. |
1453 * +---------------------------------------------------------+
1454 * | outermost SS } initialized in first_nmi; |
1455 * | outermost Return RSP } will not be changed before |
1456 * | outermost RFLAGS } NMI processing is done. |
1457 * | outermost CS } Copied to "iret" frame on each |
1458 * | outermost RIP } iteration. |
1459 * +---------------------------------------------------------+
1461 * +---------------------------------------------------------+
1463 * The "original" frame is used by hardware. Before re-enabling
1464 * NMIs, we need to be done with it, and we need to leave enough
1465 * space for the asm code here.
1467 * We return by executing IRET while RSP points to the "iret" frame.
1468 * That will either return for real or it will loop back into NMI
1471 * The "outermost" frame is copied to the "iret" frame on each
1472 * iteration of the loop, so each iteration starts with the "iret"
1473 * frame pointing to the final return target.
1477 * Determine whether we're a nested NMI.
1479 * If we interrupted kernel code between repeat_nmi and
1480 * end_repeat_nmi, then we are a nested NMI. We must not
1481 * modify the "iret" frame because it's being written by
1482 * the outer NMI. That's okay; the outer NMI handler is
1483 * about to about to call do_nmi anyway, so we can just
1484 * resume the outer NMI.
1487 movq $repeat_nmi, %rdx
1490 movq $end_repeat_nmi, %rdx
1496 * Now check "NMI executing". If it's set, then we're nested.
1497 * This will not detect if we interrupted an outer NMI just
1504 * Now test if the previous stack was an NMI stack. This covers
1505 * the case where we interrupt an outer NMI after it clears
1506 * "NMI executing" but before IRET. We need to be careful, though:
1507 * there is one case in which RSP could point to the NMI stack
1508 * despite there being no NMI active: naughty userspace controls
1509 * RSP at the very beginning of the SYSCALL targets. We can
1510 * pull a fast one on naughty userspace, though: we program
1511 * SYSCALL to mask DF, so userspace cannot cause DF to be set
1512 * if it controls the kernel's RSP. We set DF before we clear
1516 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */
1517 cmpq %rdx, 4*8(%rsp)
1518 /* If the stack pointer is above the NMI stack, this is a normal NMI */
1521 subq $EXCEPTION_STKSZ, %rdx
1522 cmpq %rdx, 4*8(%rsp)
1523 /* If it is below the NMI stack, it is a normal NMI */
1526 /* Ah, it is within the NMI stack. */
1528 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp)
1529 jz first_nmi /* RSP was user controlled. */
1531 /* This is a nested NMI. */
1535 * Modify the "iret" frame to point to repeat_nmi, forcing another
1536 * iteration of NMI handling.
1539 leaq -10*8(%rsp), %rdx
1546 /* Put stack back */
1552 /* We are returning to kernel mode, so this cannot result in a fault. */
1559 /* Make room for "NMI executing". */
1562 /* Leave room for the "iret" frame */
1565 /* Copy the "original" frame to the "outermost" frame */
1569 UNWIND_HINT_IRET_REGS
1571 /* Everything up to here is safe from nested NMIs */
1573 #ifdef CONFIG_DEBUG_ENTRY
1575 * For ease of testing, unmask NMIs right away. Disabled by
1576 * default because IRET is very expensive.
1579 pushq %rsp /* RSP (minus 8 because of the previous push) */
1580 addq $8, (%rsp) /* Fix up RSP */
1582 pushq $__KERNEL_CS /* CS */
1584 iretq /* continues at repeat_nmi below */
1585 UNWIND_HINT_IRET_REGS
1591 * If there was a nested NMI, the first NMI's iret will return
1592 * here. But NMIs are still enabled and we can take another
1593 * nested NMI. The nested NMI checks the interrupted RIP to see
1594 * if it is between repeat_nmi and end_repeat_nmi, and if so
1595 * it will just return, as we are about to repeat an NMI anyway.
1596 * This makes it safe to copy to the stack frame that a nested
1599 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if
1600 * we're repeating an NMI, gsbase has the same value that it had on
1601 * the first iteration. paranoid_entry will load the kernel
1602 * gsbase if needed before we call do_nmi. "NMI executing"
1605 movq $1, 10*8(%rsp) /* Set "NMI executing". */
1608 * Copy the "outermost" frame to the "iret" frame. NMIs that nest
1609 * here must not modify the "iret" frame while we're writing to
1610 * it or it will end up containing garbage.
1620 * Everything below this point can be preempted by a nested NMI.
1621 * If this happens, then the inner NMI will change the "iret"
1622 * frame to point back to repeat_nmi.
1624 pushq $-1 /* ORIG_RAX: no syscall to restart */
1627 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit
1628 * as we should not be calling schedule in NMI context.
1629 * Even with normal interrupts enabled. An NMI should not be
1630 * setting NEED_RESCHED or anything that normal interrupts and
1631 * exceptions might do.
1636 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */
1641 /* Always restore stashed CR3 value (see paranoid_entry) */
1642 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14
1644 testl %ebx, %ebx /* swapgs needed? */
1652 * Skip orig_ax and the "outermost" frame to point RSP at the "iret"
1653 * at the "iret" frame.
1658 * Clear "NMI executing". Set DF first so that we can easily
1659 * distinguish the remaining code between here and IRET from
1660 * the SYSCALL entry and exit paths.
1662 * We arguably should just inspect RIP instead, but I (Andy) wrote
1663 * this code when I had the misapprehension that Xen PV supported
1664 * NMIs, and Xen PV would break that approach.
1667 movq $0, 5*8(%rsp) /* clear "NMI executing" */
1670 * iretq reads the "iret" frame and exits the NMI stack in a
1671 * single instruction. We are returning to kernel mode, so this
1672 * cannot result in a fault. Similarly, we don't need to worry
1673 * about espfix64 on the way back to kernel mode.
1678 ENTRY(ignore_sysret)
1684 ENTRY(rewind_stack_do_exit)
1686 /* Prevent any naive code from trying to unwind to our caller. */
1689 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax
1690 leaq -PTREGS_SIZE(%rax), %rsp
1691 UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE
1694 END(rewind_stack_do_exit)