1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 1991,1992 Linus Torvalds
5 * entry_32.S contains the system-call and low-level fault and trap handling routines.
7 * Stack layout while running C code:
8 * ptrace needs to have all registers on the stack.
9 * If the order here is changed, it needs to be
10 * updated in fork.c:copy_process(), signal.c:do_signal(),
11 * ptrace.c and ptrace.h
23 * 28(%esp) - %gs saved iff !CONFIG_X86_32_LAZY_GS
32 #include <linux/linkage.h>
33 #include <linux/err.h>
34 #include <asm/thread_info.h>
35 #include <asm/irqflags.h>
36 #include <asm/errno.h>
37 #include <asm/segment.h>
39 #include <asm/percpu.h>
40 #include <asm/processor-flags.h>
41 #include <asm/irq_vectors.h>
42 #include <asm/cpufeatures.h>
43 #include <asm/alternative-asm.h>
46 #include <asm/frame.h>
47 #include <asm/trapnr.h>
48 #include <asm/nospec-branch.h>
52 .section .entry.text, "ax"
54 #define PTI_SWITCH_MASK (1 << PAGE_SHIFT)
57 * User gs save/restore
59 * %gs is used for userland TLS and kernel only uses it for stack
60 * canary which is required to be at %gs:20 by gcc. Read the comment
61 * at the top of stackprotector.h for more info.
63 * Local labels 98 and 99 are used.
65 #ifdef CONFIG_X86_32_LAZY_GS
67 /* unfortunately push/pop can't be no-op */
72 addl $(4 + \pop), %esp
77 /* all the rest are no-op */
84 .macro REG_TO_PTGS reg
86 .macro SET_KERNEL_GS reg
89 #else /* CONFIG_X86_32_LAZY_GS */
102 .pushsection .fixup, "ax"
106 _ASM_EXTABLE(98b, 99b)
110 98: mov PT_GS(%esp), %gs
113 .pushsection .fixup, "ax"
114 99: movl $0, PT_GS(%esp)
117 _ASM_EXTABLE(98b, 99b)
123 .macro REG_TO_PTGS reg
124 movl \reg, PT_GS(%esp)
126 .macro SET_KERNEL_GS reg
127 movl $(__KERNEL_STACK_CANARY), \reg
131 #endif /* CONFIG_X86_32_LAZY_GS */
133 /* Unconditionally switch to user cr3 */
134 .macro SWITCH_TO_USER_CR3 scratch_reg:req
135 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
137 movl %cr3, \scratch_reg
138 orl $PTI_SWITCH_MASK, \scratch_reg
139 movl \scratch_reg, %cr3
143 .macro BUG_IF_WRONG_CR3 no_user_check=0
144 #ifdef CONFIG_DEBUG_ENTRY
145 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
146 .if \no_user_check == 0
147 /* coming from usermode? */
148 testl $USER_SEGMENT_RPL_MASK, PT_CS(%esp)
153 testl $PTI_SWITCH_MASK, %eax
155 /* From userspace with kernel cr3 - BUG */
162 * Switch to kernel cr3 if not already loaded and return current cr3 in
165 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
166 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
167 movl %cr3, \scratch_reg
168 /* Test if we are already on kernel CR3 */
169 testl $PTI_SWITCH_MASK, \scratch_reg
171 andl $(~PTI_SWITCH_MASK), \scratch_reg
172 movl \scratch_reg, %cr3
173 /* Return original CR3 in \scratch_reg */
174 orl $PTI_SWITCH_MASK, \scratch_reg
178 #define CS_FROM_ENTRY_STACK (1 << 31)
179 #define CS_FROM_USER_CR3 (1 << 30)
180 #define CS_FROM_KERNEL (1 << 29)
181 #define CS_FROM_ESPFIX (1 << 28)
185 * The high bits of the CS dword (__csh) are used for CS_FROM_*.
186 * Clear them in case hardware didn't do this for us.
188 andl $0x0000ffff, 4*4(%esp)
191 testl $X86_EFLAGS_VM, 5*4(%esp)
192 jnz .Lfrom_usermode_no_fixup_\@
194 testl $USER_SEGMENT_RPL_MASK, 4*4(%esp)
195 jnz .Lfrom_usermode_no_fixup_\@
197 orl $CS_FROM_KERNEL, 4*4(%esp)
200 * When we're here from kernel mode; the (exception) stack looks like:
202 * 6*4(%esp) - <previous context>
206 * 2*4(%esp) - orig_eax
207 * 1*4(%esp) - gs / function
210 * Lets build a 5 entry IRET frame after that, such that struct pt_regs
211 * is complete and in particular regs->sp is correct. This gives us
212 * the original 6 enties as gap:
214 * 14*4(%esp) - <previous context>
215 * 13*4(%esp) - gap / flags
216 * 12*4(%esp) - gap / cs
217 * 11*4(%esp) - gap / ip
218 * 10*4(%esp) - gap / orig_eax
219 * 9*4(%esp) - gap / gs / function
220 * 8*4(%esp) - gap / fs
226 * 2*4(%esp) - orig_eax
227 * 1*4(%esp) - gs / function
232 pushl %esp # sp (points at ss)
233 addl $7*4, (%esp) # point sp back at the previous context
234 pushl 7*4(%esp) # flags
237 pushl 7*4(%esp) # orig_eax
238 pushl 7*4(%esp) # gs / function
240 .Lfrom_usermode_no_fixup_\@:
245 * We're called with %ds, %es, %fs, and %gs from the interrupted
246 * frame, so we shouldn't use them. Also, we may be in ESPFIX
247 * mode and therefore have a nonzero SS base and an offset ESP,
248 * so any attempt to access the stack needs to use SS. (except for
249 * accesses through %esp, which automatically use SS.)
251 testl $CS_FROM_KERNEL, 1*4(%esp)
252 jz .Lfinished_frame_\@
255 * Reconstruct the 3 entry IRET frame right after the (modified)
256 * regs->sp without lowering %esp in between, such that an NMI in the
257 * middle doesn't scribble our stack.
261 movl 5*4(%esp), %eax # (modified) regs->sp
263 movl 4*4(%esp), %ecx # flags
264 movl %ecx, %ss:-1*4(%eax)
266 movl 3*4(%esp), %ecx # cs
267 andl $0x0000ffff, %ecx
268 movl %ecx, %ss:-2*4(%eax)
270 movl 2*4(%esp), %ecx # ip
271 movl %ecx, %ss:-3*4(%eax)
273 movl 1*4(%esp), %ecx # eax
274 movl %ecx, %ss:-4*4(%eax)
282 .macro SAVE_ALL pt_regs_ax=%eax switch_stacks=0 skip_gs=0 unwind_espfix=0
290 movl $(__KERNEL_PERCPU), %eax
292 .if \unwind_espfix > 0
307 movl $(__USER_DS), %edx
313 /* Switch to kernel stack if necessary */
314 .if \switch_stacks > 0
315 SWITCH_TO_KERNEL_STACK
319 .macro SAVE_ALL_NMI cr3_reg:req unwind_espfix=0
320 SAVE_ALL unwind_espfix=\unwind_espfix
325 * Now switch the CR3 when PTI is enabled.
327 * We can enter with either user or kernel cr3, the code will
328 * store the old cr3 in \cr3_reg and switches to the kernel cr3
331 SWITCH_TO_KERNEL_CR3 scratch_reg=\cr3_reg
336 .macro RESTORE_INT_REGS
346 .macro RESTORE_REGS pop=0
353 .pushsection .fixup, "ax"
367 .macro RESTORE_ALL_NMI cr3_reg:req pop=0
369 * Now switch the CR3 when PTI is enabled.
371 * We enter with kernel cr3 and switch the cr3 to the value
372 * stored on \cr3_reg, which is either a user or a kernel cr3.
374 ALTERNATIVE "jmp .Lswitched_\@", "", X86_FEATURE_PTI
376 testl $PTI_SWITCH_MASK, \cr3_reg
379 /* User cr3 in \cr3_reg - write it to hardware cr3 */
386 RESTORE_REGS pop=\pop
389 .macro CHECK_AND_APPLY_ESPFIX
390 #ifdef CONFIG_X86_ESPFIX32
391 #define GDT_ESPFIX_OFFSET (GDT_ENTRY_ESPFIX_SS * 8)
392 #define GDT_ESPFIX_SS PER_CPU_VAR(gdt_page) + GDT_ESPFIX_OFFSET
394 ALTERNATIVE "jmp .Lend_\@", "", X86_BUG_ESPFIX
396 movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS
398 * Warning: PT_OLDSS(%esp) contains the wrong/random values if we
399 * are returning to the kernel.
400 * See comments in process.c:copy_thread() for details.
402 movb PT_OLDSS(%esp), %ah
403 movb PT_CS(%esp), %al
404 andl $(X86_EFLAGS_VM | (SEGMENT_TI_MASK << 8) | SEGMENT_RPL_MASK), %eax
405 cmpl $((SEGMENT_LDT << 8) | USER_RPL), %eax
406 jne .Lend_\@ # returning to user-space with LDT SS
409 * Setup and switch to ESPFIX stack
411 * We're returning to userspace with a 16 bit stack. The CPU will not
412 * restore the high word of ESP for us on executing iret... This is an
413 * "official" bug of all the x86-compatible CPUs, which we can work
414 * around to make dosemu and wine happy. We do this by preloading the
415 * high word of ESP with the high word of the userspace ESP while
416 * compensating for the offset by changing to the ESPFIX segment with
417 * a base address that matches for the difference.
419 mov %esp, %edx /* load kernel esp */
420 mov PT_OLDESP(%esp), %eax /* load userspace esp */
421 mov %dx, %ax /* eax: new kernel esp */
422 sub %eax, %edx /* offset (low word is 0) */
424 mov %dl, GDT_ESPFIX_SS + 4 /* bits 16..23 */
425 mov %dh, GDT_ESPFIX_SS + 7 /* bits 24..31 */
427 pushl %eax /* new kernel esp */
429 * Disable interrupts, but do not irqtrace this section: we
430 * will soon execute iret and the tracer was already set to
431 * the irqstate after the IRET:
433 DISABLE_INTERRUPTS(CLBR_ANY)
434 lss (%esp), %esp /* switch to espfix segment */
436 #endif /* CONFIG_X86_ESPFIX32 */
440 * Called with pt_regs fully populated and kernel segments loaded,
441 * so we can access PER_CPU and use the integer registers.
443 * We need to be very careful here with the %esp switch, because an NMI
444 * can happen everywhere. If the NMI handler finds itself on the
445 * entry-stack, it will overwrite the task-stack and everything we
446 * copied there. So allocate the stack-frame on the task-stack and
447 * switch to it before we do any copying.
450 .macro SWITCH_TO_KERNEL_STACK
452 ALTERNATIVE "", "jmp .Lend_\@", X86_FEATURE_XENPV
456 SWITCH_TO_KERNEL_CR3 scratch_reg=%eax
459 * %eax now contains the entry cr3 and we carry it forward in
460 * that register for the time this macro runs
463 /* Are we on the entry stack? Bail out if not! */
464 movl PER_CPU_VAR(cpu_entry_area), %ecx
465 addl $CPU_ENTRY_AREA_entry_stack + SIZEOF_entry_stack, %ecx
466 subl %esp, %ecx /* ecx = (end of entry_stack) - esp */
467 cmpl $SIZEOF_entry_stack, %ecx
470 /* Load stack pointer into %esi and %edi */
474 /* Move %edi to the top of the entry stack */
475 andl $(MASK_entry_stack), %edi
476 addl $(SIZEOF_entry_stack), %edi
478 /* Load top of task-stack into %edi */
479 movl TSS_entry2task_stack(%edi), %edi
481 /* Special case - entry from kernel mode via entry stack */
483 movl PT_EFLAGS(%esp), %ecx # mix EFLAGS and CS
484 movb PT_CS(%esp), %cl
485 andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %ecx
487 movl PT_CS(%esp), %ecx
488 andl $SEGMENT_RPL_MASK, %ecx
491 jb .Lentry_from_kernel_\@
494 movl $PTREGS_SIZE, %ecx
497 testl $X86_EFLAGS_VM, PT_EFLAGS(%esi)
501 * Stack-frame contains 4 additional segment registers when
502 * coming from VM86 mode
509 /* Allocate frame on task-stack */
512 /* Switch to task-stack */
516 * We are now on the task-stack and can safely copy over the
525 .Lentry_from_kernel_\@:
528 * This handles the case when we enter the kernel from
529 * kernel-mode and %esp points to the entry-stack. When this
530 * happens we need to switch to the task-stack to run C code,
531 * but switch back to the entry-stack again when we approach
532 * iret and return to the interrupted code-path. This usually
533 * happens when we hit an exception while restoring user-space
534 * segment registers on the way back to user-space or when the
535 * sysenter handler runs with eflags.tf set.
537 * When we switch to the task-stack here, we can't trust the
538 * contents of the entry-stack anymore, as the exception handler
539 * might be scheduled out or moved to another CPU. Therefore we
540 * copy the complete entry-stack to the task-stack and set a
541 * marker in the iret-frame (bit 31 of the CS dword) to detect
542 * what we've done on the iret path.
544 * On the iret path we copy everything back and switch to the
545 * entry-stack, so that the interrupted kernel code-path
546 * continues on the same stack it was interrupted with.
548 * Be aware that an NMI can happen anytime in this code.
550 * %esi: Entry-Stack pointer (same as %esp)
551 * %edi: Top of the task stack
552 * %eax: CR3 on kernel entry
555 /* Calculate number of bytes on the entry stack in %ecx */
558 /* %ecx to the top of entry-stack */
559 andl $(MASK_entry_stack), %ecx
560 addl $(SIZEOF_entry_stack), %ecx
562 /* Number of bytes on the entry stack to %ecx */
565 /* Mark stackframe as coming from entry stack */
566 orl $CS_FROM_ENTRY_STACK, PT_CS(%esp)
569 * Test the cr3 used to enter the kernel and add a marker
570 * so that we can switch back to it before iret.
572 testl $PTI_SWITCH_MASK, %eax
574 orl $CS_FROM_USER_CR3, PT_CS(%esp)
577 * %esi and %edi are unchanged, %ecx contains the number of
578 * bytes to copy. The code at .Lcopy_pt_regs_\@ will allocate
579 * the stack-frame on task-stack and copy everything over
581 jmp .Lcopy_pt_regs_\@
587 * Switch back from the kernel stack to the entry stack.
589 * The %esp register must point to pt_regs on the task stack. It will
590 * first calculate the size of the stack-frame to copy, depending on
591 * whether we return to VM86 mode or not. With that it uses 'rep movsl'
592 * to copy the contents of the stack over to the entry stack.
594 * We must be very careful here, as we can't trust the contents of the
595 * task-stack once we switched to the entry-stack. When an NMI happens
596 * while on the entry-stack, the NMI handler will switch back to the top
597 * of the task stack, overwriting our stack-frame we are about to copy.
598 * Therefore we switch the stack only after everything is copied over.
600 .macro SWITCH_TO_ENTRY_STACK
602 ALTERNATIVE "", "jmp .Lend_\@", X86_FEATURE_XENPV
605 movl $PTREGS_SIZE, %ecx
608 testl $(X86_EFLAGS_VM), PT_EFLAGS(%esp)
611 /* Additional 4 registers to copy when returning to VM86 mode */
617 /* Initialize source and destination for movsl */
618 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %edi
622 /* Save future stack pointer in %ebx */
625 /* Copy over the stack-frame */
631 * Switch to entry-stack - needs to happen after everything is
632 * copied because the NMI handler will overwrite the task-stack
633 * when on entry-stack
641 * This macro handles the case when we return to kernel-mode on the iret
642 * path and have to switch back to the entry stack and/or user-cr3
644 * See the comments below the .Lentry_from_kernel_\@ label in the
645 * SWITCH_TO_KERNEL_STACK macro for more details.
647 .macro PARANOID_EXIT_TO_KERNEL_MODE
650 * Test if we entered the kernel with the entry-stack. Most
651 * likely we did not, because this code only runs on the
652 * return-to-kernel path.
654 testl $CS_FROM_ENTRY_STACK, PT_CS(%esp)
657 /* Unlikely slow-path */
659 /* Clear marker from stack-frame */
660 andl $(~CS_FROM_ENTRY_STACK), PT_CS(%esp)
662 /* Copy the remaining task-stack contents to entry-stack */
664 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %edi
666 /* Bytes on the task-stack to ecx */
667 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp1), %ecx
670 /* Allocate stack-frame on entry-stack */
674 * Save future stack-pointer, we must not switch until the
675 * copy is done, otherwise the NMI handler could destroy the
676 * contents of the task-stack we are about to copy.
685 /* Safe to switch to entry-stack now */
689 * We came from entry-stack and need to check if we also need to
690 * switch back to user cr3.
692 testl $CS_FROM_USER_CR3, PT_CS(%esp)
695 /* Clear marker from stack-frame */
696 andl $(~CS_FROM_USER_CR3), PT_CS(%esp)
698 SWITCH_TO_USER_CR3 scratch_reg=%eax
704 * idtentry - Macro to generate entry stubs for simple IDT entries
705 * @vector: Vector number
706 * @asmsym: ASM symbol for the entry point
707 * @cfunc: C function to be called
708 * @has_error_code: Hardware pushed error code on stack
710 .macro idtentry vector asmsym cfunc has_error_code:req
711 SYM_CODE_START(\asmsym)
715 .if \has_error_code == 0
716 pushl $0 /* Clear the error code */
719 /* Push the C-function address into the GS slot */
721 /* Invoke the common exception entry */
723 SYM_CODE_END(\asmsym)
726 .macro idtentry_irq vector cfunc
727 .p2align CONFIG_X86_L1_CACHE_SHIFT
728 SYM_CODE_START_LOCAL(asm_\cfunc)
730 SAVE_ALL switch_stacks=1
733 movl PT_ORIG_EAX(%esp), %edx /* get the vector from stack */
734 movl $-1, PT_ORIG_EAX(%esp) /* no syscall to restart */
736 jmp handle_exception_return
737 SYM_CODE_END(asm_\cfunc)
740 .macro idtentry_sysvec vector cfunc
741 idtentry \vector asm_\cfunc \cfunc has_error_code=0
745 * Include the defines which emit the idt entries which are shared
746 * shared between 32 and 64 bit and emit the __irqentry_text_* markers
747 * so the stacktrace boundary checks work.
750 .globl __irqentry_text_start
751 __irqentry_text_start:
753 #include <asm/idtentry.h>
756 .globl __irqentry_text_end
763 .pushsection .text, "ax"
764 SYM_CODE_START(__switch_to_asm)
766 * Save callee-saved registers
767 * This must match the order in struct inactive_task_frame
774 * Flags are saved to prevent AC leakage. This could go
775 * away if objtool would have 32bit support to verify
776 * the STAC/CLAC correctness.
781 movl %esp, TASK_threadsp(%eax)
782 movl TASK_threadsp(%edx), %esp
784 #ifdef CONFIG_STACKPROTECTOR
785 movl TASK_stack_canary(%edx), %ebx
786 movl %ebx, PER_CPU_VAR(stack_canary)+stack_canary_offset
789 #ifdef CONFIG_RETPOLINE
791 * When switching from a shallower to a deeper call stack
792 * the RSB may either underflow or use entries populated
793 * with userspace addresses. On CPUs where those concerns
794 * exist, overwrite the RSB with entries which capture
795 * speculative execution to prevent attack.
797 FILL_RETURN_BUFFER %ebx, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
800 /* Restore flags or the incoming task to restore AC state. */
802 /* restore callee-saved registers */
809 SYM_CODE_END(__switch_to_asm)
813 * The unwinder expects the last frame on the stack to always be at the same
814 * offset from the end of the page, which allows it to validate the stack.
815 * Calling schedule_tail() directly would break that convention because its an
816 * asmlinkage function so its argument has to be pushed on the stack. This
817 * wrapper creates a proper "end of stack" frame header before the call.
819 .pushsection .text, "ax"
820 SYM_FUNC_START(schedule_tail_wrapper)
829 SYM_FUNC_END(schedule_tail_wrapper)
833 * A newly forked process directly context switches into this address.
835 * eax: prev task we switched from
836 * ebx: kernel thread func (NULL for user thread)
837 * edi: kernel thread arg
839 .pushsection .text, "ax"
840 SYM_CODE_START(ret_from_fork)
841 call schedule_tail_wrapper
844 jnz 1f /* kernel threads are uncommon */
847 /* When we fork, we trace the syscall return in the child, too. */
849 call syscall_exit_to_user_mode
850 jmp .Lsyscall_32_done
856 * A kernel thread is allowed to return here after successfully
857 * calling kernel_execve(). Exit to userspace to complete the execve()
860 movl $0, PT_EAX(%esp)
862 SYM_CODE_END(ret_from_fork)
865 SYM_ENTRY(__begin_SYSENTER_singlestep_region, SYM_L_GLOBAL, SYM_A_NONE)
867 * All code from here through __end_SYSENTER_singlestep_region is subject
868 * to being single-stepped if a user program sets TF and executes SYSENTER.
869 * There is absolutely nothing that we can do to prevent this from happening
870 * (thanks Intel!). To keep our handling of this situation as simple as
871 * possible, we handle TF just like AC and NT, except that our #DB handler
872 * will ignore all of the single-step traps generated in this range.
877 * Xen doesn't set %esp to be precisely what the normal SYSENTER
878 * entry point expects, so fix it up before using the normal path.
880 SYM_CODE_START(xen_sysenter_target)
881 addl $5*4, %esp /* remove xen-provided frame */
882 jmp .Lsysenter_past_esp
883 SYM_CODE_END(xen_sysenter_target)
887 * 32-bit SYSENTER entry.
889 * 32-bit system calls through the vDSO's __kernel_vsyscall enter here
890 * if X86_FEATURE_SEP is available. This is the preferred system call
891 * entry on 32-bit systems.
893 * The SYSENTER instruction, in principle, should *only* occur in the
894 * vDSO. In practice, a small number of Android devices were shipped
895 * with a copy of Bionic that inlined a SYSENTER instruction. This
896 * never happened in any of Google's Bionic versions -- it only happened
897 * in a narrow range of Intel-provided versions.
899 * SYSENTER loads SS, ESP, CS, and EIP from previously programmed MSRs.
900 * IF and VM in RFLAGS are cleared (IOW: interrupts are off).
901 * SYSENTER does not save anything on the stack,
902 * and does not save old EIP (!!!), ESP, or EFLAGS.
904 * To avoid losing track of EFLAGS.VM (and thus potentially corrupting
905 * user and/or vm86 state), we explicitly disable the SYSENTER
906 * instruction in vm86 mode by reprogramming the MSRs.
909 * eax system call number
918 SYM_FUNC_START(entry_SYSENTER_32)
920 * On entry-stack with all userspace-regs live - save and
921 * restore eflags and %eax to use it as scratch-reg for the cr3
926 BUG_IF_WRONG_CR3 no_user_check=1
927 SWITCH_TO_KERNEL_CR3 scratch_reg=%eax
931 /* Stack empty again, switch to task stack */
932 movl TSS_entry2task_stack(%esp), %esp
935 pushl $__USER_DS /* pt_regs->ss */
936 pushl $0 /* pt_regs->sp (placeholder) */
937 pushfl /* pt_regs->flags (except IF = 0) */
938 pushl $__USER_CS /* pt_regs->cs */
939 pushl $0 /* pt_regs->ip = 0 (placeholder) */
940 pushl %eax /* pt_regs->orig_ax */
941 SAVE_ALL pt_regs_ax=$-ENOSYS /* save rest, stack already switched */
944 * SYSENTER doesn't filter flags, so we need to clear NT, AC
945 * and TF ourselves. To save a few cycles, we can check whether
946 * either was set instead of doing an unconditional popfq.
947 * This needs to happen before enabling interrupts so that
948 * we don't get preempted with NT set.
950 * If TF is set, we will single-step all the way to here -- do_debug
951 * will ignore all the traps. (Yes, this is slow, but so is
952 * single-stepping in general. This allows us to avoid having
953 * a more complicated code to handle the case where a user program
954 * forces us to single-step through the SYSENTER entry code.)
956 * NB.: .Lsysenter_fix_flags is a label with the code under it moved
957 * out-of-line as an optimization: NT is unlikely to be set in the
958 * majority of the cases and instead of polluting the I$ unnecessarily,
959 * we're keeping that code behind a branch which will predict as
960 * not-taken and therefore its instructions won't be fetched.
962 testl $X86_EFLAGS_NT|X86_EFLAGS_AC|X86_EFLAGS_TF, PT_EFLAGS(%esp)
963 jnz .Lsysenter_fix_flags
964 .Lsysenter_flags_fixed:
968 /* XEN PV guests always use IRET path */
969 ALTERNATIVE "testl %eax, %eax; jz .Lsyscall_32_done", \
970 "jmp .Lsyscall_32_done", X86_FEATURE_XENPV
974 /* Opportunistic SYSEXIT */
977 * Setup entry stack - we keep the pointer in %eax and do the
978 * switch after almost all user-state is restored.
981 /* Load entry stack pointer and allocate frame for eflags/eax */
982 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %eax
985 /* Copy eflags and eax to entry stack */
986 movl PT_EFLAGS(%esp), %edi
987 movl PT_EAX(%esp), %esi
991 /* Restore user registers and segments */
992 movl PT_EIP(%esp), %edx /* pt_regs->ip */
993 movl PT_OLDESP(%esp), %ecx /* pt_regs->sp */
994 1: mov PT_FS(%esp), %fs
997 popl %ebx /* pt_regs->bx */
998 addl $2*4, %esp /* skip pt_regs->cx and pt_regs->dx */
999 popl %esi /* pt_regs->si */
1000 popl %edi /* pt_regs->di */
1001 popl %ebp /* pt_regs->bp */
1003 /* Switch to entry stack */
1006 /* Now ready to switch the cr3 */
1007 SWITCH_TO_USER_CR3 scratch_reg=%eax
1010 * Restore all flags except IF. (We restore IF separately because
1011 * STI gives a one-instruction window in which we won't be interrupted,
1012 * whereas POPF does not.)
1014 btrl $X86_EFLAGS_IF_BIT, (%esp)
1015 BUG_IF_WRONG_CR3 no_user_check=1
1020 * Return back to the vDSO, which will pop ecx and edx.
1021 * Don't bother with DS and ES (they already contain __USER_DS).
1026 .pushsection .fixup, "ax"
1027 2: movl $0, PT_FS(%esp)
1030 _ASM_EXTABLE(1b, 2b)
1033 .Lsysenter_fix_flags:
1034 pushl $X86_EFLAGS_FIXED
1036 jmp .Lsysenter_flags_fixed
1037 SYM_ENTRY(__end_SYSENTER_singlestep_region, SYM_L_GLOBAL, SYM_A_NONE)
1038 SYM_FUNC_END(entry_SYSENTER_32)
1041 * 32-bit legacy system call entry.
1043 * 32-bit x86 Linux system calls traditionally used the INT $0x80
1044 * instruction. INT $0x80 lands here.
1046 * This entry point can be used by any 32-bit perform system calls.
1047 * Instances of INT $0x80 can be found inline in various programs and
1048 * libraries. It is also used by the vDSO's __kernel_vsyscall
1049 * fallback for hardware that doesn't support a faster entry method.
1050 * Restarted 32-bit system calls also fall back to INT $0x80
1051 * regardless of what instruction was originally used to do the system
1052 * call. (64-bit programs can use INT $0x80 as well, but they can
1053 * only run on 64-bit kernels and therefore land in
1054 * entry_INT80_compat.)
1056 * This is considered a slow path. It is not used by most libc
1057 * implementations on modern hardware except during process startup.
1060 * eax system call number
1068 SYM_FUNC_START(entry_INT80_32)
1070 pushl %eax /* pt_regs->orig_ax */
1072 SAVE_ALL pt_regs_ax=$-ENOSYS switch_stacks=1 /* save rest */
1075 call do_int80_syscall_32
1079 restore_all_switch_stack:
1080 SWITCH_TO_ENTRY_STACK
1081 CHECK_AND_APPLY_ESPFIX
1083 /* Switch back to user CR3 */
1084 SWITCH_TO_USER_CR3 scratch_reg=%eax
1088 /* Restore user state */
1089 RESTORE_REGS pop=4 # skip orig_eax/error_code
1092 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
1093 * when returning from IPI handler and when returning from
1094 * scheduler to user-space.
1098 .section .fixup, "ax"
1099 SYM_CODE_START(asm_iret_error)
1100 pushl $0 # no error code
1103 #ifdef CONFIG_DEBUG_ENTRY
1105 * The stack-frame here is the one that iret faulted on, so its a
1106 * return-to-user frame. We are on kernel-cr3 because we come here from
1107 * the fixup code. This confuses the CR3 checker, so switch to user-cr3
1108 * as the checker expects it.
1111 SWITCH_TO_USER_CR3 scratch_reg=%eax
1115 jmp handle_exception
1116 SYM_CODE_END(asm_iret_error)
1118 _ASM_EXTABLE(.Lirq_return, asm_iret_error)
1119 SYM_FUNC_END(entry_INT80_32)
1121 .macro FIXUP_ESPFIX_STACK
1123 * Switch back for ESPFIX stack to the normal zerobased stack
1125 * We can't call C functions using the ESPFIX stack. This code reads
1126 * the high word of the segment base from the GDT and swiches to the
1127 * normal stack and adjusts ESP with the matching offset.
1129 * We might be on user CR3 here, so percpu data is not mapped and we can't
1130 * access the GDT through the percpu segment. Instead, use SGDT to find
1131 * the cpu_entry_area alias of the GDT.
1133 #ifdef CONFIG_X86_ESPFIX32
1134 /* fixup the stack */
1138 movl 2(%esp), %ecx /* GDT address */
1140 * Careful: ECX is a linear pointer, so we need to force base
1141 * zero. %cs is the only known-linear segment we have right now.
1143 mov %cs:GDT_ESPFIX_OFFSET + 4(%ecx), %al /* bits 16..23 */
1144 mov %cs:GDT_ESPFIX_OFFSET + 7(%ecx), %ah /* bits 24..31 */
1148 addl %esp, %eax /* the adjusted stack pointer */
1151 lss (%esp), %esp /* switch to the normal stack segment */
1155 .macro UNWIND_ESPFIX_STACK
1156 /* It's safe to clobber %eax, all other regs need to be preserved */
1157 #ifdef CONFIG_X86_ESPFIX32
1159 /* see if on espfix stack */
1160 cmpw $__ESPFIX_SS, %ax
1162 /* switch to normal stack */
1168 #ifdef CONFIG_PARAVIRT
1169 SYM_CODE_START(native_iret)
1171 _ASM_EXTABLE(native_iret, asm_iret_error)
1172 SYM_CODE_END(native_iret)
1175 #ifdef CONFIG_XEN_PV
1177 * See comment in entry_64.S for further explanation
1179 * Note: This is not an actual IDT entry point. It's a XEN specific entry
1180 * point and therefore named to match the 64-bit trampoline counterpart.
1182 SYM_FUNC_START(xen_asm_exc_xen_hypervisor_callback)
1184 * Check to see if we got the event in the critical
1185 * region in xen_iret_direct, after we've reenabled
1186 * events and checked for pending events. This simulates
1187 * iret instruction's behaviour where it delivers a
1188 * pending interrupt when enabling interrupts:
1190 cmpl $xen_iret_start_crit, (%esp)
1192 cmpl $xen_iret_end_crit, (%esp)
1194 call xen_iret_crit_fixup
1196 pushl $-1 /* orig_ax = -1 => not a system call */
1198 ENCODE_FRAME_POINTER
1201 call xen_pv_evtchn_do_upcall
1202 jmp handle_exception_return
1203 SYM_FUNC_END(xen_asm_exc_xen_hypervisor_callback)
1206 * Hypervisor uses this for application faults while it executes.
1207 * We get here for two reasons:
1208 * 1. Fault while reloading DS, ES, FS or GS
1209 * 2. Fault while executing IRET
1210 * Category 1 we fix up by reattempting the load, and zeroing the segment
1211 * register if the load fails.
1212 * Category 2 we fix up by jumping to do_iret_error. We cannot use the
1213 * normal Linux return path in this case because if we use the IRET hypercall
1214 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
1215 * We distinguish between categories by maintaining a status value in EAX.
1217 SYM_FUNC_START(xen_failsafe_callback)
1222 3: mov 12(%esp), %fs
1223 4: mov 16(%esp), %gs
1224 /* EAX == 0 => Category 1 (Bad segment)
1225 EAX != 0 => Category 2 (Bad IRET) */
1231 5: pushl $-1 /* orig_ax = -1 => not a system call */
1233 ENCODE_FRAME_POINTER
1234 jmp handle_exception_return
1236 .section .fixup, "ax"
1250 _ASM_EXTABLE(1b, 6b)
1251 _ASM_EXTABLE(2b, 7b)
1252 _ASM_EXTABLE(3b, 8b)
1253 _ASM_EXTABLE(4b, 9b)
1254 SYM_FUNC_END(xen_failsafe_callback)
1255 #endif /* CONFIG_XEN_PV */
1257 SYM_CODE_START_LOCAL_NOALIGN(handle_exception)
1258 /* the function address is in %gs's slot on the stack */
1259 SAVE_ALL switch_stacks=1 skip_gs=1 unwind_espfix=1
1260 ENCODE_FRAME_POINTER
1264 movl PT_GS(%esp), %edi # get the function address
1268 /* fixup orig %eax */
1269 movl PT_ORIG_EAX(%esp), %edx # get the error code
1270 movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart
1272 movl %esp, %eax # pt_regs pointer
1275 handle_exception_return:
1277 movl PT_EFLAGS(%esp), %eax # mix EFLAGS and CS
1278 movb PT_CS(%esp), %al
1279 andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %eax
1282 * We can be coming here from child spawned by kernel_thread().
1284 movl PT_CS(%esp), %eax
1285 andl $SEGMENT_RPL_MASK, %eax
1287 cmpl $USER_RPL, %eax # returning to v8086 or userspace ?
1290 PARANOID_EXIT_TO_KERNEL_MODE
1297 jmp restore_all_switch_stack
1298 SYM_CODE_END(handle_exception)
1300 SYM_CODE_START(asm_exc_double_fault)
1303 * This is a task gate handler, not an interrupt gate handler.
1304 * The error code is on the stack, but the stack is otherwise
1305 * empty. Interrupts are off. Our state is sane with the following
1308 * - CR0.TS is set. "TS" literally means "task switched".
1309 * - EFLAGS.NT is set because we're a "nested task".
1310 * - The doublefault TSS has back_link set and has been marked busy.
1311 * - TR points to the doublefault TSS and the normal TSS is busy.
1312 * - CR3 is the normal kernel PGD. This would be delightful, except
1313 * that the CPU didn't bother to save the old CR3 anywhere. This
1314 * would make it very awkward to return back to the context we came
1317 * The rest of EFLAGS is sanitized for us, so we don't need to
1318 * worry about AC or DF.
1320 * Don't even bother popping the error code. It's always zero,
1321 * and ignoring it makes us a bit more robust against buggy
1322 * hypervisor task gate implementations.
1324 * We will manually undo the task switch instead of doing a
1325 * task-switching IRET.
1328 clts /* clear CR0.TS */
1329 pushl $X86_EFLAGS_FIXED
1330 popfl /* clear EFLAGS.NT */
1332 call doublefault_shim
1334 /* We don't support returning, so we have no IRET here. */
1338 SYM_CODE_END(asm_exc_double_fault)
1341 * NMI is doubly nasty. It can happen on the first instruction of
1342 * entry_SYSENTER_32 (just like #DB), but it can also interrupt the beginning
1343 * of the #DB handler even if that #DB in turn hit before entry_SYSENTER_32
1344 * switched stacks. We handle both conditions by simply checking whether we
1345 * interrupted kernel code running on the SYSENTER stack.
1347 SYM_CODE_START(asm_exc_nmi)
1350 #ifdef CONFIG_X86_ESPFIX32
1352 * ESPFIX_SS is only ever set on the return to user path
1353 * after we've switched to the entry stack.
1357 cmpw $__ESPFIX_SS, %ax
1359 je .Lnmi_espfix_stack
1362 pushl %eax # pt_regs->orig_ax
1363 SAVE_ALL_NMI cr3_reg=%edi
1364 ENCODE_FRAME_POINTER
1365 xorl %edx, %edx # zero error code
1366 movl %esp, %eax # pt_regs pointer
1368 /* Are we currently on the SYSENTER stack? */
1369 movl PER_CPU_VAR(cpu_entry_area), %ecx
1370 addl $CPU_ENTRY_AREA_entry_stack + SIZEOF_entry_stack, %ecx
1371 subl %eax, %ecx /* ecx = (end of entry_stack) - esp */
1372 cmpl $SIZEOF_entry_stack, %ecx
1373 jb .Lnmi_from_sysenter_stack
1375 /* Not on SYSENTER stack. */
1379 .Lnmi_from_sysenter_stack:
1381 * We're on the SYSENTER stack. Switch off. No one (not even debug)
1382 * is using the thread stack right now, so it's safe for us to use it.
1385 movl PER_CPU_VAR(cpu_current_top_of_stack), %esp
1390 #ifdef CONFIG_X86_ESPFIX32
1391 testl $CS_FROM_ESPFIX, PT_CS(%esp)
1392 jnz .Lnmi_from_espfix
1395 CHECK_AND_APPLY_ESPFIX
1396 RESTORE_ALL_NMI cr3_reg=%edi pop=4
1399 #ifdef CONFIG_X86_ESPFIX32
1402 * Create the pointer to LSS back
1408 /* Copy the (short) IRET frame */
1409 pushl 4*4(%esp) # flags
1410 pushl 4*4(%esp) # cs
1411 pushl 4*4(%esp) # ip
1413 pushl %eax # orig_ax
1415 SAVE_ALL_NMI cr3_reg=%edi unwind_espfix=1
1416 ENCODE_FRAME_POINTER
1418 /* clear CS_FROM_KERNEL, set CS_FROM_ESPFIX */
1419 xorl $(CS_FROM_ESPFIX | CS_FROM_KERNEL), PT_CS(%esp)
1421 xorl %edx, %edx # zero error code
1422 movl %esp, %eax # pt_regs pointer
1423 jmp .Lnmi_from_sysenter_stack
1426 RESTORE_ALL_NMI cr3_reg=%edi
1428 * Because we cleared CS_FROM_KERNEL, IRET_FRAME 'forgot' to
1429 * fix up the gap and long frame:
1431 * 3 - original frame (exception)
1432 * 2 - ESPFIX block (above)
1433 * 6 - gap (FIXUP_FRAME)
1434 * 5 - long frame (FIXUP_FRAME)
1437 lss (1+5+6)*4(%esp), %esp # back to espfix stack
1440 SYM_CODE_END(asm_exc_nmi)
1442 .pushsection .text, "ax"
1443 SYM_CODE_START(rewind_stack_do_exit)
1444 /* Prevent any naive code from trying to unwind to our caller. */
1447 movl PER_CPU_VAR(cpu_current_top_of_stack), %esi
1448 leal -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%esi), %esp
1452 SYM_CODE_END(rewind_stack_do_exit)