1 /* SPDX-License-Identifier: GPL-2.0 */
2 #include <linux/jump_label.h>
3 #include <asm/unwind_hints.h>
4 #include <asm/cpufeatures.h>
5 #include <asm/page_types.h>
6 #include <asm/percpu.h>
7 #include <asm/asm-offsets.h>
8 #include <asm/processor-flags.h>
13 x86 function call convention, 64-bit:
14 -------------------------------------
15 arguments | callee-saved | extra caller-saved | return
16 [callee-clobbered] | | [callee-clobbered] |
17 ---------------------------------------------------------------------------
18 rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11 | rax, rdx [**]
20 ( rsp is obviously invariant across normal function calls. (gcc can 'merge'
21 functions when it sees tail-call optimization possibilities) rflags is
22 clobbered. Leftover arguments are passed over the stack frame.)
24 [*] In the frame-pointers case rbp is fixed to the stack frame.
26 [**] for struct return values wider than 64 bits the return convention is a
27 bit more complex: up to 128 bits width we return small structures
28 straight in rax, rdx. For structures larger than that (3 words or
29 larger) the caller puts a pointer to an on-stack return struct
30 [allocated in the caller's stack frame] into the first argument - i.e.
31 into rdi. All other arguments shift up by one in this case.
32 Fortunately this case is rare in the kernel.
34 For 32-bit we have the following conventions - kernel is built with
35 -mregparm=3 and -freg-struct-return:
37 x86 function calling convention, 32-bit:
38 ----------------------------------------
39 arguments | callee-saved | extra caller-saved | return
40 [callee-clobbered] | | [callee-clobbered] |
41 -------------------------------------------------------------------------
42 eax edx ecx | ebx edi esi ebp [*] | <none> | eax, edx [**]
44 ( here too esp is obviously invariant across normal function calls. eflags
45 is clobbered. Leftover arguments are passed over the stack frame. )
47 [*] In the frame-pointers case ebp is fixed to the stack frame.
49 [**] We build with -freg-struct-return, which on 32-bit means similar
50 semantics as on 64-bit: edx can be used for a second return value
51 (i.e. covering integer and structure sizes up to 64 bits) - after that
52 it gets more complex and more expensive: 3-word or larger struct returns
53 get done in the caller's frame and the pointer to the return struct goes
54 into regparm0, i.e. eax - the other arguments shift up and the
55 function's register parameters degenerate to regparm=2 in essence.
62 * 64-bit system call stack frame layout defines and helpers,
66 /* The layout forms the "struct pt_regs" on the stack: */
68 * C ABI says these regs are callee-preserved. They aren't saved on kernel entry
69 * unless syscall needs a complete, fully filled "struct pt_regs".
77 /* These regs are callee-clobbered. Always saved on kernel entry. */
88 * On syscall entry, this is syscall#. On CPU exception, this is error code.
89 * On hw interrupt, it's IRQ number:
92 /* Return frame for iretq */
99 #define SIZEOF_PTREGS 21*8
101 .macro PUSH_AND_CLEAR_REGS rdx=%rdx rax=%rax save_ret=0
103 pushq %rsi /* pt_regs->si */
104 movq 8(%rsp), %rsi /* temporarily store the return address in %rsi */
105 movq %rdi, 8(%rsp) /* pt_regs->di (overwriting original return address) */
107 pushq %rdi /* pt_regs->di */
108 pushq %rsi /* pt_regs->si */
110 pushq \rdx /* pt_regs->dx */
111 pushq %rcx /* pt_regs->cx */
112 pushq \rax /* pt_regs->ax */
113 pushq %r8 /* pt_regs->r8 */
114 pushq %r9 /* pt_regs->r9 */
115 pushq %r10 /* pt_regs->r10 */
116 pushq %r11 /* pt_regs->r11 */
117 pushq %rbx /* pt_regs->rbx */
118 pushq %rbp /* pt_regs->rbp */
119 pushq %r12 /* pt_regs->r12 */
120 pushq %r13 /* pt_regs->r13 */
121 pushq %r14 /* pt_regs->r14 */
122 pushq %r15 /* pt_regs->r15 */
126 pushq %rsi /* return address on top of stack */
130 * Sanitize registers of values that a speculation attack might
131 * otherwise want to exploit. The lower registers are likely clobbered
132 * well before they could be put to use in a speculative execution
135 xorl %edx, %edx /* nospec dx */
136 xorl %ecx, %ecx /* nospec cx */
137 xorl %r8d, %r8d /* nospec r8 */
138 xorl %r9d, %r9d /* nospec r9 */
139 xorl %r10d, %r10d /* nospec r10 */
140 xorl %r11d, %r11d /* nospec r11 */
141 xorl %ebx, %ebx /* nospec rbx */
142 xorl %ebp, %ebp /* nospec rbp */
143 xorl %r12d, %r12d /* nospec r12 */
144 xorl %r13d, %r13d /* nospec r13 */
145 xorl %r14d, %r14d /* nospec r14 */
146 xorl %r15d, %r15d /* nospec r15 */
150 .macro POP_REGS pop_rdi=1 skip_r11rcx=0
178 #ifdef CONFIG_PAGE_TABLE_ISOLATION
181 * PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two
184 #define PTI_USER_PGTABLE_BIT PAGE_SHIFT
185 #define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT)
186 #define PTI_USER_PCID_BIT X86_CR3_PTI_PCID_USER_BIT
187 #define PTI_USER_PCID_MASK (1 << PTI_USER_PCID_BIT)
188 #define PTI_USER_PGTABLE_AND_PCID_MASK (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK)
190 .macro SET_NOFLUSH_BIT reg:req
191 bts $X86_CR3_PCID_NOFLUSH_BIT, \reg
194 .macro ADJUST_KERNEL_CR3 reg:req
195 ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID
196 /* Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */
197 andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg
200 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
201 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
202 mov %cr3, \scratch_reg
203 ADJUST_KERNEL_CR3 \scratch_reg
204 mov \scratch_reg, %cr3
208 #define THIS_CPU_user_pcid_flush_mask \
209 PER_CPU_VAR(cpu_tlbstate) + TLB_STATE_user_pcid_flush_mask
211 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
212 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
213 mov %cr3, \scratch_reg
215 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
218 * Test if the ASID needs a flush.
220 movq \scratch_reg, \scratch_reg2
221 andq $(0x7FF), \scratch_reg /* mask ASID */
222 bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
225 /* Flush needed, clear the bit */
226 btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
227 movq \scratch_reg2, \scratch_reg
231 movq \scratch_reg2, \scratch_reg
232 SET_NOFLUSH_BIT \scratch_reg
235 /* Flip the ASID to the user version */
236 orq $(PTI_USER_PCID_MASK), \scratch_reg
239 /* Flip the PGD to the user version */
240 orq $(PTI_USER_PGTABLE_MASK), \scratch_reg
241 mov \scratch_reg, %cr3
245 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
247 SWITCH_TO_USER_CR3_NOSTACK scratch_reg=\scratch_reg scratch_reg2=%rax
251 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
252 ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI
253 movq %cr3, \scratch_reg
254 movq \scratch_reg, \save_reg
256 * Test the user pagetable bit. If set, then the user page tables
257 * are active. If clear CR3 already has the kernel page table
260 bt $PTI_USER_PGTABLE_BIT, \scratch_reg
263 ADJUST_KERNEL_CR3 \scratch_reg
264 movq \scratch_reg, %cr3
269 .macro RESTORE_CR3 scratch_reg:req save_reg:req
270 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
272 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
275 * KERNEL pages can always resume with NOFLUSH as we do
278 bt $PTI_USER_PGTABLE_BIT, \save_reg
282 * Check if there's a pending flush for the user ASID we're
285 movq \save_reg, \scratch_reg
286 andq $(0x7FF), \scratch_reg
287 bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
290 btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
294 SET_NOFLUSH_BIT \save_reg
298 * The CR3 write could be avoided when not changing its value,
299 * but would require a CR3 read *and* a scratch register.
305 #else /* CONFIG_PAGE_TABLE_ISOLATION=n: */
307 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
309 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
311 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
313 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
315 .macro RESTORE_CR3 scratch_reg:req save_reg:req
321 * Mitigate Spectre v1 for conditional swapgs code paths.
323 * FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to
324 * prevent a speculative swapgs when coming from kernel space.
326 * FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path,
327 * to prevent the swapgs from getting speculatively skipped when coming from
330 .macro FENCE_SWAPGS_USER_ENTRY
331 ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER
333 .macro FENCE_SWAPGS_KERNEL_ENTRY
334 ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL
337 .macro STACKLEAK_ERASE_NOCLOBBER
338 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
345 .macro SAVE_AND_SET_GSBASE scratch_reg:req save_reg:req
347 GET_PERCPU_BASE \scratch_reg
348 wrgsbase \scratch_reg
351 #else /* CONFIG_X86_64 */
352 # undef UNWIND_HINT_IRET_REGS
353 # define UNWIND_HINT_IRET_REGS
354 #endif /* !CONFIG_X86_64 */
356 .macro STACKLEAK_ERASE
357 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
365 * CPU/node NR is loaded from the limit (size) field of a special segment
366 * descriptor entry in GDT.
368 .macro LOAD_CPU_AND_NODE_SEG_LIMIT reg:req
369 movq $__CPUNODE_SEG, \reg
374 * Fetch the per-CPU GSBASE value for this processor and put it in @reg.
375 * We normally use %gs for accessing per-CPU data, but we are setting up
376 * %gs here and obviously can not use %gs itself to access per-CPU data.
378 .macro GET_PERCPU_BASE reg:req
380 "LOAD_CPU_AND_NODE_SEG_LIMIT \reg", \
383 andq $VDSO_CPUNODE_MASK, \reg
384 movq __per_cpu_offset(, \reg, 8), \reg
389 .macro GET_PERCPU_BASE reg:req
390 movq pcpu_unit_offsets(%rip), \reg
393 #endif /* CONFIG_SMP */