1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/config.h>
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
16 #include <linux/hugetlb.h>
17 #include <linux/slab.h>
18 #include <linux/initrd.h>
19 #include <linux/swap.h>
20 #include <linux/pagemap.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
28 #include <asm/system.h>
30 #include <asm/pgalloc.h>
31 #include <asm/pgtable.h>
32 #include <asm/oplib.h>
33 #include <asm/iommu.h>
35 #include <asm/uaccess.h>
36 #include <asm/mmu_context.h>
37 #include <asm/tlbflush.h>
39 #include <asm/starfire.h>
41 #include <asm/spitfire.h>
42 #include <asm/sections.h>
44 #include <asm/hypervisor.h>
46 extern void device_scan(void);
48 #define MAX_PHYS_ADDRESS (1UL << 42UL)
49 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
50 #define KPTE_BITMAP_BYTES \
51 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
53 unsigned long kern_linear_pte_xor[2] __read_mostly;
55 /* A bitmap, one bit for every 256MB of physical memory. If the bit
56 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
57 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
59 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
61 /* A special kernel TSB for 4MB and 256MB linear mappings. */
62 struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
66 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
67 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
68 static int pavail_ents __initdata;
69 static int pavail_rescan_ents __initdata;
71 static int cmp_p64(const void *a, const void *b)
73 const struct linux_prom64_registers *x = a, *y = b;
75 if (x->phys_addr > y->phys_addr)
77 if (x->phys_addr < y->phys_addr)
82 static void __init read_obp_memory(const char *property,
83 struct linux_prom64_registers *regs,
86 int node = prom_finddevice("/memory");
87 int prop_size = prom_getproplen(node, property);
90 ents = prop_size / sizeof(struct linux_prom64_registers);
91 if (ents > MAX_BANKS) {
92 prom_printf("The machine has more %s property entries than "
93 "this kernel can support (%d).\n",
98 ret = prom_getproperty(node, property, (char *) regs, prop_size);
100 prom_printf("Couldn't get %s property from /memory.\n");
106 /* Sanitize what we got from the firmware, by page aligning
109 for (i = 0; i < ents; i++) {
110 unsigned long base, size;
112 base = regs[i].phys_addr;
113 size = regs[i].reg_size;
116 if (base & ~PAGE_MASK) {
117 unsigned long new_base = PAGE_ALIGN(base);
119 size -= new_base - base;
120 if ((long) size < 0L)
124 regs[i].phys_addr = base;
125 regs[i].reg_size = size;
127 sort(regs, ents, sizeof(struct linux_prom64_registers),
131 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
133 /* Ugly, but necessary... -DaveM */
134 unsigned long phys_base __read_mostly;
135 unsigned long kern_base __read_mostly;
136 unsigned long kern_size __read_mostly;
137 unsigned long pfn_base __read_mostly;
139 /* get_new_mmu_context() uses "cache + 1". */
140 DEFINE_SPINLOCK(ctx_alloc_lock);
141 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
142 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
143 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
145 /* References to special section boundaries */
146 extern char _start[], _end[];
148 /* Initial ramdisk setup */
149 extern unsigned long sparc_ramdisk_image64;
150 extern unsigned int sparc_ramdisk_image;
151 extern unsigned int sparc_ramdisk_size;
153 struct page *mem_map_zero __read_mostly;
155 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
157 unsigned long sparc64_kern_pri_context __read_mostly;
158 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
159 unsigned long sparc64_kern_sec_context __read_mostly;
163 kmem_cache_t *pgtable_cache __read_mostly;
165 static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
170 void pgtable_cache_init(void)
172 pgtable_cache = kmem_cache_create("pgtable_cache",
173 PAGE_SIZE, PAGE_SIZE,
175 SLAB_MUST_HWCACHE_ALIGN,
178 if (!pgtable_cache) {
179 prom_printf("pgtable_cache_init(): Could not create!\n");
184 #ifdef CONFIG_DEBUG_DCFLUSH
185 atomic_t dcpage_flushes = ATOMIC_INIT(0);
187 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
191 inline void flush_dcache_page_impl(struct page *page)
193 BUG_ON(tlb_type == hypervisor);
194 #ifdef CONFIG_DEBUG_DCFLUSH
195 atomic_inc(&dcpage_flushes);
198 #ifdef DCACHE_ALIASING_POSSIBLE
199 __flush_dcache_page(page_address(page),
200 ((tlb_type == spitfire) &&
201 page_mapping(page) != NULL));
203 if (page_mapping(page) != NULL &&
204 tlb_type == spitfire)
205 __flush_icache_page(__pa(page_address(page)));
209 #define PG_dcache_dirty PG_arch_1
210 #define PG_dcache_cpu_shift 24
211 #define PG_dcache_cpu_mask (256 - 1)
214 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
217 #define dcache_dirty_cpu(page) \
218 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
220 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
222 unsigned long mask = this_cpu;
223 unsigned long non_cpu_bits;
225 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
226 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
228 __asm__ __volatile__("1:\n\t"
230 "and %%g7, %1, %%g1\n\t"
231 "or %%g1, %0, %%g1\n\t"
232 "casx [%2], %%g7, %%g1\n\t"
234 "membar #StoreLoad | #StoreStore\n\t"
235 "bne,pn %%xcc, 1b\n\t"
238 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
242 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
244 unsigned long mask = (1UL << PG_dcache_dirty);
246 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
249 "srlx %%g7, %4, %%g1\n\t"
250 "and %%g1, %3, %%g1\n\t"
252 "bne,pn %%icc, 2f\n\t"
253 " andn %%g7, %1, %%g1\n\t"
254 "casx [%2], %%g7, %%g1\n\t"
256 "membar #StoreLoad | #StoreStore\n\t"
257 "bne,pn %%xcc, 1b\n\t"
261 : "r" (cpu), "r" (mask), "r" (&page->flags),
262 "i" (PG_dcache_cpu_mask),
263 "i" (PG_dcache_cpu_shift)
267 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
269 unsigned long tsb_addr = (unsigned long) ent;
271 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
272 tsb_addr = __pa(tsb_addr);
274 __tsb_insert(tsb_addr, tag, pte);
277 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
278 unsigned long _PAGE_SZBITS __read_mostly;
280 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
282 struct mm_struct *mm;
284 if (tlb_type != hypervisor) {
285 unsigned long pfn = pte_pfn(pte);
286 unsigned long pg_flags;
289 if (pfn_valid(pfn) &&
290 (page = pfn_to_page(pfn), page_mapping(page)) &&
291 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
292 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
294 int this_cpu = get_cpu();
296 /* This is just to optimize away some function calls
300 flush_dcache_page_impl(page);
302 smp_flush_dcache_page_impl(page, cpu);
304 clear_dcache_dirty_cpu(page, cpu);
311 if ((pte_val(pte) & _PAGE_ALL_SZ_BITS) == _PAGE_SZBITS) {
315 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
316 (mm->context.tsb_nentries - 1UL)];
317 tag = (address >> 22UL);
318 tsb_insert(tsb, tag, pte_val(pte));
322 void flush_dcache_page(struct page *page)
324 struct address_space *mapping;
327 if (tlb_type == hypervisor)
330 /* Do not bother with the expensive D-cache flush if it
331 * is merely the zero page. The 'bigcore' testcase in GDB
332 * causes this case to run millions of times.
334 if (page == ZERO_PAGE(0))
337 this_cpu = get_cpu();
339 mapping = page_mapping(page);
340 if (mapping && !mapping_mapped(mapping)) {
341 int dirty = test_bit(PG_dcache_dirty, &page->flags);
343 int dirty_cpu = dcache_dirty_cpu(page);
345 if (dirty_cpu == this_cpu)
347 smp_flush_dcache_page_impl(page, dirty_cpu);
349 set_dcache_dirty(page, this_cpu);
351 /* We could delay the flush for the !page_mapping
352 * case too. But that case is for exec env/arg
353 * pages and those are %99 certainly going to get
354 * faulted into the tlb (and thus flushed) anyways.
356 flush_dcache_page_impl(page);
363 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
365 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
366 if (tlb_type == spitfire) {
369 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
370 __flush_icache_page(__get_phys(kaddr));
374 unsigned long page_to_pfn(struct page *page)
376 return (unsigned long) ((page - mem_map) + pfn_base);
379 struct page *pfn_to_page(unsigned long pfn)
381 return (mem_map + (pfn - pfn_base));
386 printk("Mem-info:\n");
388 printk("Free swap: %6ldkB\n",
389 nr_swap_pages << (PAGE_SHIFT-10));
390 printk("%ld pages of RAM\n", num_physpages);
391 printk("%d free pages\n", nr_free_pages());
394 void mmu_info(struct seq_file *m)
396 if (tlb_type == cheetah)
397 seq_printf(m, "MMU Type\t: Cheetah\n");
398 else if (tlb_type == cheetah_plus)
399 seq_printf(m, "MMU Type\t: Cheetah+\n");
400 else if (tlb_type == spitfire)
401 seq_printf(m, "MMU Type\t: Spitfire\n");
402 else if (tlb_type == hypervisor)
403 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
405 seq_printf(m, "MMU Type\t: ???\n");
407 #ifdef CONFIG_DEBUG_DCFLUSH
408 seq_printf(m, "DCPageFlushes\t: %d\n",
409 atomic_read(&dcpage_flushes));
411 seq_printf(m, "DCPageFlushesXC\t: %d\n",
412 atomic_read(&dcpage_flushes_xcall));
413 #endif /* CONFIG_SMP */
414 #endif /* CONFIG_DEBUG_DCFLUSH */
417 struct linux_prom_translation {
423 /* Exported for kernel TLB miss handling in ktlb.S */
424 struct linux_prom_translation prom_trans[512] __read_mostly;
425 unsigned int prom_trans_ents __read_mostly;
427 /* Exported for SMP bootup purposes. */
428 unsigned long kern_locked_tte_data;
430 /* The obp translations are saved based on 8k pagesize, since obp can
431 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
432 * HI_OBP_ADDRESS range are handled in ktlb.S.
434 static inline int in_obp_range(unsigned long vaddr)
436 return (vaddr >= LOW_OBP_ADDRESS &&
437 vaddr < HI_OBP_ADDRESS);
440 static int cmp_ptrans(const void *a, const void *b)
442 const struct linux_prom_translation *x = a, *y = b;
444 if (x->virt > y->virt)
446 if (x->virt < y->virt)
451 /* Read OBP translations property into 'prom_trans[]'. */
452 static void __init read_obp_translations(void)
454 int n, node, ents, first, last, i;
456 node = prom_finddevice("/virtual-memory");
457 n = prom_getproplen(node, "translations");
458 if (unlikely(n == 0 || n == -1)) {
459 prom_printf("prom_mappings: Couldn't get size.\n");
462 if (unlikely(n > sizeof(prom_trans))) {
463 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
467 if ((n = prom_getproperty(node, "translations",
468 (char *)&prom_trans[0],
469 sizeof(prom_trans))) == -1) {
470 prom_printf("prom_mappings: Couldn't get property.\n");
474 n = n / sizeof(struct linux_prom_translation);
478 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
481 /* Now kick out all the non-OBP entries. */
482 for (i = 0; i < ents; i++) {
483 if (in_obp_range(prom_trans[i].virt))
487 for (; i < ents; i++) {
488 if (!in_obp_range(prom_trans[i].virt))
493 for (i = 0; i < (last - first); i++) {
494 struct linux_prom_translation *src = &prom_trans[i + first];
495 struct linux_prom_translation *dest = &prom_trans[i];
499 for (; i < ents; i++) {
500 struct linux_prom_translation *dest = &prom_trans[i];
501 dest->virt = dest->size = dest->data = 0x0UL;
504 prom_trans_ents = last - first;
506 if (tlb_type == spitfire) {
507 /* Clear diag TTE bits. */
508 for (i = 0; i < prom_trans_ents; i++)
509 prom_trans[i].data &= ~0x0003fe0000000000UL;
513 static void __init hypervisor_tlb_lock(unsigned long vaddr,
517 register unsigned long func asm("%o5");
518 register unsigned long arg0 asm("%o0");
519 register unsigned long arg1 asm("%o1");
520 register unsigned long arg2 asm("%o2");
521 register unsigned long arg3 asm("%o3");
523 func = HV_FAST_MMU_MAP_PERM_ADDR;
528 __asm__ __volatile__("ta 0x80"
529 : "=&r" (func), "=&r" (arg0),
530 "=&r" (arg1), "=&r" (arg2),
532 : "0" (func), "1" (arg0), "2" (arg1),
533 "3" (arg2), "4" (arg3));
535 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
536 "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
541 static unsigned long kern_large_tte(unsigned long paddr);
543 static void __init remap_kernel(void)
545 unsigned long phys_page, tte_vaddr, tte_data;
546 int tlb_ent = sparc64_highest_locked_tlbent();
548 tte_vaddr = (unsigned long) KERNBASE;
549 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
550 tte_data = kern_large_tte(phys_page);
552 kern_locked_tte_data = tte_data;
554 /* Now lock us into the TLBs via Hypervisor or OBP. */
555 if (tlb_type == hypervisor) {
556 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
557 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
559 tte_vaddr += 0x400000;
560 tte_data += 0x400000;
561 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
562 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
565 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
566 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
569 prom_dtlb_load(tlb_ent,
571 tte_vaddr + 0x400000);
572 prom_itlb_load(tlb_ent,
574 tte_vaddr + 0x400000);
576 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
578 if (tlb_type == cheetah_plus) {
579 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
580 CTX_CHEETAH_PLUS_NUC);
581 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
582 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
587 static void __init inherit_prom_mappings(void)
589 read_obp_translations();
591 /* Now fixup OBP's idea about where we really are mapped. */
592 prom_printf("Remapping the kernel... ");
594 prom_printf("done.\n");
597 void prom_world(int enter)
600 set_fs((mm_segment_t) { get_thread_current_ds() });
602 __asm__ __volatile__("flushw");
605 #ifdef DCACHE_ALIASING_POSSIBLE
606 void __flush_dcache_range(unsigned long start, unsigned long end)
610 if (tlb_type == spitfire) {
613 for (va = start; va < end; va += 32) {
614 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
618 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
621 for (va = start; va < end; va += 32)
622 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
626 "i" (ASI_DCACHE_INVALIDATE));
629 #endif /* DCACHE_ALIASING_POSSIBLE */
631 /* Caller does TLB context flushing on local CPU if necessary.
632 * The caller also ensures that CTX_VALID(mm->context) is false.
634 * We must be careful about boundary cases so that we never
635 * let the user have CTX 0 (nucleus) or we ever use a CTX
636 * version of zero (and thus NO_CONTEXT would not be caught
637 * by version mis-match tests in mmu_context.h).
639 * Always invoked with interrupts disabled.
641 void get_new_mmu_context(struct mm_struct *mm)
643 unsigned long ctx, new_ctx;
644 unsigned long orig_pgsz_bits;
647 spin_lock(&ctx_alloc_lock);
648 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
649 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
650 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
652 if (new_ctx >= (1 << CTX_NR_BITS)) {
653 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
654 if (new_ctx >= ctx) {
656 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
659 new_ctx = CTX_FIRST_VERSION;
661 /* Don't call memset, for 16 entries that's just
664 mmu_context_bmap[0] = 3;
665 mmu_context_bmap[1] = 0;
666 mmu_context_bmap[2] = 0;
667 mmu_context_bmap[3] = 0;
668 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
669 mmu_context_bmap[i + 0] = 0;
670 mmu_context_bmap[i + 1] = 0;
671 mmu_context_bmap[i + 2] = 0;
672 mmu_context_bmap[i + 3] = 0;
678 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
679 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
681 tlb_context_cache = new_ctx;
682 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
683 spin_unlock(&ctx_alloc_lock);
685 if (unlikely(new_version))
686 smp_new_mmu_context_version();
689 void sparc_ultra_dump_itlb(void)
693 if (tlb_type == spitfire) {
694 printk ("Contents of itlb: ");
695 for (slot = 0; slot < 14; slot++) printk (" ");
696 printk ("%2x:%016lx,%016lx\n",
698 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
699 for (slot = 1; slot < 64; slot+=3) {
700 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
702 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
704 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
706 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
708 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
709 printk ("Contents of itlb0:\n");
710 for (slot = 0; slot < 16; slot+=2) {
711 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
713 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
715 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
717 printk ("Contents of itlb2:\n");
718 for (slot = 0; slot < 128; slot+=2) {
719 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
721 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
723 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
728 void sparc_ultra_dump_dtlb(void)
732 if (tlb_type == spitfire) {
733 printk ("Contents of dtlb: ");
734 for (slot = 0; slot < 14; slot++) printk (" ");
735 printk ("%2x:%016lx,%016lx\n", 0,
736 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
737 for (slot = 1; slot < 64; slot+=3) {
738 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
740 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
742 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
744 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
746 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
747 printk ("Contents of dtlb0:\n");
748 for (slot = 0; slot < 16; slot+=2) {
749 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
751 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
753 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
755 printk ("Contents of dtlb2:\n");
756 for (slot = 0; slot < 512; slot+=2) {
757 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
759 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
761 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
763 if (tlb_type == cheetah_plus) {
764 printk ("Contents of dtlb3:\n");
765 for (slot = 0; slot < 512; slot+=2) {
766 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
768 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
770 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
776 extern unsigned long cmdline_memory_size;
778 unsigned long __init bootmem_init(unsigned long *pages_avail)
780 unsigned long bootmap_size, start_pfn, end_pfn;
781 unsigned long end_of_phys_memory = 0UL;
782 unsigned long bootmap_pfn, bytes_avail, size;
785 #ifdef CONFIG_DEBUG_BOOTMEM
786 prom_printf("bootmem_init: Scan pavail, ");
790 for (i = 0; i < pavail_ents; i++) {
791 end_of_phys_memory = pavail[i].phys_addr +
793 bytes_avail += pavail[i].reg_size;
794 if (cmdline_memory_size) {
795 if (bytes_avail > cmdline_memory_size) {
796 unsigned long slack = bytes_avail - cmdline_memory_size;
798 bytes_avail -= slack;
799 end_of_phys_memory -= slack;
801 pavail[i].reg_size -= slack;
802 if ((long)pavail[i].reg_size <= 0L) {
803 pavail[i].phys_addr = 0xdeadbeefUL;
804 pavail[i].reg_size = 0UL;
807 pavail[i+1].reg_size = 0Ul;
808 pavail[i+1].phys_addr = 0xdeadbeefUL;
816 *pages_avail = bytes_avail >> PAGE_SHIFT;
818 /* Start with page aligned address of last symbol in kernel
819 * image. The kernel is hard mapped below PAGE_OFFSET in a
820 * 4MB locked TLB translation.
822 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
824 bootmap_pfn = start_pfn;
826 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
828 #ifdef CONFIG_BLK_DEV_INITRD
829 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
830 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
831 unsigned long ramdisk_image = sparc_ramdisk_image ?
832 sparc_ramdisk_image : sparc_ramdisk_image64;
833 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
834 ramdisk_image -= KERNBASE;
835 initrd_start = ramdisk_image + phys_base;
836 initrd_end = initrd_start + sparc_ramdisk_size;
837 if (initrd_end > end_of_phys_memory) {
838 printk(KERN_CRIT "initrd extends beyond end of memory "
839 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
840 initrd_end, end_of_phys_memory);
844 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
845 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
846 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
850 /* Initialize the boot-time allocator. */
851 max_pfn = max_low_pfn = end_pfn;
852 min_low_pfn = pfn_base;
854 #ifdef CONFIG_DEBUG_BOOTMEM
855 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
856 min_low_pfn, bootmap_pfn, max_low_pfn);
858 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
860 /* Now register the available physical memory with the
863 for (i = 0; i < pavail_ents; i++) {
864 #ifdef CONFIG_DEBUG_BOOTMEM
865 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
866 i, pavail[i].phys_addr, pavail[i].reg_size);
868 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
871 #ifdef CONFIG_BLK_DEV_INITRD
873 size = initrd_end - initrd_start;
875 /* Resert the initrd image area. */
876 #ifdef CONFIG_DEBUG_BOOTMEM
877 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
878 initrd_start, initrd_end);
880 reserve_bootmem(initrd_start, size);
881 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
883 initrd_start += PAGE_OFFSET;
884 initrd_end += PAGE_OFFSET;
887 /* Reserve the kernel text/data/bss. */
888 #ifdef CONFIG_DEBUG_BOOTMEM
889 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
891 reserve_bootmem(kern_base, kern_size);
892 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
894 /* Reserve the bootmem map. We do not account for it
895 * in pages_avail because we will release that memory
896 * in free_all_bootmem.
899 #ifdef CONFIG_DEBUG_BOOTMEM
900 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
901 (bootmap_pfn << PAGE_SHIFT), size);
903 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
904 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
909 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
910 static int pall_ents __initdata;
912 #ifdef CONFIG_DEBUG_PAGEALLOC
913 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
915 unsigned long vstart = PAGE_OFFSET + pstart;
916 unsigned long vend = PAGE_OFFSET + pend;
917 unsigned long alloc_bytes = 0UL;
919 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
920 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
925 while (vstart < vend) {
926 unsigned long this_end, paddr = __pa(vstart);
927 pgd_t *pgd = pgd_offset_k(vstart);
932 pud = pud_offset(pgd, vstart);
933 if (pud_none(*pud)) {
936 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
937 alloc_bytes += PAGE_SIZE;
938 pud_populate(&init_mm, pud, new);
941 pmd = pmd_offset(pud, vstart);
942 if (!pmd_present(*pmd)) {
945 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
946 alloc_bytes += PAGE_SIZE;
947 pmd_populate_kernel(&init_mm, pmd, new);
950 pte = pte_offset_kernel(pmd, vstart);
951 this_end = (vstart + PMD_SIZE) & PMD_MASK;
955 while (vstart < this_end) {
956 pte_val(*pte) = (paddr | pgprot_val(prot));
967 extern unsigned int kvmap_linear_patch[1];
968 #endif /* CONFIG_DEBUG_PAGEALLOC */
970 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
972 const unsigned long shift_256MB = 28;
973 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
974 const unsigned long size_256MB = (1UL << shift_256MB);
976 while (start < end) {
979 if (start & mask_256MB) {
980 start = (start + size_256MB) & ~mask_256MB;
984 remains = end - start;
985 while (remains >= size_256MB) {
986 unsigned long index = start >> shift_256MB;
988 __set_bit(index, kpte_linear_bitmap);
991 remains -= size_256MB;
996 static void __init kernel_physical_mapping_init(void)
999 #ifdef CONFIG_DEBUG_PAGEALLOC
1000 unsigned long mem_alloced = 0UL;
1003 read_obp_memory("reg", &pall[0], &pall_ents);
1005 for (i = 0; i < pall_ents; i++) {
1006 unsigned long phys_start, phys_end;
1008 phys_start = pall[i].phys_addr;
1009 phys_end = phys_start + pall[i].reg_size;
1011 mark_kpte_bitmap(phys_start, phys_end);
1013 #ifdef CONFIG_DEBUG_PAGEALLOC
1014 mem_alloced += kernel_map_range(phys_start, phys_end,
1019 #ifdef CONFIG_DEBUG_PAGEALLOC
1020 printk("Allocated %ld bytes for kernel page tables.\n",
1023 kvmap_linear_patch[0] = 0x01000000; /* nop */
1024 flushi(&kvmap_linear_patch[0]);
1030 #ifdef CONFIG_DEBUG_PAGEALLOC
1031 void kernel_map_pages(struct page *page, int numpages, int enable)
1033 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1034 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1036 kernel_map_range(phys_start, phys_end,
1037 (enable ? PAGE_KERNEL : __pgprot(0)));
1039 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1040 PAGE_OFFSET + phys_end);
1042 /* we should perform an IPI and flush all tlbs,
1043 * but that can deadlock->flush only current cpu.
1045 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1046 PAGE_OFFSET + phys_end);
1050 unsigned long __init find_ecache_flush_span(unsigned long size)
1054 for (i = 0; i < pavail_ents; i++) {
1055 if (pavail[i].reg_size >= size)
1056 return pavail[i].phys_addr;
1062 static void __init tsb_phys_patch(void)
1064 struct tsb_ldquad_phys_patch_entry *pquad;
1065 struct tsb_phys_patch_entry *p;
1067 pquad = &__tsb_ldquad_phys_patch;
1068 while (pquad < &__tsb_ldquad_phys_patch_end) {
1069 unsigned long addr = pquad->addr;
1071 if (tlb_type == hypervisor)
1072 *(unsigned int *) addr = pquad->sun4v_insn;
1074 *(unsigned int *) addr = pquad->sun4u_insn;
1076 __asm__ __volatile__("flush %0"
1083 p = &__tsb_phys_patch;
1084 while (p < &__tsb_phys_patch_end) {
1085 unsigned long addr = p->addr;
1087 *(unsigned int *) addr = p->insn;
1089 __asm__ __volatile__("flush %0"
1097 /* Don't mark as init, we give this to the Hypervisor. */
1098 static struct hv_tsb_descr ktsb_descr[2];
1099 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1101 static void __init sun4v_ktsb_init(void)
1103 unsigned long ktsb_pa;
1105 /* First KTSB for PAGE_SIZE mappings. */
1106 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1108 switch (PAGE_SIZE) {
1111 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1112 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1116 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1117 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1121 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1122 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1125 case 4 * 1024 * 1024:
1126 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1127 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1131 ktsb_descr[0].assoc = 1;
1132 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1133 ktsb_descr[0].ctx_idx = 0;
1134 ktsb_descr[0].tsb_base = ktsb_pa;
1135 ktsb_descr[0].resv = 0;
1137 /* Second KTSB for 4MB/256MB mappings. */
1138 ktsb_pa = (kern_base +
1139 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1141 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1142 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1143 HV_PGSZ_MASK_256MB);
1144 ktsb_descr[1].assoc = 1;
1145 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1146 ktsb_descr[1].ctx_idx = 0;
1147 ktsb_descr[1].tsb_base = ktsb_pa;
1148 ktsb_descr[1].resv = 0;
1151 void __cpuinit sun4v_ktsb_register(void)
1153 register unsigned long func asm("%o5");
1154 register unsigned long arg0 asm("%o0");
1155 register unsigned long arg1 asm("%o1");
1158 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1160 func = HV_FAST_MMU_TSB_CTX0;
1163 __asm__ __volatile__("ta %6"
1164 : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1165 : "0" (func), "1" (arg0), "2" (arg1),
1166 "i" (HV_FAST_TRAP));
1169 /* paging_init() sets up the page tables */
1171 extern void cheetah_ecache_flush_init(void);
1172 extern void sun4v_patch_tlb_handlers(void);
1174 static unsigned long last_valid_pfn;
1175 pgd_t swapper_pg_dir[2048];
1177 static void sun4u_pgprot_init(void);
1178 static void sun4v_pgprot_init(void);
1180 void __init paging_init(void)
1182 unsigned long end_pfn, pages_avail, shift;
1183 unsigned long real_end, i;
1185 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1186 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1188 /* Invalidate both kernel TSBs. */
1189 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1190 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1192 if (tlb_type == hypervisor)
1193 sun4v_pgprot_init();
1195 sun4u_pgprot_init();
1197 if (tlb_type == cheetah_plus ||
1198 tlb_type == hypervisor)
1201 if (tlb_type == hypervisor) {
1202 sun4v_patch_tlb_handlers();
1206 /* Find available physical memory... */
1207 read_obp_memory("available", &pavail[0], &pavail_ents);
1209 phys_base = 0xffffffffffffffffUL;
1210 for (i = 0; i < pavail_ents; i++)
1211 phys_base = min(phys_base, pavail[i].phys_addr);
1213 pfn_base = phys_base >> PAGE_SHIFT;
1215 set_bit(0, mmu_context_bmap);
1217 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1219 real_end = (unsigned long)_end;
1220 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1222 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1223 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1227 /* Set kernel pgd to upper alias so physical page computations
1230 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1232 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1234 /* Now can init the kernel/bad page tables. */
1235 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1236 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1238 inherit_prom_mappings();
1240 /* Ok, we can use our TLB miss and window trap handlers safely. */
1245 if (tlb_type == hypervisor)
1246 sun4v_ktsb_register();
1248 /* Setup bootmem... */
1250 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1252 kernel_physical_mapping_init();
1255 unsigned long zones_size[MAX_NR_ZONES];
1256 unsigned long zholes_size[MAX_NR_ZONES];
1257 unsigned long npages;
1260 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1261 zones_size[znum] = zholes_size[znum] = 0;
1263 npages = end_pfn - pfn_base;
1264 zones_size[ZONE_DMA] = npages;
1265 zholes_size[ZONE_DMA] = npages - pages_avail;
1267 free_area_init_node(0, &contig_page_data, zones_size,
1268 phys_base >> PAGE_SHIFT, zholes_size);
1274 static void __init taint_real_pages(void)
1278 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1280 /* Find changes discovered in the physmem available rescan and
1281 * reserve the lost portions in the bootmem maps.
1283 for (i = 0; i < pavail_ents; i++) {
1284 unsigned long old_start, old_end;
1286 old_start = pavail[i].phys_addr;
1287 old_end = old_start +
1289 while (old_start < old_end) {
1292 for (n = 0; pavail_rescan_ents; n++) {
1293 unsigned long new_start, new_end;
1295 new_start = pavail_rescan[n].phys_addr;
1296 new_end = new_start +
1297 pavail_rescan[n].reg_size;
1299 if (new_start <= old_start &&
1300 new_end >= (old_start + PAGE_SIZE)) {
1301 set_bit(old_start >> 22,
1302 sparc64_valid_addr_bitmap);
1306 reserve_bootmem(old_start, PAGE_SIZE);
1309 old_start += PAGE_SIZE;
1314 void __init mem_init(void)
1316 unsigned long codepages, datapages, initpages;
1317 unsigned long addr, last;
1320 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1322 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1323 if (sparc64_valid_addr_bitmap == NULL) {
1324 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1327 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1329 addr = PAGE_OFFSET + kern_base;
1330 last = PAGE_ALIGN(kern_size) + addr;
1331 while (addr < last) {
1332 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1338 max_mapnr = last_valid_pfn - pfn_base;
1339 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1341 #ifdef CONFIG_DEBUG_BOOTMEM
1342 prom_printf("mem_init: Calling free_all_bootmem().\n");
1344 totalram_pages = num_physpages = free_all_bootmem() - 1;
1347 * Set up the zero page, mark it reserved, so that page count
1348 * is not manipulated when freeing the page from user ptes.
1350 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1351 if (mem_map_zero == NULL) {
1352 prom_printf("paging_init: Cannot alloc zero page.\n");
1355 SetPageReserved(mem_map_zero);
1357 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1358 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1359 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1360 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1361 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1362 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1364 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1365 nr_free_pages() << (PAGE_SHIFT-10),
1366 codepages << (PAGE_SHIFT-10),
1367 datapages << (PAGE_SHIFT-10),
1368 initpages << (PAGE_SHIFT-10),
1369 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1371 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1372 cheetah_ecache_flush_init();
1375 void free_initmem(void)
1377 unsigned long addr, initend;
1380 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1382 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1383 initend = (unsigned long)(__init_end) & PAGE_MASK;
1384 for (; addr < initend; addr += PAGE_SIZE) {
1389 ((unsigned long) __va(kern_base)) -
1390 ((unsigned long) KERNBASE));
1391 memset((void *)addr, 0xcc, PAGE_SIZE);
1392 p = virt_to_page(page);
1394 ClearPageReserved(p);
1395 set_page_count(p, 1);
1402 #ifdef CONFIG_BLK_DEV_INITRD
1403 void free_initrd_mem(unsigned long start, unsigned long end)
1406 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1407 for (; start < end; start += PAGE_SIZE) {
1408 struct page *p = virt_to_page(start);
1410 ClearPageReserved(p);
1411 set_page_count(p, 1);
1419 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1420 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1421 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1422 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1423 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1424 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1426 pgprot_t PAGE_KERNEL __read_mostly;
1427 EXPORT_SYMBOL(PAGE_KERNEL);
1429 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1430 pgprot_t PAGE_COPY __read_mostly;
1432 pgprot_t PAGE_SHARED __read_mostly;
1433 EXPORT_SYMBOL(PAGE_SHARED);
1435 pgprot_t PAGE_EXEC __read_mostly;
1436 unsigned long pg_iobits __read_mostly;
1438 unsigned long _PAGE_IE __read_mostly;
1440 unsigned long _PAGE_E __read_mostly;
1441 EXPORT_SYMBOL(_PAGE_E);
1443 unsigned long _PAGE_CACHE __read_mostly;
1444 EXPORT_SYMBOL(_PAGE_CACHE);
1446 static void prot_init_common(unsigned long page_none,
1447 unsigned long page_shared,
1448 unsigned long page_copy,
1449 unsigned long page_readonly,
1450 unsigned long page_exec_bit)
1452 PAGE_COPY = __pgprot(page_copy);
1453 PAGE_SHARED = __pgprot(page_shared);
1455 protection_map[0x0] = __pgprot(page_none);
1456 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1457 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1458 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1459 protection_map[0x4] = __pgprot(page_readonly);
1460 protection_map[0x5] = __pgprot(page_readonly);
1461 protection_map[0x6] = __pgprot(page_copy);
1462 protection_map[0x7] = __pgprot(page_copy);
1463 protection_map[0x8] = __pgprot(page_none);
1464 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1465 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1466 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1467 protection_map[0xc] = __pgprot(page_readonly);
1468 protection_map[0xd] = __pgprot(page_readonly);
1469 protection_map[0xe] = __pgprot(page_shared);
1470 protection_map[0xf] = __pgprot(page_shared);
1473 static void __init sun4u_pgprot_init(void)
1475 unsigned long page_none, page_shared, page_copy, page_readonly;
1476 unsigned long page_exec_bit;
1478 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1479 _PAGE_CACHE_4U | _PAGE_P_4U |
1480 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1482 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1483 _PAGE_CACHE_4U | _PAGE_P_4U |
1484 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1485 _PAGE_EXEC_4U | _PAGE_L_4U);
1486 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1488 _PAGE_IE = _PAGE_IE_4U;
1489 _PAGE_E = _PAGE_E_4U;
1490 _PAGE_CACHE = _PAGE_CACHE_4U;
1492 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1493 __ACCESS_BITS_4U | _PAGE_E_4U);
1495 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1497 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1498 _PAGE_P_4U | _PAGE_W_4U);
1500 /* XXX Should use 256MB on Panther. XXX */
1501 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1503 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1504 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1505 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1506 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1509 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1510 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1511 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1512 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1513 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1514 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1515 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1517 page_exec_bit = _PAGE_EXEC_4U;
1519 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1523 static void __init sun4v_pgprot_init(void)
1525 unsigned long page_none, page_shared, page_copy, page_readonly;
1526 unsigned long page_exec_bit;
1528 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1529 _PAGE_CACHE_4V | _PAGE_P_4V |
1530 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1532 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1533 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1535 _PAGE_IE = _PAGE_IE_4V;
1536 _PAGE_E = _PAGE_E_4V;
1537 _PAGE_CACHE = _PAGE_CACHE_4V;
1539 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1541 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1542 _PAGE_P_4V | _PAGE_W_4V);
1544 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1546 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1547 _PAGE_P_4V | _PAGE_W_4V);
1549 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1550 __ACCESS_BITS_4V | _PAGE_E_4V);
1552 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1553 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1554 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1555 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1556 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1558 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1559 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1560 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1561 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1562 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1563 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1564 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1566 page_exec_bit = _PAGE_EXEC_4V;
1568 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1572 unsigned long pte_sz_bits(unsigned long sz)
1574 if (tlb_type == hypervisor) {
1578 return _PAGE_SZ8K_4V;
1580 return _PAGE_SZ64K_4V;
1582 return _PAGE_SZ512K_4V;
1583 case 4 * 1024 * 1024:
1584 return _PAGE_SZ4MB_4V;
1590 return _PAGE_SZ8K_4U;
1592 return _PAGE_SZ64K_4U;
1594 return _PAGE_SZ512K_4U;
1595 case 4 * 1024 * 1024:
1596 return _PAGE_SZ4MB_4U;
1601 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1605 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
1606 pte_val(pte) |= (((unsigned long)space) << 32);
1607 pte_val(pte) |= pte_sz_bits(page_size);
1612 static unsigned long kern_large_tte(unsigned long paddr)
1616 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1617 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1618 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1619 if (tlb_type == hypervisor)
1620 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1621 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1622 _PAGE_EXEC_4V | _PAGE_W_4V);
1628 * Translate PROM's mapping we capture at boot time into physical address.
1629 * The second parameter is only set from prom_callback() invocations.
1631 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
1636 mask = _PAGE_PADDR_4U;
1637 if (tlb_type == hypervisor)
1638 mask = _PAGE_PADDR_4V;
1640 for (i = 0; i < prom_trans_ents; i++) {
1641 struct linux_prom_translation *p = &prom_trans[i];
1643 if (promva >= p->virt &&
1644 promva < (p->virt + p->size)) {
1645 unsigned long base = p->data & mask;
1649 return base + (promva & (8192 - 1));
1657 /* XXX We should kill off this ugly thing at so me point. XXX */
1658 unsigned long sun4u_get_pte(unsigned long addr)
1664 unsigned long mask = _PAGE_PADDR_4U;
1666 if (tlb_type == hypervisor)
1667 mask = _PAGE_PADDR_4V;
1669 if (addr >= PAGE_OFFSET)
1672 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
1673 return prom_virt_to_phys(addr, NULL);
1675 pgdp = pgd_offset_k(addr);
1676 pudp = pud_offset(pgdp, addr);
1677 pmdp = pmd_offset(pudp, addr);
1678 ptep = pte_offset_kernel(pmdp, addr);
1680 return pte_val(*ptep) & mask;
1683 /* If not locked, zap it. */
1684 void __flush_tlb_all(void)
1686 unsigned long pstate;
1689 __asm__ __volatile__("flushw\n\t"
1690 "rdpr %%pstate, %0\n\t"
1691 "wrpr %0, %1, %%pstate"
1694 if (tlb_type == spitfire) {
1695 for (i = 0; i < 64; i++) {
1696 /* Spitfire Errata #32 workaround */
1697 /* NOTE: Always runs on spitfire, so no
1698 * cheetah+ page size encodings.
1700 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1704 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1706 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1707 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1710 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1711 spitfire_put_dtlb_data(i, 0x0UL);
1714 /* Spitfire Errata #32 workaround */
1715 /* NOTE: Always runs on spitfire, so no
1716 * cheetah+ page size encodings.
1718 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1722 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1724 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1725 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1728 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1729 spitfire_put_itlb_data(i, 0x0UL);
1732 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1733 cheetah_flush_dtlb_all();
1734 cheetah_flush_itlb_all();
1736 __asm__ __volatile__("wrpr %0, 0, %%pstate"