arch/sparc/mm/srmmu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * srmmu.c:  SRMMU specific routines for memory management.
   4  *
   5  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
   6  * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
   7  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
   8  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   9  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
  10  */
  11
  12 #include <linux/seq_file.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/memblock.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/vmalloc.h>
  17 #include <linux/kdebug.h>
  18 #include <linux/export.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/log2.h>
  22 #include <linux/gfp.h>
  23 #include <linux/fs.h>
  24 #include <linux/mm.h>
  25
  26 #include <asm/mmu_context.h>
  27 #include <asm/cacheflush.h>
  28 #include <asm/tlbflush.h>
  29 #include <asm/io-unit.h>
  30 #include <asm/pgalloc.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/bitext.h>
  33 #include <asm/vaddrs.h>
  34 #include <asm/cache.h>
  35 #include <asm/traps.h>
  36 #include <asm/oplib.h>
  37 #include <asm/mbus.h>
  38 #include <asm/page.h>
  39 #include <asm/asi.h>
  40 #include <asm/smp.h>
  41 #include <asm/io.h>
  42
  43 /* Now the cpu specific definitions. */
  44 #include <asm/turbosparc.h>
  45 #include <asm/tsunami.h>
  46 #include <asm/viking.h>
  47 #include <asm/swift.h>
  48 #include <asm/leon.h>
  49 #include <asm/mxcc.h>
  50 #include <asm/ross.h>
  51
  52 #include "mm_32.h"
  53
  54 enum mbus_module srmmu_modtype;
  55 static unsigned int hwbug_bitmask;
  56 int vac_cache_size;
  57 EXPORT_SYMBOL(vac_cache_size);
  58 int vac_line_size;
  59
  60 extern struct resource sparc_iomap;
  61
  62 extern unsigned long last_valid_pfn;
  63
  64 static pgd_t *srmmu_swapper_pg_dir;
  65
  66 const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops;
  67 EXPORT_SYMBOL(sparc32_cachetlb_ops);
  68
  69 #ifdef CONFIG_SMP
  70 const struct sparc32_cachetlb_ops *local_ops;
  71
  72 #define FLUSH_BEGIN(mm)
  73 #define FLUSH_END
  74 #else
  75 #define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) {
  76 #define FLUSH_END       }
  77 #endif
  78
  79 int flush_page_for_dma_global = 1;
  80
  81 char *srmmu_name;
  82
  83 ctxd_t *srmmu_ctx_table_phys;
  84 static ctxd_t *srmmu_context_table;
  85
  86 int viking_mxcc_present;
  87 static DEFINE_SPINLOCK(srmmu_context_spinlock);
  88
  89 static int is_hypersparc;
  90
  91 static int srmmu_cache_pagetables;
  92
  93 /* these will be initialized in srmmu_nocache_calcsize() */
  94 static unsigned long srmmu_nocache_size;
  95 static unsigned long srmmu_nocache_end;
  96
  97 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
  98 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
  99
 100 /* The context table is a nocache user with the biggest alignment needs. */
 101 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
 102
 103 void *srmmu_nocache_pool;
 104 static struct bit_map srmmu_nocache_map;
 105
 106 static inline int srmmu_pmd_none(pmd_t pmd)
 107 { return !(pmd_val(pmd) & 0xFFFFFFF); }
 108
 109 /* XXX should we hyper_flush_whole_icache here - Anton */
 110 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
 111 {
 112         pte_t pte;
 113
 114         pte = __pte((SRMMU_ET_PTD | (__nocache_pa(pgdp) >> 4)));
 115         set_pte((pte_t *)ctxp, pte);
 116 }
 117
 118 /*
 119  * Locations of MSI Registers.
 120  */
 121 #define MSI_MBUS_ARBEN  0xe0001008      /* MBus Arbiter Enable register */
 122
 123 /*
 124  * Useful bits in the MSI Registers.
 125  */
 126 #define MSI_ASYNC_MODE  0x80000000      /* Operate the MSI asynchronously */
 127
 128 static void msi_set_sync(void)
 129 {
 130         __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
 131                               "andn %%g3, %2, %%g3\n\t"
 132                               "sta %%g3, [%0] %1\n\t" : :
 133                               "r" (MSI_MBUS_ARBEN),
 134                               "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
 135 }
 136
 137 void pmd_set(pmd_t *pmdp, pte_t *ptep)
 138 {
 139         unsigned long ptp = __nocache_pa(ptep) >> 4;
 140         set_pte((pte_t *)&pmd_val(*pmdp), __pte(SRMMU_ET_PTD | ptp));
 141 }
 142
 143 /* Find an entry in the third-level page table.. */
 144 pte_t *pte_offset_kernel(pmd_t *dir, unsigned long address)
 145 {
 146         void *pte;
 147
 148         pte = __nocache_va((pmd_val(*dir) & SRMMU_PTD_PMASK) << 4);
 149         return (pte_t *) pte +
 150             ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
 151 }
 152
 153 /*
 154  * size: bytes to allocate in the nocache area.
 155  * align: bytes, number to align at.
 156  * Returns the virtual address of the allocated area.
 157  */
 158 static void *__srmmu_get_nocache(int size, int align)
 159 {
 160         int offset, minsz = 1 << SRMMU_NOCACHE_BITMAP_SHIFT;
 161         unsigned long addr;
 162
 163         if (size < minsz) {
 164                 printk(KERN_ERR "Size 0x%x too small for nocache request\n",
 165                        size);
 166                 size = minsz;
 167         }
 168         if (size & (minsz - 1)) {
 169                 printk(KERN_ERR "Size 0x%x unaligned in nocache request\n",
 170                        size);
 171                 size += minsz - 1;
 172         }
 173         BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
 174
 175         offset = bit_map_string_get(&srmmu_nocache_map,
 176                                     size >> SRMMU_NOCACHE_BITMAP_SHIFT,
 177                                     align >> SRMMU_NOCACHE_BITMAP_SHIFT);
 178         if (offset == -1) {
 179                 printk(KERN_ERR "srmmu: out of nocache %d: %d/%d\n",
 180                        size, (int) srmmu_nocache_size,
 181                        srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
 182                 return NULL;
 183         }
 184
 185         addr = SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT);
 186         return (void *)addr;
 187 }
 188
 189 void *srmmu_get_nocache(int size, int align)
 190 {
 191         void *tmp;
 192
 193         tmp = __srmmu_get_nocache(size, align);
 194
 195         if (tmp)
 196                 memset(tmp, 0, size);
 197
 198         return tmp;
 199 }
 200
 201 void srmmu_free_nocache(void *addr, int size)
 202 {
 203         unsigned long vaddr;
 204         int offset;
 205
 206         vaddr = (unsigned long)addr;
 207         if (vaddr < SRMMU_NOCACHE_VADDR) {
 208                 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
 209                     vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
 210                 BUG();
 211         }
 212         if (vaddr + size > srmmu_nocache_end) {
 213                 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
 214                     vaddr, srmmu_nocache_end);
 215                 BUG();
 216         }
 217         if (!is_power_of_2(size)) {
 218                 printk("Size 0x%x is not a power of 2\n", size);
 219                 BUG();
 220         }
 221         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 222                 printk("Size 0x%x is too small\n", size);
 223                 BUG();
 224         }
 225         if (vaddr & (size - 1)) {
 226                 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
 227                 BUG();
 228         }
 229
 230         offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
 231         size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 232
 233         bit_map_clear(&srmmu_nocache_map, offset, size);
 234 }
 235
 236 static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
 237                                                  unsigned long end);
 238
 239 /* Return how much physical memory we have.  */
 240 static unsigned long __init probe_memory(void)
 241 {
 242         unsigned long total = 0;
 243         int i;
 244
 245         for (i = 0; sp_banks[i].num_bytes; i++)
 246                 total += sp_banks[i].num_bytes;
 247
 248         return total;
 249 }
 250
 251 /*
 252  * Reserve nocache dynamically proportionally to the amount of
 253  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
 254  */
 255 static void __init srmmu_nocache_calcsize(void)
 256 {
 257         unsigned long sysmemavail = probe_memory() / 1024;
 258         int srmmu_nocache_npages;
 259
 260         srmmu_nocache_npages =
 261                 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
 262
 263  /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
 264         // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
 265         if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
 266                 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
 267
 268         /* anything above 1280 blows up */
 269         if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
 270                 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
 271
 272         srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
 273         srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
 274 }
 275
 276 static void __init srmmu_nocache_init(void)
 277 {
 278         void *srmmu_nocache_bitmap;
 279         unsigned int bitmap_bits;
 280         pgd_t *pgd;
 281         p4d_t *p4d;
 282         pud_t *pud;
 283         pmd_t *pmd;
 284         pte_t *pte;
 285         unsigned long paddr, vaddr;
 286         unsigned long pteval;
 287
 288         bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 289
 290         srmmu_nocache_pool = memblock_alloc(srmmu_nocache_size,
 291                                             SRMMU_NOCACHE_ALIGN_MAX);
 292         if (!srmmu_nocache_pool)
 293                 panic("%s: Failed to allocate %lu bytes align=0x%x\n",
 294                       __func__, srmmu_nocache_size, SRMMU_NOCACHE_ALIGN_MAX);
 295         memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
 296
 297         srmmu_nocache_bitmap =
 298                 memblock_alloc(BITS_TO_LONGS(bitmap_bits) * sizeof(long),
 299                                SMP_CACHE_BYTES);
 300         if (!srmmu_nocache_bitmap)
 301                 panic("%s: Failed to allocate %zu bytes\n", __func__,
 302                       BITS_TO_LONGS(bitmap_bits) * sizeof(long));
 303         bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
 304
 305         srmmu_swapper_pg_dir = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 306         memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
 307         init_mm.pgd = srmmu_swapper_pg_dir;
 308
 309         srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
 310
 311         paddr = __pa((unsigned long)srmmu_nocache_pool);
 312         vaddr = SRMMU_NOCACHE_VADDR;
 313
 314         while (vaddr < srmmu_nocache_end) {
 315                 pgd = pgd_offset_k(vaddr);
 316                 p4d = p4d_offset(pgd, vaddr);
 317                 pud = pud_offset(p4d, vaddr);
 318                 pmd = pmd_offset(__nocache_fix(pud), vaddr);
 319                 pte = pte_offset_kernel(__nocache_fix(pmd), vaddr);
 320
 321                 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
 322
 323                 if (srmmu_cache_pagetables)
 324                         pteval |= SRMMU_CACHE;
 325
 326                 set_pte(__nocache_fix(pte), __pte(pteval));
 327
 328                 vaddr += PAGE_SIZE;
 329                 paddr += PAGE_SIZE;
 330         }
 331
 332         flush_cache_all();
 333         flush_tlb_all();
 334 }
 335
 336 pgd_t *get_pgd_fast(void)
 337 {
 338         pgd_t *pgd = NULL;
 339
 340         pgd = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 341         if (pgd) {
 342                 pgd_t *init = pgd_offset_k(0);
 343                 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
 344                 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
 345                                                 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
 346         }
 347
 348         return pgd;
 349 }
 350
 351 /*
 352  * Hardware needs alignment to 256 only, but we align to whole page size
 353  * to reduce fragmentation problems due to the buddy principle.
 354  * XXX Provide actual fragmentation statistics in /proc.
 355  *
 356  * Alignments up to the page size are the same for physical and virtual
 357  * addresses of the nocache area.
 358  */
 359 pgtable_t pte_alloc_one(struct mm_struct *mm)
 360 {
 361         pte_t *ptep;
 362         struct page *page;
 363
 364         if ((ptep = pte_alloc_one_kernel(mm)) == 0)
 365                 return NULL;
 366         page = pfn_to_page(__nocache_pa((unsigned long)ptep) >> PAGE_SHIFT);
 367         spin_lock(&mm->page_table_lock);
 368         if (page_ref_inc_return(page) == 2 && !pgtable_pte_page_ctor(page)) {
 369                 page_ref_dec(page);
 370                 ptep = NULL;
 371         }
 372         spin_unlock(&mm->page_table_lock);
 373
 374         return ptep;
 375 }
 376
 377 void pte_free(struct mm_struct *mm, pgtable_t ptep)
 378 {
 379         struct page *page;
 380
 381         page = pfn_to_page(__nocache_pa((unsigned long)ptep) >> PAGE_SHIFT);
 382         spin_lock(&mm->page_table_lock);
 383         if (page_ref_dec_return(page) == 1)
 384                 pgtable_pte_page_dtor(page);
 385         spin_unlock(&mm->page_table_lock);
 386
 387         srmmu_free_nocache(ptep, SRMMU_PTE_TABLE_SIZE);
 388 }
 389
 390 /* context handling - a dynamically sized pool is used */
 391 #define NO_CONTEXT      -1
 392
 393 struct ctx_list {
 394         struct ctx_list *next;
 395         struct ctx_list *prev;
 396         unsigned int ctx_number;
 397         struct mm_struct *ctx_mm;
 398 };
 399
 400 static struct ctx_list *ctx_list_pool;
 401 static struct ctx_list ctx_free;
 402 static struct ctx_list ctx_used;
 403
 404 /* At boot time we determine the number of contexts */
 405 static int num_contexts;
 406
 407 static inline void remove_from_ctx_list(struct ctx_list *entry)
 408 {
 409         entry->next->prev = entry->prev;
 410         entry->prev->next = entry->next;
 411 }
 412
 413 static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
 414 {
 415         entry->next = head;
 416         (entry->prev = head->prev)->next = entry;
 417         head->prev = entry;
 418 }
 419 #define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
 420 #define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
 421
 422
 423 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
 424 {
 425         struct ctx_list *ctxp;
 426
 427         ctxp = ctx_free.next;
 428         if (ctxp != &ctx_free) {
 429                 remove_from_ctx_list(ctxp);
 430                 add_to_used_ctxlist(ctxp);
 431                 mm->context = ctxp->ctx_number;
 432                 ctxp->ctx_mm = mm;
 433                 return;
 434         }
 435         ctxp = ctx_used.next;
 436         if (ctxp->ctx_mm == old_mm)
 437                 ctxp = ctxp->next;
 438         if (ctxp == &ctx_used)
 439                 panic("out of mmu contexts");
 440         flush_cache_mm(ctxp->ctx_mm);
 441         flush_tlb_mm(ctxp->ctx_mm);
 442         remove_from_ctx_list(ctxp);
 443         add_to_used_ctxlist(ctxp);
 444         ctxp->ctx_mm->context = NO_CONTEXT;
 445         ctxp->ctx_mm = mm;
 446         mm->context = ctxp->ctx_number;
 447 }
 448
 449 static inline void free_context(int context)
 450 {
 451         struct ctx_list *ctx_old;
 452
 453         ctx_old = ctx_list_pool + context;
 454         remove_from_ctx_list(ctx_old);
 455         add_to_free_ctxlist(ctx_old);
 456 }
 457
 458 static void __init sparc_context_init(int numctx)
 459 {
 460         int ctx;
 461         unsigned long size;
 462
 463         size = numctx * sizeof(struct ctx_list);
 464         ctx_list_pool = memblock_alloc(size, SMP_CACHE_BYTES);
 465         if (!ctx_list_pool)
 466                 panic("%s: Failed to allocate %lu bytes\n", __func__, size);
 467
 468         for (ctx = 0; ctx < numctx; ctx++) {
 469                 struct ctx_list *clist;
 470
 471                 clist = (ctx_list_pool + ctx);
 472                 clist->ctx_number = ctx;
 473                 clist->ctx_mm = NULL;
 474         }
 475         ctx_free.next = ctx_free.prev = &ctx_free;
 476         ctx_used.next = ctx_used.prev = &ctx_used;
 477         for (ctx = 0; ctx < numctx; ctx++)
 478                 add_to_free_ctxlist(ctx_list_pool + ctx);
 479 }
 480
 481 void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
 482                struct task_struct *tsk)
 483 {
 484         unsigned long flags;
 485
 486         if (mm->context == NO_CONTEXT) {
 487                 spin_lock_irqsave(&srmmu_context_spinlock, flags);
 488                 alloc_context(old_mm, mm);
 489                 spin_unlock_irqrestore(&srmmu_context_spinlock, flags);
 490                 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
 491         }
 492
 493         if (sparc_cpu_model == sparc_leon)
 494                 leon_switch_mm();
 495
 496         if (is_hypersparc)
 497                 hyper_flush_whole_icache();
 498
 499         srmmu_set_context(mm->context);
 500 }
 501
 502 /* Low level IO area allocation on the SRMMU. */
 503 static inline void srmmu_mapioaddr(unsigned long physaddr,
 504                                    unsigned long virt_addr, int bus_type)
 505 {
 506         pgd_t *pgdp;
 507         p4d_t *p4dp;
 508         pud_t *pudp;
 509         pmd_t *pmdp;
 510         pte_t *ptep;
 511         unsigned long tmp;
 512
 513         physaddr &= PAGE_MASK;
 514         pgdp = pgd_offset_k(virt_addr);
 515         p4dp = p4d_offset(pgdp, virt_addr);
 516         pudp = pud_offset(p4dp, virt_addr);
 517         pmdp = pmd_offset(pudp, virt_addr);
 518         ptep = pte_offset_kernel(pmdp, virt_addr);
 519         tmp = (physaddr >> 4) | SRMMU_ET_PTE;
 520
 521         /* I need to test whether this is consistent over all
 522          * sun4m's.  The bus_type represents the upper 4 bits of
 523          * 36-bit physical address on the I/O space lines...
 524          */
 525         tmp |= (bus_type << 28);
 526         tmp |= SRMMU_PRIV;
 527         __flush_page_to_ram(virt_addr);
 528         set_pte(ptep, __pte(tmp));
 529 }
 530
 531 void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
 532                       unsigned long xva, unsigned int len)
 533 {
 534         while (len != 0) {
 535                 len -= PAGE_SIZE;
 536                 srmmu_mapioaddr(xpa, xva, bus);
 537                 xva += PAGE_SIZE;
 538                 xpa += PAGE_SIZE;
 539         }
 540         flush_tlb_all();
 541 }
 542
 543 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
 544 {
 545         pgd_t *pgdp;
 546         p4d_t *p4dp;
 547         pud_t *pudp;
 548         pmd_t *pmdp;
 549         pte_t *ptep;
 550
 551
 552         pgdp = pgd_offset_k(virt_addr);
 553         p4dp = p4d_offset(pgdp, virt_addr);
 554         pudp = pud_offset(p4dp, virt_addr);
 555         pmdp = pmd_offset(pudp, virt_addr);
 556         ptep = pte_offset_kernel(pmdp, virt_addr);
 557
 558         /* No need to flush uncacheable page. */
 559         __pte_clear(ptep);
 560 }
 561
 562 void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
 563 {
 564         while (len != 0) {
 565                 len -= PAGE_SIZE;
 566                 srmmu_unmapioaddr(virt_addr);
 567                 virt_addr += PAGE_SIZE;
 568         }
 569         flush_tlb_all();
 570 }
 571
 572 /* tsunami.S */
 573 extern void tsunami_flush_cache_all(void);
 574 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
 575 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 576 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 577 extern void tsunami_flush_page_to_ram(unsigned long page);
 578 extern void tsunami_flush_page_for_dma(unsigned long page);
 579 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 580 extern void tsunami_flush_tlb_all(void);
 581 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
 582 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 583 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 584 extern void tsunami_setup_blockops(void);
 585
 586 /* swift.S */
 587 extern void swift_flush_cache_all(void);
 588 extern void swift_flush_cache_mm(struct mm_struct *mm);
 589 extern void swift_flush_cache_range(struct vm_area_struct *vma,
 590                                     unsigned long start, unsigned long end);
 591 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 592 extern void swift_flush_page_to_ram(unsigned long page);
 593 extern void swift_flush_page_for_dma(unsigned long page);
 594 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 595 extern void swift_flush_tlb_all(void);
 596 extern void swift_flush_tlb_mm(struct mm_struct *mm);
 597 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
 598                                   unsigned long start, unsigned long end);
 599 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 600
 601 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
 602 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 603 {
 604         int cctx, ctx1;
 605
 606         page &= PAGE_MASK;
 607         if ((ctx1 = vma->vm_mm->context) != -1) {
 608                 cctx = srmmu_get_context();
 609 /* Is context # ever different from current context? P3 */
 610                 if (cctx != ctx1) {
 611                         printk("flush ctx %02x curr %02x\n", ctx1, cctx);
 612                         srmmu_set_context(ctx1);
 613                         swift_flush_page(page);
 614                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 615                                         "r" (page), "i" (ASI_M_FLUSH_PROBE));
 616                         srmmu_set_context(cctx);
 617                 } else {
 618                          /* Rm. prot. bits from virt. c. */
 619                         /* swift_flush_cache_all(); */
 620                         /* swift_flush_cache_page(vma, page); */
 621                         swift_flush_page(page);
 622
 623                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 624                                 "r" (page), "i" (ASI_M_FLUSH_PROBE));
 625                         /* same as above: srmmu_flush_tlb_page() */
 626                 }
 627         }
 628 }
 629 #endif
 630
 631 /*
 632  * The following are all MBUS based SRMMU modules, and therefore could
 633  * be found in a multiprocessor configuration.  On the whole, these
 634  * chips seems to be much more touchy about DVMA and page tables
 635  * with respect to cache coherency.
 636  */
 637
 638 /* viking.S */
 639 extern void viking_flush_cache_all(void);
 640 extern void viking_flush_cache_mm(struct mm_struct *mm);
 641 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
 642                                      unsigned long end);
 643 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 644 extern void viking_flush_page_to_ram(unsigned long page);
 645 extern void viking_flush_page_for_dma(unsigned long page);
 646 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
 647 extern void viking_flush_page(unsigned long page);
 648 extern void viking_mxcc_flush_page(unsigned long page);
 649 extern void viking_flush_tlb_all(void);
 650 extern void viking_flush_tlb_mm(struct mm_struct *mm);
 651 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 652                                    unsigned long end);
 653 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
 654                                   unsigned long page);
 655 extern void sun4dsmp_flush_tlb_all(void);
 656 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
 657 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 658                                    unsigned long end);
 659 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
 660                                   unsigned long page);
 661
 662 /* hypersparc.S */
 663 extern void hypersparc_flush_cache_all(void);
 664 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
 665 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 666 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 667 extern void hypersparc_flush_page_to_ram(unsigned long page);
 668 extern void hypersparc_flush_page_for_dma(unsigned long page);
 669 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 670 extern void hypersparc_flush_tlb_all(void);
 671 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
 672 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 673 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 674 extern void hypersparc_setup_blockops(void);
 675
 676 /*
 677  * NOTE: All of this startup code assumes the low 16mb (approx.) of
 678  *       kernel mappings are done with one single contiguous chunk of
 679  *       ram.  On small ram machines (classics mainly) we only get
 680  *       around 8mb mapped for us.
 681  */
 682
 683 static void __init early_pgtable_allocfail(char *type)
 684 {
 685         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
 686         prom_halt();
 687 }
 688
 689 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
 690                                                         unsigned long end)
 691 {
 692         pgd_t *pgdp;
 693         p4d_t *p4dp;
 694         pud_t *pudp;
 695         pmd_t *pmdp;
 696         pte_t *ptep;
 697
 698         while (start < end) {
 699                 pgdp = pgd_offset_k(start);
 700                 p4dp = p4d_offset(pgdp, start);
 701                 pudp = pud_offset(p4dp, start);
 702                 if (pud_none(*(pud_t *)__nocache_fix(pudp))) {
 703                         pmdp = __srmmu_get_nocache(
 704                             SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 705                         if (pmdp == NULL)
 706                                 early_pgtable_allocfail("pmd");
 707                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
 708                         pud_set(__nocache_fix(pudp), pmdp);
 709                 }
 710                 pmdp = pmd_offset(__nocache_fix(pudp), start);
 711                 if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
 712                         ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
 713                         if (ptep == NULL)
 714                                 early_pgtable_allocfail("pte");
 715                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
 716                         pmd_set(__nocache_fix(pmdp), ptep);
 717                 }
 718                 if (start > (0xffffffffUL - PMD_SIZE))
 719                         break;
 720                 start = (start + PMD_SIZE) & PMD_MASK;
 721         }
 722 }
 723
 724 static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
 725                                                   unsigned long end)
 726 {
 727         pgd_t *pgdp;
 728         p4d_t *p4dp;
 729         pud_t *pudp;
 730         pmd_t *pmdp;
 731         pte_t *ptep;
 732
 733         while (start < end) {
 734                 pgdp = pgd_offset_k(start);
 735                 p4dp = p4d_offset(pgdp, start);
 736                 pudp = pud_offset(p4dp, start);
 737                 if (pud_none(*pudp)) {
 738                         pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 739                         if (pmdp == NULL)
 740                                 early_pgtable_allocfail("pmd");
 741                         memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
 742                         pud_set((pud_t *)pgdp, pmdp);
 743                 }
 744                 pmdp = pmd_offset(pudp, start);
 745                 if (srmmu_pmd_none(*pmdp)) {
 746                         ptep = __srmmu_get_nocache(PTE_SIZE,
 747                                                              PTE_SIZE);
 748                         if (ptep == NULL)
 749                                 early_pgtable_allocfail("pte");
 750                         memset(ptep, 0, PTE_SIZE);
 751                         pmd_set(pmdp, ptep);
 752                 }
 753                 if (start > (0xffffffffUL - PMD_SIZE))
 754                         break;
 755                 start = (start + PMD_SIZE) & PMD_MASK;
 756         }
 757 }
 758
 759 /* These flush types are not available on all chips... */
 760 static inline unsigned long srmmu_probe(unsigned long vaddr)
 761 {
 762         unsigned long retval;
 763
 764         if (sparc_cpu_model != sparc_leon) {
 765
 766                 vaddr &= PAGE_MASK;
 767                 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
 768                                      "=r" (retval) :
 769                                      "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
 770         } else {
 771                 retval = leon_swprobe(vaddr, NULL);
 772         }
 773         return retval;
 774 }
 775
 776 /*
 777  * This is much cleaner than poking around physical address space
 778  * looking at the prom's page table directly which is what most
 779  * other OS's do.  Yuck... this is much better.
 780  */
 781 static void __init srmmu_inherit_prom_mappings(unsigned long start,
 782                                                unsigned long end)
 783 {
 784         unsigned long probed;
 785         unsigned long addr;
 786         pgd_t *pgdp;
 787         p4d_t *p4dp;
 788         pud_t *pudp;
 789         pmd_t *pmdp;
 790         pte_t *ptep;
 791         int what; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
 792
 793         while (start <= end) {
 794                 if (start == 0)
 795                         break; /* probably wrap around */
 796                 if (start == 0xfef00000)
 797                         start = KADB_DEBUGGER_BEGVM;
 798                 probed = srmmu_probe(start);
 799                 if (!probed) {
 800                         /* continue probing until we find an entry */
 801                         start += PAGE_SIZE;
 802                         continue;
 803                 }
 804
 805                 /* A red snapper, see what it really is. */
 806                 what = 0;
 807                 addr = start - PAGE_SIZE;
 808
 809                 if (!(start & ~(PMD_MASK))) {
 810                         if (srmmu_probe(addr + PMD_SIZE) == probed)
 811                                 what = 1;
 812                 }
 813
 814                 if (!(start & ~(PGDIR_MASK))) {
 815                         if (srmmu_probe(addr + PGDIR_SIZE) == probed)
 816                                 what = 2;
 817                 }
 818
 819                 pgdp = pgd_offset_k(start);
 820                 p4dp = p4d_offset(pgdp, start);
 821                 pudp = pud_offset(p4dp, start);
 822                 if (what == 2) {
 823                         *(pgd_t *)__nocache_fix(pgdp) = __pgd(probed);
 824                         start += PGDIR_SIZE;
 825                         continue;
 826                 }
 827                 if (pud_none(*(pud_t *)__nocache_fix(pudp))) {
 828                         pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE,
 829                                                    SRMMU_PMD_TABLE_SIZE);
 830                         if (pmdp == NULL)
 831                                 early_pgtable_allocfail("pmd");
 832                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
 833                         pud_set(__nocache_fix(pudp), pmdp);
 834                 }
 835                 pmdp = pmd_offset(__nocache_fix(pgdp), start);
 836                 if (what == 1) {
 837                         *(pmd_t *)__nocache_fix(pmdp) = __pmd(probed);
 838                         start += PMD_SIZE;
 839                         continue;
 840                 }
 841                 if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
 842                         ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
 843                         if (ptep == NULL)
 844                                 early_pgtable_allocfail("pte");
 845                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
 846                         pmd_set(__nocache_fix(pmdp), ptep);
 847                 }
 848                 ptep = pte_offset_kernel(__nocache_fix(pmdp), start);
 849                 *(pte_t *)__nocache_fix(ptep) = __pte(probed);
 850                 start += PAGE_SIZE;
 851         }
 852 }
 853
 854 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
 855
 856 /* Create a third-level SRMMU 16MB page mapping. */
 857 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
 858 {
 859         pgd_t *pgdp = pgd_offset_k(vaddr);
 860         unsigned long big_pte;
 861
 862         big_pte = KERNEL_PTE(phys_base >> 4);
 863         *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
 864 }
 865
 866 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
 867 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
 868 {
 869         unsigned long pstart = (sp_banks[sp_entry].base_addr & PGDIR_MASK);
 870         unsigned long vstart = (vbase & PGDIR_MASK);
 871         unsigned long vend = PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
 872         /* Map "low" memory only */
 873         const unsigned long min_vaddr = PAGE_OFFSET;
 874         const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
 875
 876         if (vstart < min_vaddr || vstart >= max_vaddr)
 877                 return vstart;
 878
 879         if (vend > max_vaddr || vend < min_vaddr)
 880                 vend = max_vaddr;
 881
 882         while (vstart < vend) {
 883                 do_large_mapping(vstart, pstart);
 884                 vstart += PGDIR_SIZE; pstart += PGDIR_SIZE;
 885         }
 886         return vstart;
 887 }
 888
 889 static void __init map_kernel(void)
 890 {
 891         int i;
 892
 893         if (phys_base > 0) {
 894                 do_large_mapping(PAGE_OFFSET, phys_base);
 895         }
 896
 897         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
 898                 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
 899         }
 900 }
 901
 902 void (*poke_srmmu)(void) = NULL;
 903
 904 void __init srmmu_paging_init(void)
 905 {
 906         int i;
 907         phandle cpunode;
 908         char node_str[128];
 909         pgd_t *pgd;
 910         p4d_t *p4d;
 911         pud_t *pud;
 912         pmd_t *pmd;
 913         pte_t *pte;
 914         unsigned long pages_avail;
 915
 916         init_mm.context = (unsigned long) NO_CONTEXT;
 917         sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
 918
 919         if (sparc_cpu_model == sun4d)
 920                 num_contexts = 65536; /* We know it is Viking */
 921         else {
 922                 /* Find the number of contexts on the srmmu. */
 923                 cpunode = prom_getchild(prom_root_node);
 924                 num_contexts = 0;
 925                 while (cpunode != 0) {
 926                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
 927                         if (!strcmp(node_str, "cpu")) {
 928                                 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
 929                                 break;
 930                         }
 931                         cpunode = prom_getsibling(cpunode);
 932                 }
 933         }
 934
 935         if (!num_contexts) {
 936                 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
 937                 prom_halt();
 938         }
 939
 940         pages_avail = 0;
 941         last_valid_pfn = bootmem_init(&pages_avail);
 942
 943         srmmu_nocache_calcsize();
 944         srmmu_nocache_init();
 945         srmmu_inherit_prom_mappings(0xfe400000, (LINUX_OPPROM_ENDVM - PAGE_SIZE));
 946         map_kernel();
 947
 948         /* ctx table has to be physically aligned to its size */
 949         srmmu_context_table = __srmmu_get_nocache(num_contexts * sizeof(ctxd_t), num_contexts * sizeof(ctxd_t));
 950         srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa(srmmu_context_table);
 951
 952         for (i = 0; i < num_contexts; i++)
 953                 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
 954
 955         flush_cache_all();
 956         srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
 957 #ifdef CONFIG_SMP
 958         /* Stop from hanging here... */
 959         local_ops->tlb_all();
 960 #else
 961         flush_tlb_all();
 962 #endif
 963         poke_srmmu();
 964
 965         srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
 966         srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
 967
 968         srmmu_allocate_ptable_skeleton(
 969                 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
 970         srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
 971
 972         pgd = pgd_offset_k(PKMAP_BASE);
 973         p4d = p4d_offset(pgd, PKMAP_BASE);
 974         pud = pud_offset(p4d, PKMAP_BASE);
 975         pmd = pmd_offset(pud, PKMAP_BASE);
 976         pte = pte_offset_kernel(pmd, PKMAP_BASE);
 977         pkmap_page_table = pte;
 978
 979         flush_cache_all();
 980         flush_tlb_all();
 981
 982         sparc_context_init(num_contexts);
 983
 984         kmap_init();
 985
 986         {
 987                 unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 };
 988
 989                 max_zone_pfn[ZONE_DMA] = max_low_pfn;
 990                 max_zone_pfn[ZONE_NORMAL] = max_low_pfn;
 991                 max_zone_pfn[ZONE_HIGHMEM] = highend_pfn;
 992
 993                 free_area_init(max_zone_pfn);
 994         }
 995 }
 996
 997 void mmu_info(struct seq_file *m)
 998 {
 999         seq_printf(m,
1000                    "MMU type\t: %s\n"
1001                    "contexts\t: %d\n"
1002                    "nocache total\t: %ld\n"
1003                    "nocache used\t: %d\n",
1004                    srmmu_name,
1005                    num_contexts,
1006                    srmmu_nocache_size,
1007                    srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
1008 }
1009
1010 int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
1011 {
1012         mm->context = NO_CONTEXT;
1013         return 0;
1014 }
1015
1016 void destroy_context(struct mm_struct *mm)
1017 {
1018         unsigned long flags;
1019
1020         if (mm->context != NO_CONTEXT) {
1021                 flush_cache_mm(mm);
1022                 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1023                 flush_tlb_mm(mm);
1024                 spin_lock_irqsave(&srmmu_context_spinlock, flags);
1025                 free_context(mm->context);
1026                 spin_unlock_irqrestore(&srmmu_context_spinlock, flags);
1027                 mm->context = NO_CONTEXT;
1028         }
1029 }
1030
1031 /* Init various srmmu chip types. */
1032 static void __init srmmu_is_bad(void)
1033 {
1034         prom_printf("Could not determine SRMMU chip type.\n");
1035         prom_halt();
1036 }
1037
1038 static void __init init_vac_layout(void)
1039 {
1040         phandle nd;
1041         int cache_lines;
1042         char node_str[128];
1043 #ifdef CONFIG_SMP
1044         int cpu = 0;
1045         unsigned long max_size = 0;
1046         unsigned long min_line_size = 0x10000000;
1047 #endif
1048
1049         nd = prom_getchild(prom_root_node);
1050         while ((nd = prom_getsibling(nd)) != 0) {
1051                 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1052                 if (!strcmp(node_str, "cpu")) {
1053                         vac_line_size = prom_getint(nd, "cache-line-size");
1054                         if (vac_line_size == -1) {
1055                                 prom_printf("can't determine cache-line-size, halting.\n");
1056                                 prom_halt();
1057                         }
1058                         cache_lines = prom_getint(nd, "cache-nlines");
1059                         if (cache_lines == -1) {
1060                                 prom_printf("can't determine cache-nlines, halting.\n");
1061                                 prom_halt();
1062                         }
1063
1064                         vac_cache_size = cache_lines * vac_line_size;
1065 #ifdef CONFIG_SMP
1066                         if (vac_cache_size > max_size)
1067                                 max_size = vac_cache_size;
1068                         if (vac_line_size < min_line_size)
1069                                 min_line_size = vac_line_size;
1070                         //FIXME: cpus not contiguous!!
1071                         cpu++;
1072                         if (cpu >= nr_cpu_ids || !cpu_online(cpu))
1073                                 break;
1074 #else
1075                         break;
1076 #endif
1077                 }
1078         }
1079         if (nd == 0) {
1080                 prom_printf("No CPU nodes found, halting.\n");
1081                 prom_halt();
1082         }
1083 #ifdef CONFIG_SMP
1084         vac_cache_size = max_size;
1085         vac_line_size = min_line_size;
1086 #endif
1087         printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1088                (int)vac_cache_size, (int)vac_line_size);
1089 }
1090
1091 static void poke_hypersparc(void)
1092 {
1093         volatile unsigned long clear;
1094         unsigned long mreg = srmmu_get_mmureg();
1095
1096         hyper_flush_unconditional_combined();
1097
1098         mreg &= ~(HYPERSPARC_CWENABLE);
1099         mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1100         mreg |= (HYPERSPARC_CMODE);
1101
1102         srmmu_set_mmureg(mreg);
1103
1104 #if 0 /* XXX I think this is bad news... -DaveM */
1105         hyper_clear_all_tags();
1106 #endif
1107
1108         put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1109         hyper_flush_whole_icache();
1110         clear = srmmu_get_faddr();
1111         clear = srmmu_get_fstatus();
1112 }
1113
1114 static const struct sparc32_cachetlb_ops hypersparc_ops = {
1115         .cache_all      = hypersparc_flush_cache_all,
1116         .cache_mm       = hypersparc_flush_cache_mm,
1117         .cache_page     = hypersparc_flush_cache_page,
1118         .cache_range    = hypersparc_flush_cache_range,
1119         .tlb_all        = hypersparc_flush_tlb_all,
1120         .tlb_mm         = hypersparc_flush_tlb_mm,
1121         .tlb_page       = hypersparc_flush_tlb_page,
1122         .tlb_range      = hypersparc_flush_tlb_range,
1123         .page_to_ram    = hypersparc_flush_page_to_ram,
1124         .sig_insns      = hypersparc_flush_sig_insns,
1125         .page_for_dma   = hypersparc_flush_page_for_dma,
1126 };
1127
1128 static void __init init_hypersparc(void)
1129 {
1130         srmmu_name = "ROSS HyperSparc";
1131         srmmu_modtype = HyperSparc;
1132
1133         init_vac_layout();
1134
1135         is_hypersparc = 1;
1136         sparc32_cachetlb_ops = &hypersparc_ops;
1137
1138         poke_srmmu = poke_hypersparc;
1139
1140         hypersparc_setup_blockops();
1141 }
1142
1143 static void poke_swift(void)
1144 {
1145         unsigned long mreg;
1146
1147         /* Clear any crap from the cache or else... */
1148         swift_flush_cache_all();
1149
1150         /* Enable I & D caches */
1151         mreg = srmmu_get_mmureg();
1152         mreg |= (SWIFT_IE | SWIFT_DE);
1153         /*
1154          * The Swift branch folding logic is completely broken.  At
1155          * trap time, if things are just right, if can mistakenly
1156          * think that a trap is coming from kernel mode when in fact
1157          * it is coming from user mode (it mis-executes the branch in
1158          * the trap code).  So you see things like crashme completely
1159          * hosing your machine which is completely unacceptable.  Turn
1160          * this shit off... nice job Fujitsu.
1161          */
1162         mreg &= ~(SWIFT_BF);
1163         srmmu_set_mmureg(mreg);
1164 }
1165
1166 static const struct sparc32_cachetlb_ops swift_ops = {
1167         .cache_all      = swift_flush_cache_all,
1168         .cache_mm       = swift_flush_cache_mm,
1169         .cache_page     = swift_flush_cache_page,
1170         .cache_range    = swift_flush_cache_range,
1171         .tlb_all        = swift_flush_tlb_all,
1172         .tlb_mm         = swift_flush_tlb_mm,
1173         .tlb_page       = swift_flush_tlb_page,
1174         .tlb_range      = swift_flush_tlb_range,
1175         .page_to_ram    = swift_flush_page_to_ram,
1176         .sig_insns      = swift_flush_sig_insns,
1177         .page_for_dma   = swift_flush_page_for_dma,
1178 };
1179
1180 #define SWIFT_MASKID_ADDR  0x10003018
1181 static void __init init_swift(void)
1182 {
1183         unsigned long swift_rev;
1184
1185         __asm__ __volatile__("lda [%1] %2, %0\n\t"
1186                              "srl %0, 0x18, %0\n\t" :
1187                              "=r" (swift_rev) :
1188                              "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1189         srmmu_name = "Fujitsu Swift";
1190         switch (swift_rev) {
1191         case 0x11:
1192         case 0x20:
1193         case 0x23:
1194         case 0x30:
1195                 srmmu_modtype = Swift_lots_o_bugs;
1196                 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1197                 /*
1198                  * Gee george, I wonder why Sun is so hush hush about
1199                  * this hardware bug... really braindamage stuff going
1200                  * on here.  However I think we can find a way to avoid
1201                  * all of the workaround overhead under Linux.  Basically,
1202                  * any page fault can cause kernel pages to become user
1203                  * accessible (the mmu gets confused and clears some of
1204                  * the ACC bits in kernel ptes).  Aha, sounds pretty
1205                  * horrible eh?  But wait, after extensive testing it appears
1206                  * that if you use pgd_t level large kernel pte's (like the
1207                  * 4MB pages on the Pentium) the bug does not get tripped
1208                  * at all.  This avoids almost all of the major overhead.
1209                  * Welcome to a world where your vendor tells you to,
1210                  * "apply this kernel patch" instead of "sorry for the
1211                  * broken hardware, send it back and we'll give you
1212                  * properly functioning parts"
1213                  */
1214                 break;
1215         case 0x25:
1216         case 0x31:
1217                 srmmu_modtype = Swift_bad_c;
1218                 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1219                 /*
1220                  * You see Sun allude to this hardware bug but never
1221                  * admit things directly, they'll say things like,
1222                  * "the Swift chip cache problems" or similar.
1223                  */
1224                 break;
1225         default:
1226                 srmmu_modtype = Swift_ok;
1227                 break;
1228         }
1229
1230         sparc32_cachetlb_ops = &swift_ops;
1231         flush_page_for_dma_global = 0;
1232
1233         /*
1234          * Are you now convinced that the Swift is one of the
1235          * biggest VLSI abortions of all time?  Bravo Fujitsu!
1236          * Fujitsu, the !#?!%$'d up processor people.  I bet if
1237          * you examined the microcode of the Swift you'd find
1238          * XXX's all over the place.
1239          */
1240         poke_srmmu = poke_swift;
1241 }
1242
1243 static void turbosparc_flush_cache_all(void)
1244 {
1245         flush_user_windows();
1246         turbosparc_idflash_clear();
1247 }
1248
1249 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1250 {
1251         FLUSH_BEGIN(mm)
1252         flush_user_windows();
1253         turbosparc_idflash_clear();
1254         FLUSH_END
1255 }
1256
1257 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1258 {
1259         FLUSH_BEGIN(vma->vm_mm)
1260         flush_user_windows();
1261         turbosparc_idflash_clear();
1262         FLUSH_END
1263 }
1264
1265 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1266 {
1267         FLUSH_BEGIN(vma->vm_mm)
1268         flush_user_windows();
1269         if (vma->vm_flags & VM_EXEC)
1270                 turbosparc_flush_icache();
1271         turbosparc_flush_dcache();
1272         FLUSH_END
1273 }
1274
1275 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1276 static void turbosparc_flush_page_to_ram(unsigned long page)
1277 {
1278 #ifdef TURBOSPARC_WRITEBACK
1279         volatile unsigned long clear;
1280
1281         if (srmmu_probe(page))
1282                 turbosparc_flush_page_cache(page);
1283         clear = srmmu_get_fstatus();
1284 #endif
1285 }
1286
1287 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1288 {
1289 }
1290
1291 static void turbosparc_flush_page_for_dma(unsigned long page)
1292 {
1293         turbosparc_flush_dcache();
1294 }
1295
1296 static void turbosparc_flush_tlb_all(void)
1297 {
1298         srmmu_flush_whole_tlb();
1299 }
1300
1301 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1302 {
1303         FLUSH_BEGIN(mm)
1304         srmmu_flush_whole_tlb();
1305         FLUSH_END
1306 }
1307
1308 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1309 {
1310         FLUSH_BEGIN(vma->vm_mm)
1311         srmmu_flush_whole_tlb();
1312         FLUSH_END
1313 }
1314
1315 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1316 {
1317         FLUSH_BEGIN(vma->vm_mm)
1318         srmmu_flush_whole_tlb();
1319         FLUSH_END
1320 }
1321
1322
1323 static void poke_turbosparc(void)
1324 {
1325         unsigned long mreg = srmmu_get_mmureg();
1326         unsigned long ccreg;
1327
1328         /* Clear any crap from the cache or else... */
1329         turbosparc_flush_cache_all();
1330         /* Temporarily disable I & D caches */
1331         mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE);
1332         mreg &= ~(TURBOSPARC_PCENABLE);         /* Don't check parity */
1333         srmmu_set_mmureg(mreg);
1334
1335         ccreg = turbosparc_get_ccreg();
1336
1337 #ifdef TURBOSPARC_WRITEBACK
1338         ccreg |= (TURBOSPARC_SNENABLE);         /* Do DVMA snooping in Dcache */
1339         ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1340                         /* Write-back D-cache, emulate VLSI
1341                          * abortion number three, not number one */
1342 #else
1343         /* For now let's play safe, optimize later */
1344         ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1345                         /* Do DVMA snooping in Dcache, Write-thru D-cache */
1346         ccreg &= ~(TURBOSPARC_uS2);
1347                         /* Emulate VLSI abortion number three, not number one */
1348 #endif
1349
1350         switch (ccreg & 7) {
1351         case 0: /* No SE cache */
1352         case 7: /* Test mode */
1353                 break;
1354         default:
1355                 ccreg |= (TURBOSPARC_SCENABLE);
1356         }
1357         turbosparc_set_ccreg(ccreg);
1358
1359         mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1360         mreg |= (TURBOSPARC_ICSNOOP);           /* Icache snooping on */
1361         srmmu_set_mmureg(mreg);
1362 }
1363
1364 static const struct sparc32_cachetlb_ops turbosparc_ops = {
1365         .cache_all      = turbosparc_flush_cache_all,
1366         .cache_mm       = turbosparc_flush_cache_mm,
1367         .cache_page     = turbosparc_flush_cache_page,
1368         .cache_range    = turbosparc_flush_cache_range,
1369         .tlb_all        = turbosparc_flush_tlb_all,
1370         .tlb_mm         = turbosparc_flush_tlb_mm,
1371         .tlb_page       = turbosparc_flush_tlb_page,
1372         .tlb_range      = turbosparc_flush_tlb_range,
1373         .page_to_ram    = turbosparc_flush_page_to_ram,
1374         .sig_insns      = turbosparc_flush_sig_insns,
1375         .page_for_dma   = turbosparc_flush_page_for_dma,
1376 };
1377
1378 static void __init init_turbosparc(void)
1379 {
1380         srmmu_name = "Fujitsu TurboSparc";
1381         srmmu_modtype = TurboSparc;
1382         sparc32_cachetlb_ops = &turbosparc_ops;
1383         poke_srmmu = poke_turbosparc;
1384 }
1385
1386 static void poke_tsunami(void)
1387 {
1388         unsigned long mreg = srmmu_get_mmureg();
1389
1390         tsunami_flush_icache();
1391         tsunami_flush_dcache();
1392         mreg &= ~TSUNAMI_ITD;
1393         mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1394         srmmu_set_mmureg(mreg);
1395 }
1396
1397 static const struct sparc32_cachetlb_ops tsunami_ops = {
1398         .cache_all      = tsunami_flush_cache_all,
1399         .cache_mm       = tsunami_flush_cache_mm,
1400         .cache_page     = tsunami_flush_cache_page,
1401         .cache_range    = tsunami_flush_cache_range,
1402         .tlb_all        = tsunami_flush_tlb_all,
1403         .tlb_mm         = tsunami_flush_tlb_mm,
1404         .tlb_page       = tsunami_flush_tlb_page,
1405         .tlb_range      = tsunami_flush_tlb_range,
1406         .page_to_ram    = tsunami_flush_page_to_ram,
1407         .sig_insns      = tsunami_flush_sig_insns,
1408         .page_for_dma   = tsunami_flush_page_for_dma,
1409 };
1410
1411 static void __init init_tsunami(void)
1412 {
1413         /*
1414          * Tsunami's pretty sane, Sun and TI actually got it
1415          * somewhat right this time.  Fujitsu should have
1416          * taken some lessons from them.
1417          */
1418
1419         srmmu_name = "TI Tsunami";
1420         srmmu_modtype = Tsunami;
1421         sparc32_cachetlb_ops = &tsunami_ops;
1422         poke_srmmu = poke_tsunami;
1423
1424         tsunami_setup_blockops();
1425 }
1426
1427 static void poke_viking(void)
1428 {
1429         unsigned long mreg = srmmu_get_mmureg();
1430         static int smp_catch;
1431
1432         if (viking_mxcc_present) {
1433                 unsigned long mxcc_control = mxcc_get_creg();
1434
1435                 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1436                 mxcc_control &= ~(MXCC_CTL_RRC);
1437                 mxcc_set_creg(mxcc_control);
1438
1439                 /*
1440                  * We don't need memory parity checks.
1441                  * XXX This is a mess, have to dig out later. ecd.
1442                 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1443                  */
1444
1445                 /* We do cache ptables on MXCC. */
1446                 mreg |= VIKING_TCENABLE;
1447         } else {
1448                 unsigned long bpreg;
1449
1450                 mreg &= ~(VIKING_TCENABLE);
1451                 if (smp_catch++) {
1452                         /* Must disable mixed-cmd mode here for other cpu's. */
1453                         bpreg = viking_get_bpreg();
1454                         bpreg &= ~(VIKING_ACTION_MIX);
1455                         viking_set_bpreg(bpreg);
1456
1457                         /* Just in case PROM does something funny. */
1458                         msi_set_sync();
1459                 }
1460         }
1461
1462         mreg |= VIKING_SPENABLE;
1463         mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1464         mreg |= VIKING_SBENABLE;
1465         mreg &= ~(VIKING_ACENABLE);
1466         srmmu_set_mmureg(mreg);
1467 }
1468
1469 static struct sparc32_cachetlb_ops viking_ops __ro_after_init = {
1470         .cache_all      = viking_flush_cache_all,
1471         .cache_mm       = viking_flush_cache_mm,
1472         .cache_page     = viking_flush_cache_page,
1473         .cache_range    = viking_flush_cache_range,
1474         .tlb_all        = viking_flush_tlb_all,
1475         .tlb_mm         = viking_flush_tlb_mm,
1476         .tlb_page       = viking_flush_tlb_page,
1477         .tlb_range      = viking_flush_tlb_range,
1478         .page_to_ram    = viking_flush_page_to_ram,
1479         .sig_insns      = viking_flush_sig_insns,
1480         .page_for_dma   = viking_flush_page_for_dma,
1481 };
1482
1483 #ifdef CONFIG_SMP
1484 /* On sun4d the cpu broadcasts local TLB flushes, so we can just
1485  * perform the local TLB flush and all the other cpus will see it.
1486  * But, unfortunately, there is a bug in the sun4d XBUS backplane
1487  * that requires that we add some synchronization to these flushes.
1488  *
1489  * The bug is that the fifo which keeps track of all the pending TLB
1490  * broadcasts in the system is an entry or two too small, so if we
1491  * have too many going at once we'll overflow that fifo and lose a TLB
1492  * flush resulting in corruption.
1493  *
1494  * Our workaround is to take a global spinlock around the TLB flushes,
1495  * which guarentees we won't ever have too many pending.  It's a big
1496  * hammer, but a semaphore like system to make sure we only have N TLB
1497  * flushes going at once will require SMP locking anyways so there's
1498  * no real value in trying any harder than this.
1499  */
1500 static struct sparc32_cachetlb_ops viking_sun4d_smp_ops __ro_after_init = {
1501         .cache_all      = viking_flush_cache_all,
1502         .cache_mm       = viking_flush_cache_mm,
1503         .cache_page     = viking_flush_cache_page,
1504         .cache_range    = viking_flush_cache_range,
1505         .tlb_all        = sun4dsmp_flush_tlb_all,
1506         .tlb_mm         = sun4dsmp_flush_tlb_mm,
1507         .tlb_page       = sun4dsmp_flush_tlb_page,
1508         .tlb_range      = sun4dsmp_flush_tlb_range,
1509         .page_to_ram    = viking_flush_page_to_ram,
1510         .sig_insns      = viking_flush_sig_insns,
1511         .page_for_dma   = viking_flush_page_for_dma,
1512 };
1513 #endif
1514
1515 static void __init init_viking(void)
1516 {
1517         unsigned long mreg = srmmu_get_mmureg();
1518
1519         /* Ahhh, the viking.  SRMMU VLSI abortion number two... */
1520         if (mreg & VIKING_MMODE) {
1521                 srmmu_name = "TI Viking";
1522                 viking_mxcc_present = 0;
1523                 msi_set_sync();
1524
1525                 /*
1526                  * We need this to make sure old viking takes no hits
1527                  * on it's cache for dma snoops to workaround the
1528                  * "load from non-cacheable memory" interrupt bug.
1529                  * This is only necessary because of the new way in
1530                  * which we use the IOMMU.
1531                  */
1532                 viking_ops.page_for_dma = viking_flush_page;
1533 #ifdef CONFIG_SMP
1534                 viking_sun4d_smp_ops.page_for_dma = viking_flush_page;
1535 #endif
1536                 flush_page_for_dma_global = 0;
1537         } else {
1538                 srmmu_name = "TI Viking/MXCC";
1539                 viking_mxcc_present = 1;
1540                 srmmu_cache_pagetables = 1;
1541         }
1542
1543         sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1544                 &viking_ops;
1545 #ifdef CONFIG_SMP
1546         if (sparc_cpu_model == sun4d)
1547                 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1548                         &viking_sun4d_smp_ops;
1549 #endif
1550
1551         poke_srmmu = poke_viking;
1552 }
1553
1554 /* Probe for the srmmu chip version. */
1555 static void __init get_srmmu_type(void)
1556 {
1557         unsigned long mreg, psr;
1558         unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1559
1560         srmmu_modtype = SRMMU_INVAL_MOD;
1561         hwbug_bitmask = 0;
1562
1563         mreg = srmmu_get_mmureg(); psr = get_psr();
1564         mod_typ = (mreg & 0xf0000000) >> 28;
1565         mod_rev = (mreg & 0x0f000000) >> 24;
1566         psr_typ = (psr >> 28) & 0xf;
1567         psr_vers = (psr >> 24) & 0xf;
1568
1569         /* First, check for sparc-leon. */
1570         if (sparc_cpu_model == sparc_leon) {
1571                 init_leon();
1572                 return;
1573         }
1574
1575         /* Second, check for HyperSparc or Cypress. */
1576         if (mod_typ == 1) {
1577                 switch (mod_rev) {
1578                 case 7:
1579                         /* UP or MP Hypersparc */
1580                         init_hypersparc();
1581                         break;
1582                 case 0:
1583                 case 2:
1584                 case 10:
1585                 case 11:
1586                 case 12:
1587                 case 13:
1588                 case 14:
1589                 case 15:
1590                 default:
1591                         prom_printf("Sparc-Linux Cypress support does not longer exit.\n");
1592                         prom_halt();
1593                         break;
1594                 }
1595                 return;
1596         }
1597
1598         /* Now Fujitsu TurboSparc. It might happen that it is
1599          * in Swift emulation mode, so we will check later...
1600          */
1601         if (psr_typ == 0 && psr_vers == 5) {
1602                 init_turbosparc();
1603                 return;
1604         }
1605
1606         /* Next check for Fujitsu Swift. */
1607         if (psr_typ == 0 && psr_vers == 4) {
1608                 phandle cpunode;
1609                 char node_str[128];
1610
1611                 /* Look if it is not a TurboSparc emulating Swift... */
1612                 cpunode = prom_getchild(prom_root_node);
1613                 while ((cpunode = prom_getsibling(cpunode)) != 0) {
1614                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1615                         if (!strcmp(node_str, "cpu")) {
1616                                 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
1617                                     prom_getintdefault(cpunode, "psr-version", 1) == 5) {
1618                                         init_turbosparc();
1619                                         return;
1620                                 }
1621                                 break;
1622                         }
1623                 }
1624
1625                 init_swift();
1626                 return;
1627         }
1628
1629         /* Now the Viking family of srmmu. */
1630         if (psr_typ == 4 &&
1631            ((psr_vers == 0) ||
1632             ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
1633                 init_viking();
1634                 return;
1635         }
1636
1637         /* Finally the Tsunami. */
1638         if (psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
1639                 init_tsunami();
1640                 return;
1641         }
1642
1643         /* Oh well */
1644         srmmu_is_bad();
1645 }
1646
1647 #ifdef CONFIG_SMP
1648 /* Local cross-calls. */
1649 static void smp_flush_page_for_dma(unsigned long page)
1650 {
1651         xc1((smpfunc_t) local_ops->page_for_dma, page);
1652         local_ops->page_for_dma(page);
1653 }
1654
1655 static void smp_flush_cache_all(void)
1656 {
1657         xc0((smpfunc_t) local_ops->cache_all);
1658         local_ops->cache_all();
1659 }
1660
1661 static void smp_flush_tlb_all(void)
1662 {
1663         xc0((smpfunc_t) local_ops->tlb_all);
1664         local_ops->tlb_all();
1665 }
1666
1667 static void smp_flush_cache_mm(struct mm_struct *mm)
1668 {
1669         if (mm->context != NO_CONTEXT) {
1670                 cpumask_t cpu_mask;
1671                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1672                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1673                 if (!cpumask_empty(&cpu_mask))
1674                         xc1((smpfunc_t) local_ops->cache_mm, (unsigned long) mm);
1675                 local_ops->cache_mm(mm);
1676         }
1677 }
1678
1679 static void smp_flush_tlb_mm(struct mm_struct *mm)
1680 {
1681         if (mm->context != NO_CONTEXT) {
1682                 cpumask_t cpu_mask;
1683                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1684                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1685                 if (!cpumask_empty(&cpu_mask)) {
1686                         xc1((smpfunc_t) local_ops->tlb_mm, (unsigned long) mm);
1687                         if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm)
1688                                 cpumask_copy(mm_cpumask(mm),
1689                                              cpumask_of(smp_processor_id()));
1690                 }
1691                 local_ops->tlb_mm(mm);
1692         }
1693 }
1694
1695 static void smp_flush_cache_range(struct vm_area_struct *vma,
1696                                   unsigned long start,
1697                                   unsigned long end)
1698 {
1699         struct mm_struct *mm = vma->vm_mm;
1700
1701         if (mm->context != NO_CONTEXT) {
1702                 cpumask_t cpu_mask;
1703                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1704                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1705                 if (!cpumask_empty(&cpu_mask))
1706                         xc3((smpfunc_t) local_ops->cache_range,
1707                             (unsigned long) vma, start, end);
1708                 local_ops->cache_range(vma, start, end);
1709         }
1710 }
1711
1712 static void smp_flush_tlb_range(struct vm_area_struct *vma,
1713                                 unsigned long start,
1714                                 unsigned long end)
1715 {
1716         struct mm_struct *mm = vma->vm_mm;
1717
1718         if (mm->context != NO_CONTEXT) {
1719                 cpumask_t cpu_mask;
1720                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1721                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1722                 if (!cpumask_empty(&cpu_mask))
1723                         xc3((smpfunc_t) local_ops->tlb_range,
1724                             (unsigned long) vma, start, end);
1725                 local_ops->tlb_range(vma, start, end);
1726         }
1727 }
1728
1729 static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1730 {
1731         struct mm_struct *mm = vma->vm_mm;
1732
1733         if (mm->context != NO_CONTEXT) {
1734                 cpumask_t cpu_mask;
1735                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1736                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1737                 if (!cpumask_empty(&cpu_mask))
1738                         xc2((smpfunc_t) local_ops->cache_page,
1739                             (unsigned long) vma, page);
1740                 local_ops->cache_page(vma, page);
1741         }
1742 }
1743
1744 static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1745 {
1746         struct mm_struct *mm = vma->vm_mm;
1747
1748         if (mm->context != NO_CONTEXT) {
1749                 cpumask_t cpu_mask;
1750                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1751                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1752                 if (!cpumask_empty(&cpu_mask))
1753                         xc2((smpfunc_t) local_ops->tlb_page,
1754                             (unsigned long) vma, page);
1755                 local_ops->tlb_page(vma, page);
1756         }
1757 }
1758
1759 static void smp_flush_page_to_ram(unsigned long page)
1760 {
1761         /* Current theory is that those who call this are the one's
1762          * who have just dirtied their cache with the pages contents
1763          * in kernel space, therefore we only run this on local cpu.
1764          *
1765          * XXX This experiment failed, research further... -DaveM
1766          */
1767 #if 1
1768         xc1((smpfunc_t) local_ops->page_to_ram, page);
1769 #endif
1770         local_ops->page_to_ram(page);
1771 }
1772
1773 static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1774 {
1775         cpumask_t cpu_mask;
1776         cpumask_copy(&cpu_mask, mm_cpumask(mm));
1777         cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1778         if (!cpumask_empty(&cpu_mask))
1779                 xc2((smpfunc_t) local_ops->sig_insns,
1780                     (unsigned long) mm, insn_addr);
1781         local_ops->sig_insns(mm, insn_addr);
1782 }
1783
1784 static struct sparc32_cachetlb_ops smp_cachetlb_ops __ro_after_init = {
1785         .cache_all      = smp_flush_cache_all,
1786         .cache_mm       = smp_flush_cache_mm,
1787         .cache_page     = smp_flush_cache_page,
1788         .cache_range    = smp_flush_cache_range,
1789         .tlb_all        = smp_flush_tlb_all,
1790         .tlb_mm         = smp_flush_tlb_mm,
1791         .tlb_page       = smp_flush_tlb_page,
1792         .tlb_range      = smp_flush_tlb_range,
1793         .page_to_ram    = smp_flush_page_to_ram,
1794         .sig_insns      = smp_flush_sig_insns,
1795         .page_for_dma   = smp_flush_page_for_dma,
1796 };
1797 #endif
1798
1799 /* Load up routines and constants for sun4m and sun4d mmu */
1800 void __init load_mmu(void)
1801 {
1802         /* Functions */
1803         get_srmmu_type();
1804
1805 #ifdef CONFIG_SMP
1806         /* El switcheroo... */
1807         local_ops = sparc32_cachetlb_ops;
1808
1809         if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) {
1810                 smp_cachetlb_ops.tlb_all = local_ops->tlb_all;
1811                 smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm;
1812                 smp_cachetlb_ops.tlb_range = local_ops->tlb_range;
1813                 smp_cachetlb_ops.tlb_page = local_ops->tlb_page;
1814         }
1815
1816         if (poke_srmmu == poke_viking) {
1817                 /* Avoid unnecessary cross calls. */
1818                 smp_cachetlb_ops.cache_all = local_ops->cache_all;
1819                 smp_cachetlb_ops.cache_mm = local_ops->cache_mm;
1820                 smp_cachetlb_ops.cache_range = local_ops->cache_range;
1821                 smp_cachetlb_ops.cache_page = local_ops->cache_page;
1822
1823                 smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram;
1824                 smp_cachetlb_ops.sig_insns = local_ops->sig_insns;
1825                 smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma;
1826         }
1827
1828         /* It really is const after this point. */
1829         sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1830                 &smp_cachetlb_ops;
1831 #endif
1832
1833         if (sparc_cpu_model != sun4d)
1834                 ld_mmu_iommu();
1835 #ifdef CONFIG_SMP
1836         if (sparc_cpu_model == sun4d)
1837                 sun4d_init_smp();
1838         else if (sparc_cpu_model == sparc_leon)
1839                 leon_init_smp();
1840         else
1841                 sun4m_init_smp();
1842 #endif
1843 }