1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sparc64/mm/init.c
5 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 #include <linux/extable.h>
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/memblock.h>
16 #include <linux/hugetlb.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/ioport.h>
27 #include <linux/percpu.h>
28 #include <linux/mmzone.h>
29 #include <linux/gfp.h>
33 #include <asm/pgalloc.h>
34 #include <asm/oplib.h>
35 #include <asm/iommu.h>
37 #include <linux/uaccess.h>
38 #include <asm/mmu_context.h>
39 #include <asm/tlbflush.h>
41 #include <asm/starfire.h>
43 #include <asm/spitfire.h>
44 #include <asm/sections.h>
46 #include <asm/hypervisor.h>
48 #include <asm/mdesc.h>
49 #include <asm/cpudata.h>
50 #include <asm/setup.h>
55 unsigned long kern_linear_pte_xor[4] __read_mostly;
56 static unsigned long page_cache4v_flag;
58 /* A bitmap, two bits for every 256MB of physical memory. These two
59 * bits determine what page size we use for kernel linear
60 * translations. They form an index into kern_linear_pte_xor[]. The
61 * value in the indexed slot is XOR'd with the TLB miss virtual
62 * address to form the resulting TTE. The mapping is:
69 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
70 * support 2GB pages, and hopefully future cpus will support the 16GB
71 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
72 * if these larger page sizes are not supported by the cpu.
74 * It would be nice to determine this from the machine description
75 * 'cpu' properties, but we need to have this table setup before the
76 * MDESC is initialized.
79 #ifndef CONFIG_DEBUG_PAGEALLOC
80 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
81 * Space is allocated for this right after the trap table in
82 * arch/sparc64/kernel/head.S
84 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
86 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
88 static unsigned long cpu_pgsz_mask;
90 #define MAX_BANKS 1024
92 static struct linux_prom64_registers pavail[MAX_BANKS];
93 static int pavail_ents;
95 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
97 static int cmp_p64(const void *a, const void *b)
99 const struct linux_prom64_registers *x = a, *y = b;
101 if (x->phys_addr > y->phys_addr)
103 if (x->phys_addr < y->phys_addr)
108 static void __init read_obp_memory(const char *property,
109 struct linux_prom64_registers *regs,
112 phandle node = prom_finddevice("/memory");
113 int prop_size = prom_getproplen(node, property);
116 ents = prop_size / sizeof(struct linux_prom64_registers);
117 if (ents > MAX_BANKS) {
118 prom_printf("The machine has more %s property entries than "
119 "this kernel can support (%d).\n",
120 property, MAX_BANKS);
124 ret = prom_getproperty(node, property, (char *) regs, prop_size);
126 prom_printf("Couldn't get %s property from /memory.\n",
131 /* Sanitize what we got from the firmware, by page aligning
134 for (i = 0; i < ents; i++) {
135 unsigned long base, size;
137 base = regs[i].phys_addr;
138 size = regs[i].reg_size;
141 if (base & ~PAGE_MASK) {
142 unsigned long new_base = PAGE_ALIGN(base);
144 size -= new_base - base;
145 if ((long) size < 0L)
150 /* If it is empty, simply get rid of it.
151 * This simplifies the logic of the other
152 * functions that process these arrays.
154 memmove(®s[i], ®s[i + 1],
155 (ents - i - 1) * sizeof(regs[0]));
160 regs[i].phys_addr = base;
161 regs[i].reg_size = size;
166 sort(regs, ents, sizeof(struct linux_prom64_registers),
170 /* Kernel physical address base and size in bytes. */
171 unsigned long kern_base __read_mostly;
172 unsigned long kern_size __read_mostly;
174 /* Initial ramdisk setup */
175 extern unsigned long sparc_ramdisk_image64;
176 extern unsigned int sparc_ramdisk_image;
177 extern unsigned int sparc_ramdisk_size;
179 struct page *mem_map_zero __read_mostly;
180 EXPORT_SYMBOL(mem_map_zero);
182 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
184 unsigned long sparc64_kern_pri_context __read_mostly;
185 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
186 unsigned long sparc64_kern_sec_context __read_mostly;
188 int num_kernel_image_mappings;
190 #ifdef CONFIG_DEBUG_DCFLUSH
191 atomic_t dcpage_flushes = ATOMIC_INIT(0);
193 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
197 inline void flush_dcache_page_impl(struct page *page)
199 BUG_ON(tlb_type == hypervisor);
200 #ifdef CONFIG_DEBUG_DCFLUSH
201 atomic_inc(&dcpage_flushes);
204 #ifdef DCACHE_ALIASING_POSSIBLE
205 __flush_dcache_page(page_address(page),
206 ((tlb_type == spitfire) &&
207 page_mapping_file(page) != NULL));
209 if (page_mapping_file(page) != NULL &&
210 tlb_type == spitfire)
211 __flush_icache_page(__pa(page_address(page)));
215 #define PG_dcache_dirty PG_arch_1
216 #define PG_dcache_cpu_shift 32UL
217 #define PG_dcache_cpu_mask \
218 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
220 #define dcache_dirty_cpu(page) \
221 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
223 static inline void set_dcache_dirty(struct page *page, int this_cpu)
225 unsigned long mask = this_cpu;
226 unsigned long non_cpu_bits;
228 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
229 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
231 __asm__ __volatile__("1:\n\t"
233 "and %%g7, %1, %%g1\n\t"
234 "or %%g1, %0, %%g1\n\t"
235 "casx [%2], %%g7, %%g1\n\t"
237 "bne,pn %%xcc, 1b\n\t"
240 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
244 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
246 unsigned long mask = (1UL << PG_dcache_dirty);
248 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
251 "srlx %%g7, %4, %%g1\n\t"
252 "and %%g1, %3, %%g1\n\t"
254 "bne,pn %%icc, 2f\n\t"
255 " andn %%g7, %1, %%g1\n\t"
256 "casx [%2], %%g7, %%g1\n\t"
258 "bne,pn %%xcc, 1b\n\t"
262 : "r" (cpu), "r" (mask), "r" (&page->flags),
263 "i" (PG_dcache_cpu_mask),
264 "i" (PG_dcache_cpu_shift)
268 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
270 unsigned long tsb_addr = (unsigned long) ent;
272 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
273 tsb_addr = __pa(tsb_addr);
275 __tsb_insert(tsb_addr, tag, pte);
278 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
280 static void flush_dcache(unsigned long pfn)
284 page = pfn_to_page(pfn);
286 unsigned long pg_flags;
288 pg_flags = page->flags;
289 if (pg_flags & (1UL << PG_dcache_dirty)) {
290 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
292 int this_cpu = get_cpu();
294 /* This is just to optimize away some function calls
298 flush_dcache_page_impl(page);
300 smp_flush_dcache_page_impl(page, cpu);
302 clear_dcache_dirty_cpu(page, cpu);
309 /* mm->context.lock must be held */
310 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
311 unsigned long tsb_hash_shift, unsigned long address,
314 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
320 tsb += ((address >> tsb_hash_shift) &
321 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
322 tag = (address >> 22UL);
323 tsb_insert(tsb, tag, tte);
326 #ifdef CONFIG_HUGETLB_PAGE
327 static int __init hugetlbpage_init(void)
329 hugetlb_add_hstate(HPAGE_64K_SHIFT - PAGE_SHIFT);
330 hugetlb_add_hstate(HPAGE_SHIFT - PAGE_SHIFT);
331 hugetlb_add_hstate(HPAGE_256MB_SHIFT - PAGE_SHIFT);
332 hugetlb_add_hstate(HPAGE_2GB_SHIFT - PAGE_SHIFT);
337 arch_initcall(hugetlbpage_init);
339 static void __init pud_huge_patch(void)
341 struct pud_huge_patch_entry *p;
344 p = &__pud_huge_patch;
346 *(unsigned int *)addr = p->insn;
348 __asm__ __volatile__("flush %0" : : "r" (addr));
351 bool __init arch_hugetlb_valid_size(unsigned long size)
353 unsigned int hugepage_shift = ilog2(size);
354 unsigned short hv_pgsz_idx;
355 unsigned int hv_pgsz_mask;
357 switch (hugepage_shift) {
358 case HPAGE_16GB_SHIFT:
359 hv_pgsz_mask = HV_PGSZ_MASK_16GB;
360 hv_pgsz_idx = HV_PGSZ_IDX_16GB;
363 case HPAGE_2GB_SHIFT:
364 hv_pgsz_mask = HV_PGSZ_MASK_2GB;
365 hv_pgsz_idx = HV_PGSZ_IDX_2GB;
367 case HPAGE_256MB_SHIFT:
368 hv_pgsz_mask = HV_PGSZ_MASK_256MB;
369 hv_pgsz_idx = HV_PGSZ_IDX_256MB;
372 hv_pgsz_mask = HV_PGSZ_MASK_4MB;
373 hv_pgsz_idx = HV_PGSZ_IDX_4MB;
375 case HPAGE_64K_SHIFT:
376 hv_pgsz_mask = HV_PGSZ_MASK_64K;
377 hv_pgsz_idx = HV_PGSZ_IDX_64K;
383 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U)
388 #endif /* CONFIG_HUGETLB_PAGE */
390 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
392 struct mm_struct *mm;
397 if (tlb_type != hypervisor) {
398 unsigned long pfn = pte_pfn(pte);
406 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
407 if (!pte_accessible(mm, pte))
410 spin_lock_irqsave(&mm->context.lock, flags);
413 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
414 if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) {
415 unsigned long hugepage_size = PAGE_SIZE;
417 if (is_vm_hugetlb_page(vma))
418 hugepage_size = huge_page_size(hstate_vma(vma));
420 if (hugepage_size >= PUD_SIZE) {
421 unsigned long mask = 0x1ffc00000UL;
423 /* Transfer bits [32:22] from address to resolve
426 pte_val(pte) &= ~mask;
427 pte_val(pte) |= (address & mask);
428 } else if (hugepage_size >= PMD_SIZE) {
429 /* We are fabricating 8MB pages using 4MB
432 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
435 if (hugepage_size >= PMD_SIZE) {
436 __update_mmu_tsb_insert(mm, MM_TSB_HUGE,
437 REAL_HPAGE_SHIFT, address, pte_val(pte));
443 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
444 address, pte_val(pte));
446 spin_unlock_irqrestore(&mm->context.lock, flags);
449 void flush_dcache_page(struct page *page)
451 struct address_space *mapping;
454 if (tlb_type == hypervisor)
457 /* Do not bother with the expensive D-cache flush if it
458 * is merely the zero page. The 'bigcore' testcase in GDB
459 * causes this case to run millions of times.
461 if (page == ZERO_PAGE(0))
464 this_cpu = get_cpu();
466 mapping = page_mapping_file(page);
467 if (mapping && !mapping_mapped(mapping)) {
468 int dirty = test_bit(PG_dcache_dirty, &page->flags);
470 int dirty_cpu = dcache_dirty_cpu(page);
472 if (dirty_cpu == this_cpu)
474 smp_flush_dcache_page_impl(page, dirty_cpu);
476 set_dcache_dirty(page, this_cpu);
478 /* We could delay the flush for the !page_mapping
479 * case too. But that case is for exec env/arg
480 * pages and those are %99 certainly going to get
481 * faulted into the tlb (and thus flushed) anyways.
483 flush_dcache_page_impl(page);
489 EXPORT_SYMBOL(flush_dcache_page);
491 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
493 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
494 if (tlb_type == spitfire) {
497 /* This code only runs on Spitfire cpus so this is
498 * why we can assume _PAGE_PADDR_4U.
500 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
501 unsigned long paddr, mask = _PAGE_PADDR_4U;
503 if (kaddr >= PAGE_OFFSET)
504 paddr = kaddr & mask;
506 pte_t *ptep = virt_to_kpte(kaddr);
508 paddr = pte_val(*ptep) & mask;
510 __flush_icache_page(paddr);
514 EXPORT_SYMBOL(flush_icache_range);
516 void mmu_info(struct seq_file *m)
518 static const char *pgsz_strings[] = {
519 "8K", "64K", "512K", "4MB", "32MB",
520 "256MB", "2GB", "16GB",
524 if (tlb_type == cheetah)
525 seq_printf(m, "MMU Type\t: Cheetah\n");
526 else if (tlb_type == cheetah_plus)
527 seq_printf(m, "MMU Type\t: Cheetah+\n");
528 else if (tlb_type == spitfire)
529 seq_printf(m, "MMU Type\t: Spitfire\n");
530 else if (tlb_type == hypervisor)
531 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
533 seq_printf(m, "MMU Type\t: ???\n");
535 seq_printf(m, "MMU PGSZs\t: ");
537 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
538 if (cpu_pgsz_mask & (1UL << i)) {
539 seq_printf(m, "%s%s",
540 printed ? "," : "", pgsz_strings[i]);
546 #ifdef CONFIG_DEBUG_DCFLUSH
547 seq_printf(m, "DCPageFlushes\t: %d\n",
548 atomic_read(&dcpage_flushes));
550 seq_printf(m, "DCPageFlushesXC\t: %d\n",
551 atomic_read(&dcpage_flushes_xcall));
552 #endif /* CONFIG_SMP */
553 #endif /* CONFIG_DEBUG_DCFLUSH */
556 struct linux_prom_translation prom_trans[512] __read_mostly;
557 unsigned int prom_trans_ents __read_mostly;
559 unsigned long kern_locked_tte_data;
561 /* The obp translations are saved based on 8k pagesize, since obp can
562 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
563 * HI_OBP_ADDRESS range are handled in ktlb.S.
565 static inline int in_obp_range(unsigned long vaddr)
567 return (vaddr >= LOW_OBP_ADDRESS &&
568 vaddr < HI_OBP_ADDRESS);
571 static int cmp_ptrans(const void *a, const void *b)
573 const struct linux_prom_translation *x = a, *y = b;
575 if (x->virt > y->virt)
577 if (x->virt < y->virt)
582 /* Read OBP translations property into 'prom_trans[]'. */
583 static void __init read_obp_translations(void)
585 int n, node, ents, first, last, i;
587 node = prom_finddevice("/virtual-memory");
588 n = prom_getproplen(node, "translations");
589 if (unlikely(n == 0 || n == -1)) {
590 prom_printf("prom_mappings: Couldn't get size.\n");
593 if (unlikely(n > sizeof(prom_trans))) {
594 prom_printf("prom_mappings: Size %d is too big.\n", n);
598 if ((n = prom_getproperty(node, "translations",
599 (char *)&prom_trans[0],
600 sizeof(prom_trans))) == -1) {
601 prom_printf("prom_mappings: Couldn't get property.\n");
605 n = n / sizeof(struct linux_prom_translation);
609 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
612 /* Now kick out all the non-OBP entries. */
613 for (i = 0; i < ents; i++) {
614 if (in_obp_range(prom_trans[i].virt))
618 for (; i < ents; i++) {
619 if (!in_obp_range(prom_trans[i].virt))
624 for (i = 0; i < (last - first); i++) {
625 struct linux_prom_translation *src = &prom_trans[i + first];
626 struct linux_prom_translation *dest = &prom_trans[i];
630 for (; i < ents; i++) {
631 struct linux_prom_translation *dest = &prom_trans[i];
632 dest->virt = dest->size = dest->data = 0x0UL;
635 prom_trans_ents = last - first;
637 if (tlb_type == spitfire) {
638 /* Clear diag TTE bits. */
639 for (i = 0; i < prom_trans_ents; i++)
640 prom_trans[i].data &= ~0x0003fe0000000000UL;
643 /* Force execute bit on. */
644 for (i = 0; i < prom_trans_ents; i++)
645 prom_trans[i].data |= (tlb_type == hypervisor ?
646 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
649 static void __init hypervisor_tlb_lock(unsigned long vaddr,
653 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
656 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
657 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
662 static unsigned long kern_large_tte(unsigned long paddr);
664 static void __init remap_kernel(void)
666 unsigned long phys_page, tte_vaddr, tte_data;
667 int i, tlb_ent = sparc64_highest_locked_tlbent();
669 tte_vaddr = (unsigned long) KERNBASE;
670 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
671 tte_data = kern_large_tte(phys_page);
673 kern_locked_tte_data = tte_data;
675 /* Now lock us into the TLBs via Hypervisor or OBP. */
676 if (tlb_type == hypervisor) {
677 for (i = 0; i < num_kernel_image_mappings; i++) {
678 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
679 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
680 tte_vaddr += 0x400000;
681 tte_data += 0x400000;
684 for (i = 0; i < num_kernel_image_mappings; i++) {
685 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
686 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
687 tte_vaddr += 0x400000;
688 tte_data += 0x400000;
690 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
692 if (tlb_type == cheetah_plus) {
693 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
694 CTX_CHEETAH_PLUS_NUC);
695 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
696 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
701 static void __init inherit_prom_mappings(void)
703 /* Now fixup OBP's idea about where we really are mapped. */
704 printk("Remapping the kernel... ");
709 void prom_world(int enter)
714 __asm__ __volatile__("flushw");
717 void __flush_dcache_range(unsigned long start, unsigned long end)
721 if (tlb_type == spitfire) {
724 for (va = start; va < end; va += 32) {
725 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
729 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
732 for (va = start; va < end; va += 32)
733 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
737 "i" (ASI_DCACHE_INVALIDATE));
740 EXPORT_SYMBOL(__flush_dcache_range);
742 /* get_new_mmu_context() uses "cache + 1". */
743 DEFINE_SPINLOCK(ctx_alloc_lock);
744 unsigned long tlb_context_cache = CTX_FIRST_VERSION;
745 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
746 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
747 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
748 DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
750 static void mmu_context_wrap(void)
752 unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
753 unsigned long new_ver, new_ctx, old_ctx;
754 struct mm_struct *mm;
757 bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);
759 /* Reserve kernel context */
760 set_bit(0, mmu_context_bmap);
762 new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
763 if (unlikely(new_ver == 0))
764 new_ver = CTX_FIRST_VERSION;
765 tlb_context_cache = new_ver;
768 * Make sure that any new mm that are added into per_cpu_secondary_mm,
769 * are going to go through get_new_mmu_context() path.
774 * Updated versions to current on those CPUs that had valid secondary
777 for_each_online_cpu(cpu) {
779 * If a new mm is stored after we took this mm from the array,
780 * it will go into get_new_mmu_context() path, because we
781 * already bumped the version in tlb_context_cache.
783 mm = per_cpu(per_cpu_secondary_mm, cpu);
785 if (unlikely(!mm || mm == &init_mm))
788 old_ctx = mm->context.sparc64_ctx_val;
789 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
790 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
791 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
792 mm->context.sparc64_ctx_val = new_ctx;
797 /* Caller does TLB context flushing on local CPU if necessary.
798 * The caller also ensures that CTX_VALID(mm->context) is false.
800 * We must be careful about boundary cases so that we never
801 * let the user have CTX 0 (nucleus) or we ever use a CTX
802 * version of zero (and thus NO_CONTEXT would not be caught
803 * by version mis-match tests in mmu_context.h).
805 * Always invoked with interrupts disabled.
807 void get_new_mmu_context(struct mm_struct *mm)
809 unsigned long ctx, new_ctx;
810 unsigned long orig_pgsz_bits;
812 spin_lock(&ctx_alloc_lock);
814 /* wrap might have happened, test again if our context became valid */
815 if (unlikely(CTX_VALID(mm->context)))
817 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
818 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
819 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
820 if (new_ctx >= (1 << CTX_NR_BITS)) {
821 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
822 if (new_ctx >= ctx) {
827 if (mm->context.sparc64_ctx_val)
828 cpumask_clear(mm_cpumask(mm));
829 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
830 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
831 tlb_context_cache = new_ctx;
832 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
834 spin_unlock(&ctx_alloc_lock);
837 static int numa_enabled = 1;
838 static int numa_debug;
840 static int __init early_numa(char *p)
845 if (strstr(p, "off"))
848 if (strstr(p, "debug"))
853 early_param("numa", early_numa);
855 #define numadbg(f, a...) \
856 do { if (numa_debug) \
857 printk(KERN_INFO f, ## a); \
860 static void __init find_ramdisk(unsigned long phys_base)
862 #ifdef CONFIG_BLK_DEV_INITRD
863 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
864 unsigned long ramdisk_image;
866 /* Older versions of the bootloader only supported a
867 * 32-bit physical address for the ramdisk image
868 * location, stored at sparc_ramdisk_image. Newer
869 * SILO versions set sparc_ramdisk_image to zero and
870 * provide a full 64-bit physical address at
871 * sparc_ramdisk_image64.
873 ramdisk_image = sparc_ramdisk_image;
875 ramdisk_image = sparc_ramdisk_image64;
877 /* Another bootloader quirk. The bootloader normalizes
878 * the physical address to KERNBASE, so we have to
879 * factor that back out and add in the lowest valid
880 * physical page address to get the true physical address.
882 ramdisk_image -= KERNBASE;
883 ramdisk_image += phys_base;
885 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
886 ramdisk_image, sparc_ramdisk_size);
888 initrd_start = ramdisk_image;
889 initrd_end = ramdisk_image + sparc_ramdisk_size;
891 memblock_reserve(initrd_start, sparc_ramdisk_size);
893 initrd_start += PAGE_OFFSET;
894 initrd_end += PAGE_OFFSET;
899 struct node_mem_mask {
903 static struct node_mem_mask node_masks[MAX_NUMNODES];
904 static int num_node_masks;
906 #ifdef CONFIG_NEED_MULTIPLE_NODES
908 struct mdesc_mlgroup {
915 static struct mdesc_mlgroup *mlgroups;
916 static int num_mlgroups;
918 int numa_cpu_lookup_table[NR_CPUS];
919 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
921 struct mdesc_mblock {
924 u64 offset; /* RA-to-PA */
926 static struct mdesc_mblock *mblocks;
927 static int num_mblocks;
929 static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr)
931 struct mdesc_mblock *m = NULL;
934 for (i = 0; i < num_mblocks; i++) {
937 if (addr >= m->base &&
938 addr < (m->base + m->size)) {
946 static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid)
948 int prev_nid, new_nid;
950 prev_nid = NUMA_NO_NODE;
951 for ( ; start < end; start += PAGE_SIZE) {
952 for (new_nid = 0; new_nid < num_node_masks; new_nid++) {
953 struct node_mem_mask *p = &node_masks[new_nid];
955 if ((start & p->mask) == p->match) {
956 if (prev_nid == NUMA_NO_NODE)
962 if (new_nid == num_node_masks) {
964 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.",
969 if (prev_nid != new_nid)
974 return start > end ? end : start;
977 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
979 u64 ret_end, pa_start, m_mask, m_match, m_end;
980 struct mdesc_mblock *mblock;
983 if (tlb_type != hypervisor)
984 return memblock_nid_range_sun4u(start, end, nid);
986 mblock = addr_to_mblock(start);
988 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]",
996 pa_start = start + mblock->offset;
1000 for (_nid = 0; _nid < num_node_masks; _nid++) {
1001 struct node_mem_mask *const m = &node_masks[_nid];
1003 if ((pa_start & m->mask) == m->match) {
1010 if (num_node_masks == _nid) {
1011 /* We could not find NUMA group, so default to 0, but lets
1012 * search for latency group, so we could calculate the correct
1013 * end address that we return
1017 for (i = 0; i < num_mlgroups; i++) {
1018 struct mdesc_mlgroup *const m = &mlgroups[i];
1020 if ((pa_start & m->mask) == m->match) {
1027 if (i == num_mlgroups) {
1028 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]",
1037 * Each latency group has match and mask, and each memory block has an
1038 * offset. An address belongs to a latency group if its address matches
1039 * the following formula: ((addr + offset) & mask) == match
1040 * It is, however, slow to check every single page if it matches a
1041 * particular latency group. As optimization we calculate end value by
1042 * using bit arithmetics.
1044 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset;
1045 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
1046 ret_end = m_end > end ? end : m_end;
1054 /* This must be invoked after performing all of the necessary
1055 * memblock_set_node() calls for 'nid'. We need to be able to get
1056 * correct data from get_pfn_range_for_nid().
1058 static void __init allocate_node_data(int nid)
1060 struct pglist_data *p;
1061 unsigned long start_pfn, end_pfn;
1062 #ifdef CONFIG_NEED_MULTIPLE_NODES
1064 NODE_DATA(nid) = memblock_alloc_node(sizeof(struct pglist_data),
1065 SMP_CACHE_BYTES, nid);
1066 if (!NODE_DATA(nid)) {
1067 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
1071 NODE_DATA(nid)->node_id = nid;
1076 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
1077 p->node_start_pfn = start_pfn;
1078 p->node_spanned_pages = end_pfn - start_pfn;
1081 static void init_node_masks_nonnuma(void)
1083 #ifdef CONFIG_NEED_MULTIPLE_NODES
1087 numadbg("Initializing tables for non-numa.\n");
1089 node_masks[0].mask = 0;
1090 node_masks[0].match = 0;
1093 #ifdef CONFIG_NEED_MULTIPLE_NODES
1094 for (i = 0; i < NR_CPUS; i++)
1095 numa_cpu_lookup_table[i] = 0;
1097 cpumask_setall(&numa_cpumask_lookup_table[0]);
1101 #ifdef CONFIG_NEED_MULTIPLE_NODES
1102 struct pglist_data *node_data[MAX_NUMNODES];
1104 EXPORT_SYMBOL(numa_cpu_lookup_table);
1105 EXPORT_SYMBOL(numa_cpumask_lookup_table);
1106 EXPORT_SYMBOL(node_data);
1108 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
1113 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
1114 u64 target = mdesc_arc_target(md, arc);
1117 val = mdesc_get_property(md, target,
1118 "cfg-handle", NULL);
1119 if (val && *val == cfg_handle)
1125 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
1128 u64 arc, candidate, best_latency = ~(u64)0;
1130 candidate = MDESC_NODE_NULL;
1131 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1132 u64 target = mdesc_arc_target(md, arc);
1133 const char *name = mdesc_node_name(md, target);
1136 if (strcmp(name, "pio-latency-group"))
1139 val = mdesc_get_property(md, target, "latency", NULL);
1143 if (*val < best_latency) {
1145 best_latency = *val;
1149 if (candidate == MDESC_NODE_NULL)
1152 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
1155 int of_node_to_nid(struct device_node *dp)
1157 const struct linux_prom64_registers *regs;
1158 struct mdesc_handle *md;
1163 /* This is the right thing to do on currently supported
1164 * SUN4U NUMA platforms as well, as the PCI controller does
1165 * not sit behind any particular memory controller.
1170 regs = of_get_property(dp, "reg", NULL);
1174 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1180 mdesc_for_each_node_by_name(md, grp, "group") {
1181 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1193 static void __init add_node_ranges(void)
1195 struct memblock_region *reg;
1196 unsigned long prev_max;
1199 prev_max = memblock.memory.max;
1201 for_each_memblock(memory, reg) {
1202 unsigned long size = reg->size;
1203 unsigned long start, end;
1207 while (start < end) {
1208 unsigned long this_end;
1211 this_end = memblock_nid_range(start, end, &nid);
1213 numadbg("Setting memblock NUMA node nid[%d] "
1214 "start[%lx] end[%lx]\n",
1215 nid, start, this_end);
1217 memblock_set_node(start, this_end - start,
1218 &memblock.memory, nid);
1219 if (memblock.memory.max != prev_max)
1220 goto memblock_resized;
1226 static int __init grab_mlgroups(struct mdesc_handle *md)
1228 unsigned long paddr;
1232 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1237 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup),
1242 mlgroups = __va(paddr);
1243 num_mlgroups = count;
1246 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1247 struct mdesc_mlgroup *m = &mlgroups[count++];
1252 val = mdesc_get_property(md, node, "latency", NULL);
1254 val = mdesc_get_property(md, node, "address-match", NULL);
1256 val = mdesc_get_property(md, node, "address-mask", NULL);
1259 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1260 "match[%llx] mask[%llx]\n",
1261 count - 1, m->node, m->latency, m->match, m->mask);
1267 static int __init grab_mblocks(struct mdesc_handle *md)
1269 unsigned long paddr;
1273 mdesc_for_each_node_by_name(md, node, "mblock")
1278 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock),
1283 mblocks = __va(paddr);
1284 num_mblocks = count;
1287 mdesc_for_each_node_by_name(md, node, "mblock") {
1288 struct mdesc_mblock *m = &mblocks[count++];
1291 val = mdesc_get_property(md, node, "base", NULL);
1293 val = mdesc_get_property(md, node, "size", NULL);
1295 val = mdesc_get_property(md, node,
1296 "address-congruence-offset", NULL);
1298 /* The address-congruence-offset property is optional.
1299 * Explicity zero it be identifty this.
1306 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1307 count - 1, m->base, m->size, m->offset);
1313 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1314 u64 grp, cpumask_t *mask)
1318 cpumask_clear(mask);
1320 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1321 u64 target = mdesc_arc_target(md, arc);
1322 const char *name = mdesc_node_name(md, target);
1325 if (strcmp(name, "cpu"))
1327 id = mdesc_get_property(md, target, "id", NULL);
1328 if (*id < nr_cpu_ids)
1329 cpumask_set_cpu(*id, mask);
1333 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1337 for (i = 0; i < num_mlgroups; i++) {
1338 struct mdesc_mlgroup *m = &mlgroups[i];
1339 if (m->node == node)
1345 int __node_distance(int from, int to)
1347 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1348 pr_warn("Returning default NUMA distance value for %d->%d\n",
1350 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1352 return numa_latency[from][to];
1354 EXPORT_SYMBOL(__node_distance);
1356 static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1360 for (i = 0; i < MAX_NUMNODES; i++) {
1361 struct node_mem_mask *n = &node_masks[i];
1363 if ((grp->mask == n->mask) && (grp->match == n->match))
1369 static void __init find_numa_latencies_for_group(struct mdesc_handle *md,
1374 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1376 u64 target = mdesc_arc_target(md, arc);
1377 struct mdesc_mlgroup *m = find_mlgroup(target);
1381 tnode = find_best_numa_node_for_mlgroup(m);
1382 if (tnode == MAX_NUMNODES)
1384 numa_latency[index][tnode] = m->latency;
1388 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1391 struct mdesc_mlgroup *candidate = NULL;
1392 u64 arc, best_latency = ~(u64)0;
1393 struct node_mem_mask *n;
1395 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1396 u64 target = mdesc_arc_target(md, arc);
1397 struct mdesc_mlgroup *m = find_mlgroup(target);
1400 if (m->latency < best_latency) {
1402 best_latency = m->latency;
1408 if (num_node_masks != index) {
1409 printk(KERN_ERR "Inconsistent NUMA state, "
1410 "index[%d] != num_node_masks[%d]\n",
1411 index, num_node_masks);
1415 n = &node_masks[num_node_masks++];
1417 n->mask = candidate->mask;
1418 n->match = candidate->match;
1420 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n",
1421 index, n->mask, n->match, candidate->latency);
1426 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1432 numa_parse_mdesc_group_cpus(md, grp, &mask);
1434 for_each_cpu(cpu, &mask)
1435 numa_cpu_lookup_table[cpu] = index;
1436 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1439 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1440 for_each_cpu(cpu, &mask)
1445 return numa_attach_mlgroup(md, grp, index);
1448 static int __init numa_parse_mdesc(void)
1450 struct mdesc_handle *md = mdesc_grab();
1451 int i, j, err, count;
1454 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1455 if (node == MDESC_NODE_NULL) {
1460 err = grab_mblocks(md);
1464 err = grab_mlgroups(md);
1469 mdesc_for_each_node_by_name(md, node, "group") {
1470 err = numa_parse_mdesc_group(md, node, count);
1477 mdesc_for_each_node_by_name(md, node, "group") {
1478 find_numa_latencies_for_group(md, node, count);
1482 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1483 for (i = 0; i < MAX_NUMNODES; i++) {
1484 u64 self_latency = numa_latency[i][i];
1486 for (j = 0; j < MAX_NUMNODES; j++) {
1487 numa_latency[i][j] =
1488 (numa_latency[i][j] * LOCAL_DISTANCE) /
1495 for (i = 0; i < num_node_masks; i++) {
1496 allocate_node_data(i);
1506 static int __init numa_parse_jbus(void)
1508 unsigned long cpu, index;
1510 /* NUMA node id is encoded in bits 36 and higher, and there is
1511 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1514 for_each_present_cpu(cpu) {
1515 numa_cpu_lookup_table[cpu] = index;
1516 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1517 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1518 node_masks[index].match = cpu << 36UL;
1522 num_node_masks = index;
1526 for (index = 0; index < num_node_masks; index++) {
1527 allocate_node_data(index);
1528 node_set_online(index);
1534 static int __init numa_parse_sun4u(void)
1536 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1539 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1540 if ((ver >> 32UL) == __JALAPENO_ID ||
1541 (ver >> 32UL) == __SERRANO_ID)
1542 return numa_parse_jbus();
1547 static int __init bootmem_init_numa(void)
1552 numadbg("bootmem_init_numa()\n");
1554 /* Some sane defaults for numa latency values */
1555 for (i = 0; i < MAX_NUMNODES; i++) {
1556 for (j = 0; j < MAX_NUMNODES; j++)
1557 numa_latency[i][j] = (i == j) ?
1558 LOCAL_DISTANCE : REMOTE_DISTANCE;
1562 if (tlb_type == hypervisor)
1563 err = numa_parse_mdesc();
1565 err = numa_parse_sun4u();
1572 static int bootmem_init_numa(void)
1579 static void __init bootmem_init_nonnuma(void)
1581 unsigned long top_of_ram = memblock_end_of_DRAM();
1582 unsigned long total_ram = memblock_phys_mem_size();
1584 numadbg("bootmem_init_nonnuma()\n");
1586 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1587 top_of_ram, total_ram);
1588 printk(KERN_INFO "Memory hole size: %ldMB\n",
1589 (top_of_ram - total_ram) >> 20);
1591 init_node_masks_nonnuma();
1592 memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0);
1593 allocate_node_data(0);
1597 static unsigned long __init bootmem_init(unsigned long phys_base)
1599 unsigned long end_pfn;
1601 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1602 max_pfn = max_low_pfn = end_pfn;
1603 min_low_pfn = (phys_base >> PAGE_SHIFT);
1605 if (bootmem_init_numa() < 0)
1606 bootmem_init_nonnuma();
1608 /* Dump memblock with node info. */
1609 memblock_dump_all();
1611 /* XXX cpu notifier XXX */
1618 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1619 static int pall_ents __initdata;
1621 static unsigned long max_phys_bits = 40;
1623 bool kern_addr_valid(unsigned long addr)
1631 if ((long)addr < 0L) {
1632 unsigned long pa = __pa(addr);
1634 if ((pa >> max_phys_bits) != 0UL)
1637 return pfn_valid(pa >> PAGE_SHIFT);
1640 if (addr >= (unsigned long) KERNBASE &&
1641 addr < (unsigned long)&_end)
1644 pgd = pgd_offset_k(addr);
1648 p4d = p4d_offset(pgd, addr);
1652 pud = pud_offset(p4d, addr);
1656 if (pud_large(*pud))
1657 return pfn_valid(pud_pfn(*pud));
1659 pmd = pmd_offset(pud, addr);
1663 if (pmd_large(*pmd))
1664 return pfn_valid(pmd_pfn(*pmd));
1666 pte = pte_offset_kernel(pmd, addr);
1670 return pfn_valid(pte_pfn(*pte));
1672 EXPORT_SYMBOL(kern_addr_valid);
1674 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1678 const unsigned long mask16gb = (1UL << 34) - 1UL;
1679 u64 pte_val = vstart;
1681 /* Each PUD is 8GB */
1682 if ((vstart & mask16gb) ||
1683 (vend - vstart <= mask16gb)) {
1684 pte_val ^= kern_linear_pte_xor[2];
1685 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1687 return vstart + PUD_SIZE;
1690 pte_val ^= kern_linear_pte_xor[3];
1691 pte_val |= _PAGE_PUD_HUGE;
1693 vend = vstart + mask16gb + 1UL;
1694 while (vstart < vend) {
1695 pud_val(*pud) = pte_val;
1697 pte_val += PUD_SIZE;
1704 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1707 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1713 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1717 const unsigned long mask256mb = (1UL << 28) - 1UL;
1718 const unsigned long mask2gb = (1UL << 31) - 1UL;
1719 u64 pte_val = vstart;
1721 /* Each PMD is 8MB */
1722 if ((vstart & mask256mb) ||
1723 (vend - vstart <= mask256mb)) {
1724 pte_val ^= kern_linear_pte_xor[0];
1725 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1727 return vstart + PMD_SIZE;
1730 if ((vstart & mask2gb) ||
1731 (vend - vstart <= mask2gb)) {
1732 pte_val ^= kern_linear_pte_xor[1];
1733 pte_val |= _PAGE_PMD_HUGE;
1734 vend = vstart + mask256mb + 1UL;
1736 pte_val ^= kern_linear_pte_xor[2];
1737 pte_val |= _PAGE_PMD_HUGE;
1738 vend = vstart + mask2gb + 1UL;
1741 while (vstart < vend) {
1742 pmd_val(*pmd) = pte_val;
1744 pte_val += PMD_SIZE;
1752 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1755 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1761 static unsigned long __ref kernel_map_range(unsigned long pstart,
1762 unsigned long pend, pgprot_t prot,
1765 unsigned long vstart = PAGE_OFFSET + pstart;
1766 unsigned long vend = PAGE_OFFSET + pend;
1767 unsigned long alloc_bytes = 0UL;
1769 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1770 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1775 while (vstart < vend) {
1776 unsigned long this_end, paddr = __pa(vstart);
1777 pgd_t *pgd = pgd_offset_k(vstart);
1783 if (pgd_none(*pgd)) {
1786 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1790 alloc_bytes += PAGE_SIZE;
1791 pgd_populate(&init_mm, pgd, new);
1794 p4d = p4d_offset(pgd, vstart);
1795 if (p4d_none(*p4d)) {
1798 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1802 alloc_bytes += PAGE_SIZE;
1803 p4d_populate(&init_mm, p4d, new);
1806 pud = pud_offset(p4d, vstart);
1807 if (pud_none(*pud)) {
1810 if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1811 vstart = kernel_map_hugepud(vstart, vend, pud);
1814 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1818 alloc_bytes += PAGE_SIZE;
1819 pud_populate(&init_mm, pud, new);
1822 pmd = pmd_offset(pud, vstart);
1823 if (pmd_none(*pmd)) {
1826 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1827 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1830 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1834 alloc_bytes += PAGE_SIZE;
1835 pmd_populate_kernel(&init_mm, pmd, new);
1838 pte = pte_offset_kernel(pmd, vstart);
1839 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1840 if (this_end > vend)
1843 while (vstart < this_end) {
1844 pte_val(*pte) = (paddr | pgprot_val(prot));
1846 vstart += PAGE_SIZE;
1855 panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n",
1856 __func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1860 static void __init flush_all_kernel_tsbs(void)
1864 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1865 struct tsb *ent = &swapper_tsb[i];
1867 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1869 #ifndef CONFIG_DEBUG_PAGEALLOC
1870 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1871 struct tsb *ent = &swapper_4m_tsb[i];
1873 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1878 extern unsigned int kvmap_linear_patch[1];
1880 static void __init kernel_physical_mapping_init(void)
1882 unsigned long i, mem_alloced = 0UL;
1883 bool use_huge = true;
1885 #ifdef CONFIG_DEBUG_PAGEALLOC
1888 for (i = 0; i < pall_ents; i++) {
1889 unsigned long phys_start, phys_end;
1891 phys_start = pall[i].phys_addr;
1892 phys_end = phys_start + pall[i].reg_size;
1894 mem_alloced += kernel_map_range(phys_start, phys_end,
1895 PAGE_KERNEL, use_huge);
1898 printk("Allocated %ld bytes for kernel page tables.\n",
1901 kvmap_linear_patch[0] = 0x01000000; /* nop */
1902 flushi(&kvmap_linear_patch[0]);
1904 flush_all_kernel_tsbs();
1909 #ifdef CONFIG_DEBUG_PAGEALLOC
1910 void __kernel_map_pages(struct page *page, int numpages, int enable)
1912 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1913 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1915 kernel_map_range(phys_start, phys_end,
1916 (enable ? PAGE_KERNEL : __pgprot(0)), false);
1918 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1919 PAGE_OFFSET + phys_end);
1921 /* we should perform an IPI and flush all tlbs,
1922 * but that can deadlock->flush only current cpu.
1924 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1925 PAGE_OFFSET + phys_end);
1929 unsigned long __init find_ecache_flush_span(unsigned long size)
1933 for (i = 0; i < pavail_ents; i++) {
1934 if (pavail[i].reg_size >= size)
1935 return pavail[i].phys_addr;
1941 unsigned long PAGE_OFFSET;
1942 EXPORT_SYMBOL(PAGE_OFFSET);
1944 unsigned long VMALLOC_END = 0x0000010000000000UL;
1945 EXPORT_SYMBOL(VMALLOC_END);
1947 unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
1948 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1950 static void __init setup_page_offset(void)
1952 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1953 /* Cheetah/Panther support a full 64-bit virtual
1954 * address, so we can use all that our page tables
1957 sparc64_va_hole_top = 0xfff0000000000000UL;
1958 sparc64_va_hole_bottom = 0x0010000000000000UL;
1961 } else if (tlb_type == hypervisor) {
1962 switch (sun4v_chip_type) {
1963 case SUN4V_CHIP_NIAGARA1:
1964 case SUN4V_CHIP_NIAGARA2:
1965 /* T1 and T2 support 48-bit virtual addresses. */
1966 sparc64_va_hole_top = 0xffff800000000000UL;
1967 sparc64_va_hole_bottom = 0x0000800000000000UL;
1971 case SUN4V_CHIP_NIAGARA3:
1972 /* T3 supports 48-bit virtual addresses. */
1973 sparc64_va_hole_top = 0xffff800000000000UL;
1974 sparc64_va_hole_bottom = 0x0000800000000000UL;
1978 case SUN4V_CHIP_NIAGARA4:
1979 case SUN4V_CHIP_NIAGARA5:
1980 case SUN4V_CHIP_SPARC64X:
1981 case SUN4V_CHIP_SPARC_M6:
1982 /* T4 and later support 52-bit virtual addresses. */
1983 sparc64_va_hole_top = 0xfff8000000000000UL;
1984 sparc64_va_hole_bottom = 0x0008000000000000UL;
1987 case SUN4V_CHIP_SPARC_M7:
1988 case SUN4V_CHIP_SPARC_SN:
1989 /* M7 and later support 52-bit virtual addresses. */
1990 sparc64_va_hole_top = 0xfff8000000000000UL;
1991 sparc64_va_hole_bottom = 0x0008000000000000UL;
1994 case SUN4V_CHIP_SPARC_M8:
1996 /* M8 and later support 54-bit virtual addresses.
1997 * However, restricting M8 and above VA bits to 53
1998 * as 4-level page table cannot support more than
2001 sparc64_va_hole_top = 0xfff0000000000000UL;
2002 sparc64_va_hole_bottom = 0x0010000000000000UL;
2008 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
2009 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
2014 PAGE_OFFSET = sparc64_va_hole_top;
2015 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
2016 (sparc64_va_hole_bottom >> 2));
2018 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
2019 PAGE_OFFSET, max_phys_bits);
2020 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
2021 VMALLOC_START, VMALLOC_END);
2022 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
2023 VMEMMAP_BASE, VMEMMAP_BASE << 1);
2026 static void __init tsb_phys_patch(void)
2028 struct tsb_ldquad_phys_patch_entry *pquad;
2029 struct tsb_phys_patch_entry *p;
2031 pquad = &__tsb_ldquad_phys_patch;
2032 while (pquad < &__tsb_ldquad_phys_patch_end) {
2033 unsigned long addr = pquad->addr;
2035 if (tlb_type == hypervisor)
2036 *(unsigned int *) addr = pquad->sun4v_insn;
2038 *(unsigned int *) addr = pquad->sun4u_insn;
2040 __asm__ __volatile__("flush %0"
2047 p = &__tsb_phys_patch;
2048 while (p < &__tsb_phys_patch_end) {
2049 unsigned long addr = p->addr;
2051 *(unsigned int *) addr = p->insn;
2053 __asm__ __volatile__("flush %0"
2061 /* Don't mark as init, we give this to the Hypervisor. */
2062 #ifndef CONFIG_DEBUG_PAGEALLOC
2063 #define NUM_KTSB_DESCR 2
2065 #define NUM_KTSB_DESCR 1
2067 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
2069 /* The swapper TSBs are loaded with a base sequence of:
2071 * sethi %uhi(SYMBOL), REG1
2072 * sethi %hi(SYMBOL), REG2
2073 * or REG1, %ulo(SYMBOL), REG1
2074 * or REG2, %lo(SYMBOL), REG2
2075 * sllx REG1, 32, REG1
2076 * or REG1, REG2, REG1
2078 * When we use physical addressing for the TSB accesses, we patch the
2079 * first four instructions in the above sequence.
2082 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
2084 unsigned long high_bits, low_bits;
2086 high_bits = (pa >> 32) & 0xffffffff;
2087 low_bits = (pa >> 0) & 0xffffffff;
2089 while (start < end) {
2090 unsigned int *ia = (unsigned int *)(unsigned long)*start;
2092 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
2093 __asm__ __volatile__("flush %0" : : "r" (ia));
2095 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
2096 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
2098 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
2099 __asm__ __volatile__("flush %0" : : "r" (ia + 2));
2101 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
2102 __asm__ __volatile__("flush %0" : : "r" (ia + 3));
2108 static void ktsb_phys_patch(void)
2110 extern unsigned int __swapper_tsb_phys_patch;
2111 extern unsigned int __swapper_tsb_phys_patch_end;
2112 unsigned long ktsb_pa;
2114 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2115 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
2116 &__swapper_tsb_phys_patch_end, ktsb_pa);
2117 #ifndef CONFIG_DEBUG_PAGEALLOC
2119 extern unsigned int __swapper_4m_tsb_phys_patch;
2120 extern unsigned int __swapper_4m_tsb_phys_patch_end;
2121 ktsb_pa = (kern_base +
2122 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2123 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
2124 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
2129 static void __init sun4v_ktsb_init(void)
2131 unsigned long ktsb_pa;
2133 /* First KTSB for PAGE_SIZE mappings. */
2134 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2136 switch (PAGE_SIZE) {
2139 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
2140 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
2144 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
2145 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
2149 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
2150 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
2153 case 4 * 1024 * 1024:
2154 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
2155 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
2159 ktsb_descr[0].assoc = 1;
2160 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
2161 ktsb_descr[0].ctx_idx = 0;
2162 ktsb_descr[0].tsb_base = ktsb_pa;
2163 ktsb_descr[0].resv = 0;
2165 #ifndef CONFIG_DEBUG_PAGEALLOC
2166 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
2167 ktsb_pa = (kern_base +
2168 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2170 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
2171 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
2172 HV_PGSZ_MASK_256MB |
2174 HV_PGSZ_MASK_16GB) &
2176 ktsb_descr[1].assoc = 1;
2177 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
2178 ktsb_descr[1].ctx_idx = 0;
2179 ktsb_descr[1].tsb_base = ktsb_pa;
2180 ktsb_descr[1].resv = 0;
2184 void sun4v_ktsb_register(void)
2186 unsigned long pa, ret;
2188 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
2190 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
2192 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
2193 "errors with %lx\n", pa, ret);
2198 static void __init sun4u_linear_pte_xor_finalize(void)
2200 #ifndef CONFIG_DEBUG_PAGEALLOC
2201 /* This is where we would add Panther support for
2202 * 32MB and 256MB pages.
2207 static void __init sun4v_linear_pte_xor_finalize(void)
2209 unsigned long pagecv_flag;
2211 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
2212 * enables MCD error. Do not set bit 9 on M7 processor.
2214 switch (sun4v_chip_type) {
2215 case SUN4V_CHIP_SPARC_M7:
2216 case SUN4V_CHIP_SPARC_M8:
2217 case SUN4V_CHIP_SPARC_SN:
2221 pagecv_flag = _PAGE_CV_4V;
2224 #ifndef CONFIG_DEBUG_PAGEALLOC
2225 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
2226 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2228 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
2229 _PAGE_P_4V | _PAGE_W_4V);
2231 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2234 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2235 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2237 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2238 _PAGE_P_4V | _PAGE_W_4V);
2240 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2243 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2244 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2246 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2247 _PAGE_P_4V | _PAGE_W_4V);
2249 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2254 /* paging_init() sets up the page tables */
2256 static unsigned long last_valid_pfn;
2258 static void sun4u_pgprot_init(void);
2259 static void sun4v_pgprot_init(void);
2261 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2262 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2263 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2264 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2265 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2266 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2268 /* We need to exclude reserved regions. This exclusion will include
2269 * vmlinux and initrd. To be more precise the initrd size could be used to
2270 * compute a new lower limit because it is freed later during initialization.
2272 static void __init reduce_memory(phys_addr_t limit_ram)
2274 limit_ram += memblock_reserved_size();
2275 memblock_enforce_memory_limit(limit_ram);
2278 void __init paging_init(void)
2280 unsigned long end_pfn, shift, phys_base;
2281 unsigned long real_end, i;
2283 setup_page_offset();
2285 /* These build time checkes make sure that the dcache_dirty_cpu()
2286 * page->flags usage will work.
2288 * When a page gets marked as dcache-dirty, we store the
2289 * cpu number starting at bit 32 in the page->flags. Also,
2290 * functions like clear_dcache_dirty_cpu use the cpu mask
2291 * in 13-bit signed-immediate instruction fields.
2295 * Page flags must not reach into upper 32 bits that are used
2296 * for the cpu number
2298 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2301 * The bit fields placed in the high range must not reach below
2302 * the 32 bit boundary. Otherwise we cannot place the cpu field
2303 * at the 32 bit boundary.
2305 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2306 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2308 BUILD_BUG_ON(NR_CPUS > 4096);
2310 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2311 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2313 /* Invalidate both kernel TSBs. */
2314 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2315 #ifndef CONFIG_DEBUG_PAGEALLOC
2316 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2319 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2320 * bit on M7 processor. This is a conflicting usage of the same
2321 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2322 * Detection error on all pages and this will lead to problems
2323 * later. Kernel does not run with MCD enabled and hence rest
2324 * of the required steps to fully configure memory corruption
2325 * detection are not taken. We need to ensure TTE.mcde is not
2326 * set on M7 processor. Compute the value of cacheability
2327 * flag for use later taking this into consideration.
2329 switch (sun4v_chip_type) {
2330 case SUN4V_CHIP_SPARC_M7:
2331 case SUN4V_CHIP_SPARC_M8:
2332 case SUN4V_CHIP_SPARC_SN:
2333 page_cache4v_flag = _PAGE_CP_4V;
2336 page_cache4v_flag = _PAGE_CACHE_4V;
2340 if (tlb_type == hypervisor)
2341 sun4v_pgprot_init();
2343 sun4u_pgprot_init();
2345 if (tlb_type == cheetah_plus ||
2346 tlb_type == hypervisor) {
2351 if (tlb_type == hypervisor)
2352 sun4v_patch_tlb_handlers();
2354 /* Find available physical memory...
2356 * Read it twice in order to work around a bug in openfirmware.
2357 * The call to grab this table itself can cause openfirmware to
2358 * allocate memory, which in turn can take away some space from
2359 * the list of available memory. Reading it twice makes sure
2360 * we really do get the final value.
2362 read_obp_translations();
2363 read_obp_memory("reg", &pall[0], &pall_ents);
2364 read_obp_memory("available", &pavail[0], &pavail_ents);
2365 read_obp_memory("available", &pavail[0], &pavail_ents);
2367 phys_base = 0xffffffffffffffffUL;
2368 for (i = 0; i < pavail_ents; i++) {
2369 phys_base = min(phys_base, pavail[i].phys_addr);
2370 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2373 memblock_reserve(kern_base, kern_size);
2375 find_ramdisk(phys_base);
2377 if (cmdline_memory_size)
2378 reduce_memory(cmdline_memory_size);
2380 memblock_allow_resize();
2381 memblock_dump_all();
2383 set_bit(0, mmu_context_bmap);
2385 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2387 real_end = (unsigned long)_end;
2388 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2389 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2390 num_kernel_image_mappings);
2392 /* Set kernel pgd to upper alias so physical page computations
2395 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2397 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2399 inherit_prom_mappings();
2401 /* Ok, we can use our TLB miss and window trap handlers safely. */
2406 prom_build_devicetree();
2407 of_populate_present_mask();
2409 of_fill_in_cpu_data();
2412 if (tlb_type == hypervisor) {
2414 mdesc_populate_present_mask(cpu_all_mask);
2416 mdesc_fill_in_cpu_data(cpu_all_mask);
2418 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2420 sun4v_linear_pte_xor_finalize();
2423 sun4v_ktsb_register();
2425 unsigned long impl, ver;
2427 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2428 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2430 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2431 impl = ((ver >> 32) & 0xffff);
2432 if (impl == PANTHER_IMPL)
2433 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2434 HV_PGSZ_MASK_256MB);
2436 sun4u_linear_pte_xor_finalize();
2439 /* Flush the TLBs and the 4M TSB so that the updated linear
2440 * pte XOR settings are realized for all mappings.
2443 #ifndef CONFIG_DEBUG_PAGEALLOC
2444 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2448 /* Setup bootmem... */
2449 last_valid_pfn = end_pfn = bootmem_init(phys_base);
2451 kernel_physical_mapping_init();
2454 unsigned long max_zone_pfns[MAX_NR_ZONES];
2456 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2458 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2460 free_area_init(max_zone_pfns);
2463 printk("Booting Linux...\n");
2466 int page_in_phys_avail(unsigned long paddr)
2472 for (i = 0; i < pavail_ents; i++) {
2473 unsigned long start, end;
2475 start = pavail[i].phys_addr;
2476 end = start + pavail[i].reg_size;
2478 if (paddr >= start && paddr < end)
2481 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2483 #ifdef CONFIG_BLK_DEV_INITRD
2484 if (paddr >= __pa(initrd_start) &&
2485 paddr < __pa(PAGE_ALIGN(initrd_end)))
2492 static void __init register_page_bootmem_info(void)
2494 #ifdef CONFIG_NEED_MULTIPLE_NODES
2497 for_each_online_node(i)
2498 if (NODE_DATA(i)->node_spanned_pages)
2499 register_page_bootmem_info_node(NODE_DATA(i));
2502 void __init mem_init(void)
2504 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2506 memblock_free_all();
2509 * Must be done after boot memory is put on freelist, because here we
2510 * might set fields in deferred struct pages that have not yet been
2511 * initialized, and memblock_free_all() initializes all the reserved
2512 * deferred pages for us.
2514 register_page_bootmem_info();
2517 * Set up the zero page, mark it reserved, so that page count
2518 * is not manipulated when freeing the page from user ptes.
2520 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2521 if (mem_map_zero == NULL) {
2522 prom_printf("paging_init: Cannot alloc zero page.\n");
2525 mark_page_reserved(mem_map_zero);
2527 mem_init_print_info(NULL);
2529 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2530 cheetah_ecache_flush_init();
2533 void free_initmem(void)
2535 unsigned long addr, initend;
2538 /* If the physical memory maps were trimmed by kernel command
2539 * line options, don't even try freeing this initmem stuff up.
2540 * The kernel image could have been in the trimmed out region
2541 * and if so the freeing below will free invalid page structs.
2543 if (cmdline_memory_size)
2547 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2549 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2550 initend = (unsigned long)(__init_end) & PAGE_MASK;
2551 for (; addr < initend; addr += PAGE_SIZE) {
2555 ((unsigned long) __va(kern_base)) -
2556 ((unsigned long) KERNBASE));
2557 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2560 free_reserved_page(virt_to_page(page));
2564 pgprot_t PAGE_KERNEL __read_mostly;
2565 EXPORT_SYMBOL(PAGE_KERNEL);
2567 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2568 pgprot_t PAGE_COPY __read_mostly;
2570 pgprot_t PAGE_SHARED __read_mostly;
2571 EXPORT_SYMBOL(PAGE_SHARED);
2573 unsigned long pg_iobits __read_mostly;
2575 unsigned long _PAGE_IE __read_mostly;
2576 EXPORT_SYMBOL(_PAGE_IE);
2578 unsigned long _PAGE_E __read_mostly;
2579 EXPORT_SYMBOL(_PAGE_E);
2581 unsigned long _PAGE_CACHE __read_mostly;
2582 EXPORT_SYMBOL(_PAGE_CACHE);
2584 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2585 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2586 int node, struct vmem_altmap *altmap)
2588 unsigned long pte_base;
2590 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2591 _PAGE_CP_4U | _PAGE_CV_4U |
2592 _PAGE_P_4U | _PAGE_W_4U);
2593 if (tlb_type == hypervisor)
2594 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2595 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2597 pte_base |= _PAGE_PMD_HUGE;
2599 vstart = vstart & PMD_MASK;
2600 vend = ALIGN(vend, PMD_SIZE);
2601 for (; vstart < vend; vstart += PMD_SIZE) {
2602 pgd_t *pgd = vmemmap_pgd_populate(vstart, node);
2611 p4d = vmemmap_p4d_populate(pgd, vstart, node);
2615 pud = vmemmap_pud_populate(p4d, vstart, node);
2619 pmd = pmd_offset(pud, vstart);
2620 pte = pmd_val(*pmd);
2621 if (!(pte & _PAGE_VALID)) {
2622 void *block = vmemmap_alloc_block(PMD_SIZE, node);
2627 pmd_val(*pmd) = pte_base | __pa(block);
2634 void vmemmap_free(unsigned long start, unsigned long end,
2635 struct vmem_altmap *altmap)
2638 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2640 static void prot_init_common(unsigned long page_none,
2641 unsigned long page_shared,
2642 unsigned long page_copy,
2643 unsigned long page_readonly,
2644 unsigned long page_exec_bit)
2646 PAGE_COPY = __pgprot(page_copy);
2647 PAGE_SHARED = __pgprot(page_shared);
2649 protection_map[0x0] = __pgprot(page_none);
2650 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2651 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2652 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2653 protection_map[0x4] = __pgprot(page_readonly);
2654 protection_map[0x5] = __pgprot(page_readonly);
2655 protection_map[0x6] = __pgprot(page_copy);
2656 protection_map[0x7] = __pgprot(page_copy);
2657 protection_map[0x8] = __pgprot(page_none);
2658 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2659 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2660 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2661 protection_map[0xc] = __pgprot(page_readonly);
2662 protection_map[0xd] = __pgprot(page_readonly);
2663 protection_map[0xe] = __pgprot(page_shared);
2664 protection_map[0xf] = __pgprot(page_shared);
2667 static void __init sun4u_pgprot_init(void)
2669 unsigned long page_none, page_shared, page_copy, page_readonly;
2670 unsigned long page_exec_bit;
2673 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2674 _PAGE_CACHE_4U | _PAGE_P_4U |
2675 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2677 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2678 _PAGE_CACHE_4U | _PAGE_P_4U |
2679 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2680 _PAGE_EXEC_4U | _PAGE_L_4U);
2682 _PAGE_IE = _PAGE_IE_4U;
2683 _PAGE_E = _PAGE_E_4U;
2684 _PAGE_CACHE = _PAGE_CACHE_4U;
2686 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2687 __ACCESS_BITS_4U | _PAGE_E_4U);
2689 #ifdef CONFIG_DEBUG_PAGEALLOC
2690 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2692 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2695 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2696 _PAGE_P_4U | _PAGE_W_4U);
2698 for (i = 1; i < 4; i++)
2699 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2701 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2702 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2703 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2706 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2707 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2708 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2709 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2710 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2711 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2712 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2714 page_exec_bit = _PAGE_EXEC_4U;
2716 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2720 static void __init sun4v_pgprot_init(void)
2722 unsigned long page_none, page_shared, page_copy, page_readonly;
2723 unsigned long page_exec_bit;
2726 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2727 page_cache4v_flag | _PAGE_P_4V |
2728 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2730 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2732 _PAGE_IE = _PAGE_IE_4V;
2733 _PAGE_E = _PAGE_E_4V;
2734 _PAGE_CACHE = page_cache4v_flag;
2736 #ifdef CONFIG_DEBUG_PAGEALLOC
2737 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2739 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2742 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2745 for (i = 1; i < 4; i++)
2746 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2748 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2749 __ACCESS_BITS_4V | _PAGE_E_4V);
2751 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2752 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2753 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2754 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2756 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2757 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2758 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2759 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2760 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2761 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2762 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2764 page_exec_bit = _PAGE_EXEC_4V;
2766 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2770 unsigned long pte_sz_bits(unsigned long sz)
2772 if (tlb_type == hypervisor) {
2776 return _PAGE_SZ8K_4V;
2778 return _PAGE_SZ64K_4V;
2780 return _PAGE_SZ512K_4V;
2781 case 4 * 1024 * 1024:
2782 return _PAGE_SZ4MB_4V;
2788 return _PAGE_SZ8K_4U;
2790 return _PAGE_SZ64K_4U;
2792 return _PAGE_SZ512K_4U;
2793 case 4 * 1024 * 1024:
2794 return _PAGE_SZ4MB_4U;
2799 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2803 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2804 pte_val(pte) |= (((unsigned long)space) << 32);
2805 pte_val(pte) |= pte_sz_bits(page_size);
2810 static unsigned long kern_large_tte(unsigned long paddr)
2814 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2815 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2816 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2817 if (tlb_type == hypervisor)
2818 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2819 page_cache4v_flag | _PAGE_P_4V |
2820 _PAGE_EXEC_4V | _PAGE_W_4V);
2825 /* If not locked, zap it. */
2826 void __flush_tlb_all(void)
2828 unsigned long pstate;
2831 __asm__ __volatile__("flushw\n\t"
2832 "rdpr %%pstate, %0\n\t"
2833 "wrpr %0, %1, %%pstate"
2836 if (tlb_type == hypervisor) {
2837 sun4v_mmu_demap_all();
2838 } else if (tlb_type == spitfire) {
2839 for (i = 0; i < 64; i++) {
2840 /* Spitfire Errata #32 workaround */
2841 /* NOTE: Always runs on spitfire, so no
2842 * cheetah+ page size encodings.
2844 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2848 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2850 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2851 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2854 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2855 spitfire_put_dtlb_data(i, 0x0UL);
2858 /* Spitfire Errata #32 workaround */
2859 /* NOTE: Always runs on spitfire, so no
2860 * cheetah+ page size encodings.
2862 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2866 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2868 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2869 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2872 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2873 spitfire_put_itlb_data(i, 0x0UL);
2876 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2877 cheetah_flush_dtlb_all();
2878 cheetah_flush_itlb_all();
2880 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2884 pte_t *pte_alloc_one_kernel(struct mm_struct *mm)
2886 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2890 pte = (pte_t *) page_address(page);
2895 pgtable_t pte_alloc_one(struct mm_struct *mm)
2897 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2900 if (!pgtable_pte_page_ctor(page)) {
2901 free_unref_page(page);
2904 return (pte_t *) page_address(page);
2907 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2909 free_page((unsigned long)pte);
2912 static void __pte_free(pgtable_t pte)
2914 struct page *page = virt_to_page(pte);
2916 pgtable_pte_page_dtor(page);
2920 void pte_free(struct mm_struct *mm, pgtable_t pte)
2925 void pgtable_free(void *table, bool is_page)
2930 kmem_cache_free(pgtable_cache, table);
2933 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2934 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2937 unsigned long pte, flags;
2938 struct mm_struct *mm;
2941 if (!pmd_large(entry) || !pmd_young(entry))
2944 pte = pmd_val(entry);
2946 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2947 if (!(pte & _PAGE_VALID))
2950 /* We are fabricating 8MB pages using 4MB real hw pages. */
2951 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2955 spin_lock_irqsave(&mm->context.lock, flags);
2957 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2958 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2961 spin_unlock_irqrestore(&mm->context.lock, flags);
2963 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2965 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2966 static void context_reload(void *__data)
2968 struct mm_struct *mm = __data;
2970 if (mm == current->mm)
2971 load_secondary_context(mm);
2974 void hugetlb_setup(struct pt_regs *regs)
2976 struct mm_struct *mm = current->mm;
2977 struct tsb_config *tp;
2979 if (faulthandler_disabled() || !mm) {
2980 const struct exception_table_entry *entry;
2982 entry = search_exception_tables(regs->tpc);
2984 regs->tpc = entry->fixup;
2985 regs->tnpc = regs->tpc + 4;
2988 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2989 die_if_kernel("HugeTSB in atomic", regs);
2992 tp = &mm->context.tsb_block[MM_TSB_HUGE];
2993 if (likely(tp->tsb == NULL))
2994 tsb_grow(mm, MM_TSB_HUGE, 0);
2996 tsb_context_switch(mm);
2999 /* On UltraSPARC-III+ and later, configure the second half of
3000 * the Data-TLB for huge pages.
3002 if (tlb_type == cheetah_plus) {
3003 bool need_context_reload = false;
3006 spin_lock_irq(&ctx_alloc_lock);
3007 ctx = mm->context.sparc64_ctx_val;
3008 ctx &= ~CTX_PGSZ_MASK;
3009 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
3010 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
3012 if (ctx != mm->context.sparc64_ctx_val) {
3013 /* When changing the page size fields, we
3014 * must perform a context flush so that no
3015 * stale entries match. This flush must
3016 * occur with the original context register
3019 do_flush_tlb_mm(mm);
3021 /* Reload the context register of all processors
3022 * also executing in this address space.
3024 mm->context.sparc64_ctx_val = ctx;
3025 need_context_reload = true;
3027 spin_unlock_irq(&ctx_alloc_lock);
3029 if (need_context_reload)
3030 on_each_cpu(context_reload, mm, 0);
3035 static struct resource code_resource = {
3036 .name = "Kernel code",
3037 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3040 static struct resource data_resource = {
3041 .name = "Kernel data",
3042 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3045 static struct resource bss_resource = {
3046 .name = "Kernel bss",
3047 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3050 static inline resource_size_t compute_kern_paddr(void *addr)
3052 return (resource_size_t) (addr - KERNBASE + kern_base);
3055 static void __init kernel_lds_init(void)
3057 code_resource.start = compute_kern_paddr(_text);
3058 code_resource.end = compute_kern_paddr(_etext - 1);
3059 data_resource.start = compute_kern_paddr(_etext);
3060 data_resource.end = compute_kern_paddr(_edata - 1);
3061 bss_resource.start = compute_kern_paddr(__bss_start);
3062 bss_resource.end = compute_kern_paddr(_end - 1);
3065 static int __init report_memory(void)
3068 struct resource *res;
3072 for (i = 0; i < pavail_ents; i++) {
3073 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
3076 pr_warn("Failed to allocate source.\n");
3080 res->name = "System RAM";
3081 res->start = pavail[i].phys_addr;
3082 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
3083 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
3085 if (insert_resource(&iomem_resource, res) < 0) {
3086 pr_warn("Resource insertion failed.\n");
3090 insert_resource(res, &code_resource);
3091 insert_resource(res, &data_resource);
3092 insert_resource(res, &bss_resource);
3097 arch_initcall(report_memory);
3100 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
3102 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range
3105 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
3107 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
3108 if (start < LOW_OBP_ADDRESS) {
3109 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
3110 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
3112 if (end > HI_OBP_ADDRESS) {
3113 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
3114 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
3117 flush_tsb_kernel_range(start, end);
3118 do_flush_tlb_kernel_range(start, end);
3122 void copy_user_highpage(struct page *to, struct page *from,
3123 unsigned long vaddr, struct vm_area_struct *vma)
3127 vfrom = kmap_atomic(from);
3128 vto = kmap_atomic(to);
3129 copy_user_page(vto, vfrom, vaddr, to);
3131 kunmap_atomic(vfrom);
3133 /* If this page has ADI enabled, copy over any ADI tags
3136 if (vma->vm_flags & VM_SPARC_ADI) {
3137 unsigned long pfrom, pto, i, adi_tag;
3139 pfrom = page_to_phys(from);
3140 pto = page_to_phys(to);
3142 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3143 asm volatile("ldxa [%1] %2, %0\n\t"
3145 : "r" (i), "i" (ASI_MCD_REAL));
3146 asm volatile("stxa %0, [%1] %2\n\t"
3148 : "r" (adi_tag), "r" (pto),
3149 "i" (ASI_MCD_REAL));
3150 pto += adi_blksize();
3152 asm volatile("membar #Sync\n\t");
3155 EXPORT_SYMBOL(copy_user_highpage);
3157 void copy_highpage(struct page *to, struct page *from)
3161 vfrom = kmap_atomic(from);
3162 vto = kmap_atomic(to);
3163 copy_page(vto, vfrom);
3165 kunmap_atomic(vfrom);
3167 /* If this platform is ADI enabled, copy any ADI tags
3170 if (adi_capable()) {
3171 unsigned long pfrom, pto, i, adi_tag;
3173 pfrom = page_to_phys(from);
3174 pto = page_to_phys(to);
3176 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3177 asm volatile("ldxa [%1] %2, %0\n\t"
3179 : "r" (i), "i" (ASI_MCD_REAL));
3180 asm volatile("stxa %0, [%1] %2\n\t"
3182 : "r" (adi_tag), "r" (pto),
3183 "i" (ASI_MCD_REAL));
3184 pto += adi_blksize();
3186 asm volatile("membar #Sync\n\t");
3189 EXPORT_SYMBOL(copy_highpage);