1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sparc64/mm/init.c
5 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 #include <linux/extable.h>
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/memblock.h>
16 #include <linux/hugetlb.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/ioport.h>
27 #include <linux/percpu.h>
28 #include <linux/mmzone.h>
29 #include <linux/gfp.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
38 #include <linux/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
42 #include <asm/starfire.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
47 #include <asm/hypervisor.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
51 #include <asm/setup.h>
56 unsigned long kern_linear_pte_xor[4] __read_mostly;
57 static unsigned long page_cache4v_flag;
59 /* A bitmap, two bits for every 256MB of physical memory. These two
60 * bits determine what page size we use for kernel linear
61 * translations. They form an index into kern_linear_pte_xor[]. The
62 * value in the indexed slot is XOR'd with the TLB miss virtual
63 * address to form the resulting TTE. The mapping is:
70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
71 * support 2GB pages, and hopefully future cpus will support the 16GB
72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
73 * if these larger page sizes are not supported by the cpu.
75 * It would be nice to determine this from the machine description
76 * 'cpu' properties, but we need to have this table setup before the
77 * MDESC is initialized.
80 #ifndef CONFIG_DEBUG_PAGEALLOC
81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
82 * Space is allocated for this right after the trap table in
83 * arch/sparc64/kernel/head.S
85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
89 static unsigned long cpu_pgsz_mask;
91 #define MAX_BANKS 1024
93 static struct linux_prom64_registers pavail[MAX_BANKS];
94 static int pavail_ents;
96 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
98 static int cmp_p64(const void *a, const void *b)
100 const struct linux_prom64_registers *x = a, *y = b;
102 if (x->phys_addr > y->phys_addr)
104 if (x->phys_addr < y->phys_addr)
109 static void __init read_obp_memory(const char *property,
110 struct linux_prom64_registers *regs,
113 phandle node = prom_finddevice("/memory");
114 int prop_size = prom_getproplen(node, property);
117 ents = prop_size / sizeof(struct linux_prom64_registers);
118 if (ents > MAX_BANKS) {
119 prom_printf("The machine has more %s property entries than "
120 "this kernel can support (%d).\n",
121 property, MAX_BANKS);
125 ret = prom_getproperty(node, property, (char *) regs, prop_size);
127 prom_printf("Couldn't get %s property from /memory.\n",
132 /* Sanitize what we got from the firmware, by page aligning
135 for (i = 0; i < ents; i++) {
136 unsigned long base, size;
138 base = regs[i].phys_addr;
139 size = regs[i].reg_size;
142 if (base & ~PAGE_MASK) {
143 unsigned long new_base = PAGE_ALIGN(base);
145 size -= new_base - base;
146 if ((long) size < 0L)
151 /* If it is empty, simply get rid of it.
152 * This simplifies the logic of the other
153 * functions that process these arrays.
155 memmove(®s[i], ®s[i + 1],
156 (ents - i - 1) * sizeof(regs[0]));
161 regs[i].phys_addr = base;
162 regs[i].reg_size = size;
167 sort(regs, ents, sizeof(struct linux_prom64_registers),
171 /* Kernel physical address base and size in bytes. */
172 unsigned long kern_base __read_mostly;
173 unsigned long kern_size __read_mostly;
175 /* Initial ramdisk setup */
176 extern unsigned long sparc_ramdisk_image64;
177 extern unsigned int sparc_ramdisk_image;
178 extern unsigned int sparc_ramdisk_size;
180 struct page *mem_map_zero __read_mostly;
181 EXPORT_SYMBOL(mem_map_zero);
183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
185 unsigned long sparc64_kern_pri_context __read_mostly;
186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
187 unsigned long sparc64_kern_sec_context __read_mostly;
189 int num_kernel_image_mappings;
191 #ifdef CONFIG_DEBUG_DCFLUSH
192 atomic_t dcpage_flushes = ATOMIC_INIT(0);
194 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
198 inline void flush_dcache_page_impl(struct page *page)
200 BUG_ON(tlb_type == hypervisor);
201 #ifdef CONFIG_DEBUG_DCFLUSH
202 atomic_inc(&dcpage_flushes);
205 #ifdef DCACHE_ALIASING_POSSIBLE
206 __flush_dcache_page(page_address(page),
207 ((tlb_type == spitfire) &&
208 page_mapping_file(page) != NULL));
210 if (page_mapping_file(page) != NULL &&
211 tlb_type == spitfire)
212 __flush_icache_page(__pa(page_address(page)));
216 #define PG_dcache_dirty PG_arch_1
217 #define PG_dcache_cpu_shift 32UL
218 #define PG_dcache_cpu_mask \
219 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
221 #define dcache_dirty_cpu(page) \
222 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
224 static inline void set_dcache_dirty(struct page *page, int this_cpu)
226 unsigned long mask = this_cpu;
227 unsigned long non_cpu_bits;
229 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
230 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
232 __asm__ __volatile__("1:\n\t"
234 "and %%g7, %1, %%g1\n\t"
235 "or %%g1, %0, %%g1\n\t"
236 "casx [%2], %%g7, %%g1\n\t"
238 "bne,pn %%xcc, 1b\n\t"
241 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
245 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
247 unsigned long mask = (1UL << PG_dcache_dirty);
249 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
252 "srlx %%g7, %4, %%g1\n\t"
253 "and %%g1, %3, %%g1\n\t"
255 "bne,pn %%icc, 2f\n\t"
256 " andn %%g7, %1, %%g1\n\t"
257 "casx [%2], %%g7, %%g1\n\t"
259 "bne,pn %%xcc, 1b\n\t"
263 : "r" (cpu), "r" (mask), "r" (&page->flags),
264 "i" (PG_dcache_cpu_mask),
265 "i" (PG_dcache_cpu_shift)
269 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
271 unsigned long tsb_addr = (unsigned long) ent;
273 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
274 tsb_addr = __pa(tsb_addr);
276 __tsb_insert(tsb_addr, tag, pte);
279 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
281 static void flush_dcache(unsigned long pfn)
285 page = pfn_to_page(pfn);
287 unsigned long pg_flags;
289 pg_flags = page->flags;
290 if (pg_flags & (1UL << PG_dcache_dirty)) {
291 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
293 int this_cpu = get_cpu();
295 /* This is just to optimize away some function calls
299 flush_dcache_page_impl(page);
301 smp_flush_dcache_page_impl(page, cpu);
303 clear_dcache_dirty_cpu(page, cpu);
310 /* mm->context.lock must be held */
311 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
312 unsigned long tsb_hash_shift, unsigned long address,
315 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
321 tsb += ((address >> tsb_hash_shift) &
322 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
323 tag = (address >> 22UL);
324 tsb_insert(tsb, tag, tte);
327 #ifdef CONFIG_HUGETLB_PAGE
328 static void __init add_huge_page_size(unsigned long size)
332 if (size_to_hstate(size))
335 order = ilog2(size) - PAGE_SHIFT;
336 hugetlb_add_hstate(order);
339 static int __init hugetlbpage_init(void)
341 add_huge_page_size(1UL << HPAGE_64K_SHIFT);
342 add_huge_page_size(1UL << HPAGE_SHIFT);
343 add_huge_page_size(1UL << HPAGE_256MB_SHIFT);
344 add_huge_page_size(1UL << HPAGE_2GB_SHIFT);
349 arch_initcall(hugetlbpage_init);
351 static void __init pud_huge_patch(void)
353 struct pud_huge_patch_entry *p;
356 p = &__pud_huge_patch;
358 *(unsigned int *)addr = p->insn;
360 __asm__ __volatile__("flush %0" : : "r" (addr));
363 bool __init arch_hugetlb_valid_size(unsigned long size)
365 unsigned int hugepage_shift = ilog2(size);
366 unsigned short hv_pgsz_idx;
367 unsigned int hv_pgsz_mask;
369 switch (hugepage_shift) {
370 case HPAGE_16GB_SHIFT:
371 hv_pgsz_mask = HV_PGSZ_MASK_16GB;
372 hv_pgsz_idx = HV_PGSZ_IDX_16GB;
375 case HPAGE_2GB_SHIFT:
376 hv_pgsz_mask = HV_PGSZ_MASK_2GB;
377 hv_pgsz_idx = HV_PGSZ_IDX_2GB;
379 case HPAGE_256MB_SHIFT:
380 hv_pgsz_mask = HV_PGSZ_MASK_256MB;
381 hv_pgsz_idx = HV_PGSZ_IDX_256MB;
384 hv_pgsz_mask = HV_PGSZ_MASK_4MB;
385 hv_pgsz_idx = HV_PGSZ_IDX_4MB;
387 case HPAGE_64K_SHIFT:
388 hv_pgsz_mask = HV_PGSZ_MASK_64K;
389 hv_pgsz_idx = HV_PGSZ_IDX_64K;
395 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U)
401 static int __init setup_hugepagesz(char *string)
403 unsigned long long hugepage_size;
406 hugepage_size = memparse(string, &string);
408 if (!arch_hugetlb_valid_size((unsigned long)hugepage_size)) {
410 pr_err("hugepagesz=%llu not supported by MMU.\n",
415 add_huge_page_size(hugepage_size);
421 __setup("hugepagesz=", setup_hugepagesz);
422 #endif /* CONFIG_HUGETLB_PAGE */
424 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
426 struct mm_struct *mm;
431 if (tlb_type != hypervisor) {
432 unsigned long pfn = pte_pfn(pte);
440 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
441 if (!pte_accessible(mm, pte))
444 spin_lock_irqsave(&mm->context.lock, flags);
447 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
448 if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) {
449 unsigned long hugepage_size = PAGE_SIZE;
451 if (is_vm_hugetlb_page(vma))
452 hugepage_size = huge_page_size(hstate_vma(vma));
454 if (hugepage_size >= PUD_SIZE) {
455 unsigned long mask = 0x1ffc00000UL;
457 /* Transfer bits [32:22] from address to resolve
460 pte_val(pte) &= ~mask;
461 pte_val(pte) |= (address & mask);
462 } else if (hugepage_size >= PMD_SIZE) {
463 /* We are fabricating 8MB pages using 4MB
466 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
469 if (hugepage_size >= PMD_SIZE) {
470 __update_mmu_tsb_insert(mm, MM_TSB_HUGE,
471 REAL_HPAGE_SHIFT, address, pte_val(pte));
477 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
478 address, pte_val(pte));
480 spin_unlock_irqrestore(&mm->context.lock, flags);
483 void flush_dcache_page(struct page *page)
485 struct address_space *mapping;
488 if (tlb_type == hypervisor)
491 /* Do not bother with the expensive D-cache flush if it
492 * is merely the zero page. The 'bigcore' testcase in GDB
493 * causes this case to run millions of times.
495 if (page == ZERO_PAGE(0))
498 this_cpu = get_cpu();
500 mapping = page_mapping_file(page);
501 if (mapping && !mapping_mapped(mapping)) {
502 int dirty = test_bit(PG_dcache_dirty, &page->flags);
504 int dirty_cpu = dcache_dirty_cpu(page);
506 if (dirty_cpu == this_cpu)
508 smp_flush_dcache_page_impl(page, dirty_cpu);
510 set_dcache_dirty(page, this_cpu);
512 /* We could delay the flush for the !page_mapping
513 * case too. But that case is for exec env/arg
514 * pages and those are %99 certainly going to get
515 * faulted into the tlb (and thus flushed) anyways.
517 flush_dcache_page_impl(page);
523 EXPORT_SYMBOL(flush_dcache_page);
525 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
527 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
528 if (tlb_type == spitfire) {
531 /* This code only runs on Spitfire cpus so this is
532 * why we can assume _PAGE_PADDR_4U.
534 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
535 unsigned long paddr, mask = _PAGE_PADDR_4U;
537 if (kaddr >= PAGE_OFFSET)
538 paddr = kaddr & mask;
540 pgd_t *pgdp = pgd_offset_k(kaddr);
541 p4d_t *p4dp = p4d_offset(pgdp, kaddr);
542 pud_t *pudp = pud_offset(p4dp, kaddr);
543 pmd_t *pmdp = pmd_offset(pudp, kaddr);
544 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
546 paddr = pte_val(*ptep) & mask;
548 __flush_icache_page(paddr);
552 EXPORT_SYMBOL(flush_icache_range);
554 void mmu_info(struct seq_file *m)
556 static const char *pgsz_strings[] = {
557 "8K", "64K", "512K", "4MB", "32MB",
558 "256MB", "2GB", "16GB",
562 if (tlb_type == cheetah)
563 seq_printf(m, "MMU Type\t: Cheetah\n");
564 else if (tlb_type == cheetah_plus)
565 seq_printf(m, "MMU Type\t: Cheetah+\n");
566 else if (tlb_type == spitfire)
567 seq_printf(m, "MMU Type\t: Spitfire\n");
568 else if (tlb_type == hypervisor)
569 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
571 seq_printf(m, "MMU Type\t: ???\n");
573 seq_printf(m, "MMU PGSZs\t: ");
575 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
576 if (cpu_pgsz_mask & (1UL << i)) {
577 seq_printf(m, "%s%s",
578 printed ? "," : "", pgsz_strings[i]);
584 #ifdef CONFIG_DEBUG_DCFLUSH
585 seq_printf(m, "DCPageFlushes\t: %d\n",
586 atomic_read(&dcpage_flushes));
588 seq_printf(m, "DCPageFlushesXC\t: %d\n",
589 atomic_read(&dcpage_flushes_xcall));
590 #endif /* CONFIG_SMP */
591 #endif /* CONFIG_DEBUG_DCFLUSH */
594 struct linux_prom_translation prom_trans[512] __read_mostly;
595 unsigned int prom_trans_ents __read_mostly;
597 unsigned long kern_locked_tte_data;
599 /* The obp translations are saved based on 8k pagesize, since obp can
600 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
601 * HI_OBP_ADDRESS range are handled in ktlb.S.
603 static inline int in_obp_range(unsigned long vaddr)
605 return (vaddr >= LOW_OBP_ADDRESS &&
606 vaddr < HI_OBP_ADDRESS);
609 static int cmp_ptrans(const void *a, const void *b)
611 const struct linux_prom_translation *x = a, *y = b;
613 if (x->virt > y->virt)
615 if (x->virt < y->virt)
620 /* Read OBP translations property into 'prom_trans[]'. */
621 static void __init read_obp_translations(void)
623 int n, node, ents, first, last, i;
625 node = prom_finddevice("/virtual-memory");
626 n = prom_getproplen(node, "translations");
627 if (unlikely(n == 0 || n == -1)) {
628 prom_printf("prom_mappings: Couldn't get size.\n");
631 if (unlikely(n > sizeof(prom_trans))) {
632 prom_printf("prom_mappings: Size %d is too big.\n", n);
636 if ((n = prom_getproperty(node, "translations",
637 (char *)&prom_trans[0],
638 sizeof(prom_trans))) == -1) {
639 prom_printf("prom_mappings: Couldn't get property.\n");
643 n = n / sizeof(struct linux_prom_translation);
647 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
650 /* Now kick out all the non-OBP entries. */
651 for (i = 0; i < ents; i++) {
652 if (in_obp_range(prom_trans[i].virt))
656 for (; i < ents; i++) {
657 if (!in_obp_range(prom_trans[i].virt))
662 for (i = 0; i < (last - first); i++) {
663 struct linux_prom_translation *src = &prom_trans[i + first];
664 struct linux_prom_translation *dest = &prom_trans[i];
668 for (; i < ents; i++) {
669 struct linux_prom_translation *dest = &prom_trans[i];
670 dest->virt = dest->size = dest->data = 0x0UL;
673 prom_trans_ents = last - first;
675 if (tlb_type == spitfire) {
676 /* Clear diag TTE bits. */
677 for (i = 0; i < prom_trans_ents; i++)
678 prom_trans[i].data &= ~0x0003fe0000000000UL;
681 /* Force execute bit on. */
682 for (i = 0; i < prom_trans_ents; i++)
683 prom_trans[i].data |= (tlb_type == hypervisor ?
684 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
687 static void __init hypervisor_tlb_lock(unsigned long vaddr,
691 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
694 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
695 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
700 static unsigned long kern_large_tte(unsigned long paddr);
702 static void __init remap_kernel(void)
704 unsigned long phys_page, tte_vaddr, tte_data;
705 int i, tlb_ent = sparc64_highest_locked_tlbent();
707 tte_vaddr = (unsigned long) KERNBASE;
708 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
709 tte_data = kern_large_tte(phys_page);
711 kern_locked_tte_data = tte_data;
713 /* Now lock us into the TLBs via Hypervisor or OBP. */
714 if (tlb_type == hypervisor) {
715 for (i = 0; i < num_kernel_image_mappings; i++) {
716 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
717 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
718 tte_vaddr += 0x400000;
719 tte_data += 0x400000;
722 for (i = 0; i < num_kernel_image_mappings; i++) {
723 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
724 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
725 tte_vaddr += 0x400000;
726 tte_data += 0x400000;
728 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
730 if (tlb_type == cheetah_plus) {
731 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
732 CTX_CHEETAH_PLUS_NUC);
733 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
734 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
739 static void __init inherit_prom_mappings(void)
741 /* Now fixup OBP's idea about where we really are mapped. */
742 printk("Remapping the kernel... ");
747 void prom_world(int enter)
752 __asm__ __volatile__("flushw");
755 void __flush_dcache_range(unsigned long start, unsigned long end)
759 if (tlb_type == spitfire) {
762 for (va = start; va < end; va += 32) {
763 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
767 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
770 for (va = start; va < end; va += 32)
771 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
775 "i" (ASI_DCACHE_INVALIDATE));
778 EXPORT_SYMBOL(__flush_dcache_range);
780 /* get_new_mmu_context() uses "cache + 1". */
781 DEFINE_SPINLOCK(ctx_alloc_lock);
782 unsigned long tlb_context_cache = CTX_FIRST_VERSION;
783 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
784 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
785 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
786 DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
788 static void mmu_context_wrap(void)
790 unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
791 unsigned long new_ver, new_ctx, old_ctx;
792 struct mm_struct *mm;
795 bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);
797 /* Reserve kernel context */
798 set_bit(0, mmu_context_bmap);
800 new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
801 if (unlikely(new_ver == 0))
802 new_ver = CTX_FIRST_VERSION;
803 tlb_context_cache = new_ver;
806 * Make sure that any new mm that are added into per_cpu_secondary_mm,
807 * are going to go through get_new_mmu_context() path.
812 * Updated versions to current on those CPUs that had valid secondary
815 for_each_online_cpu(cpu) {
817 * If a new mm is stored after we took this mm from the array,
818 * it will go into get_new_mmu_context() path, because we
819 * already bumped the version in tlb_context_cache.
821 mm = per_cpu(per_cpu_secondary_mm, cpu);
823 if (unlikely(!mm || mm == &init_mm))
826 old_ctx = mm->context.sparc64_ctx_val;
827 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
828 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
829 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
830 mm->context.sparc64_ctx_val = new_ctx;
835 /* Caller does TLB context flushing on local CPU if necessary.
836 * The caller also ensures that CTX_VALID(mm->context) is false.
838 * We must be careful about boundary cases so that we never
839 * let the user have CTX 0 (nucleus) or we ever use a CTX
840 * version of zero (and thus NO_CONTEXT would not be caught
841 * by version mis-match tests in mmu_context.h).
843 * Always invoked with interrupts disabled.
845 void get_new_mmu_context(struct mm_struct *mm)
847 unsigned long ctx, new_ctx;
848 unsigned long orig_pgsz_bits;
850 spin_lock(&ctx_alloc_lock);
852 /* wrap might have happened, test again if our context became valid */
853 if (unlikely(CTX_VALID(mm->context)))
855 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
856 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
857 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
858 if (new_ctx >= (1 << CTX_NR_BITS)) {
859 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
860 if (new_ctx >= ctx) {
865 if (mm->context.sparc64_ctx_val)
866 cpumask_clear(mm_cpumask(mm));
867 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
868 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
869 tlb_context_cache = new_ctx;
870 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
872 spin_unlock(&ctx_alloc_lock);
875 static int numa_enabled = 1;
876 static int numa_debug;
878 static int __init early_numa(char *p)
883 if (strstr(p, "off"))
886 if (strstr(p, "debug"))
891 early_param("numa", early_numa);
893 #define numadbg(f, a...) \
894 do { if (numa_debug) \
895 printk(KERN_INFO f, ## a); \
898 static void __init find_ramdisk(unsigned long phys_base)
900 #ifdef CONFIG_BLK_DEV_INITRD
901 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
902 unsigned long ramdisk_image;
904 /* Older versions of the bootloader only supported a
905 * 32-bit physical address for the ramdisk image
906 * location, stored at sparc_ramdisk_image. Newer
907 * SILO versions set sparc_ramdisk_image to zero and
908 * provide a full 64-bit physical address at
909 * sparc_ramdisk_image64.
911 ramdisk_image = sparc_ramdisk_image;
913 ramdisk_image = sparc_ramdisk_image64;
915 /* Another bootloader quirk. The bootloader normalizes
916 * the physical address to KERNBASE, so we have to
917 * factor that back out and add in the lowest valid
918 * physical page address to get the true physical address.
920 ramdisk_image -= KERNBASE;
921 ramdisk_image += phys_base;
923 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
924 ramdisk_image, sparc_ramdisk_size);
926 initrd_start = ramdisk_image;
927 initrd_end = ramdisk_image + sparc_ramdisk_size;
929 memblock_reserve(initrd_start, sparc_ramdisk_size);
931 initrd_start += PAGE_OFFSET;
932 initrd_end += PAGE_OFFSET;
937 struct node_mem_mask {
941 static struct node_mem_mask node_masks[MAX_NUMNODES];
942 static int num_node_masks;
944 #ifdef CONFIG_NEED_MULTIPLE_NODES
946 struct mdesc_mlgroup {
953 static struct mdesc_mlgroup *mlgroups;
954 static int num_mlgroups;
956 int numa_cpu_lookup_table[NR_CPUS];
957 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
959 struct mdesc_mblock {
962 u64 offset; /* RA-to-PA */
964 static struct mdesc_mblock *mblocks;
965 static int num_mblocks;
967 static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr)
969 struct mdesc_mblock *m = NULL;
972 for (i = 0; i < num_mblocks; i++) {
975 if (addr >= m->base &&
976 addr < (m->base + m->size)) {
984 static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid)
986 int prev_nid, new_nid;
988 prev_nid = NUMA_NO_NODE;
989 for ( ; start < end; start += PAGE_SIZE) {
990 for (new_nid = 0; new_nid < num_node_masks; new_nid++) {
991 struct node_mem_mask *p = &node_masks[new_nid];
993 if ((start & p->mask) == p->match) {
994 if (prev_nid == NUMA_NO_NODE)
1000 if (new_nid == num_node_masks) {
1002 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.",
1007 if (prev_nid != new_nid)
1012 return start > end ? end : start;
1015 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
1017 u64 ret_end, pa_start, m_mask, m_match, m_end;
1018 struct mdesc_mblock *mblock;
1021 if (tlb_type != hypervisor)
1022 return memblock_nid_range_sun4u(start, end, nid);
1024 mblock = addr_to_mblock(start);
1026 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]",
1034 pa_start = start + mblock->offset;
1038 for (_nid = 0; _nid < num_node_masks; _nid++) {
1039 struct node_mem_mask *const m = &node_masks[_nid];
1041 if ((pa_start & m->mask) == m->match) {
1048 if (num_node_masks == _nid) {
1049 /* We could not find NUMA group, so default to 0, but lets
1050 * search for latency group, so we could calculate the correct
1051 * end address that we return
1055 for (i = 0; i < num_mlgroups; i++) {
1056 struct mdesc_mlgroup *const m = &mlgroups[i];
1058 if ((pa_start & m->mask) == m->match) {
1065 if (i == num_mlgroups) {
1066 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]",
1075 * Each latency group has match and mask, and each memory block has an
1076 * offset. An address belongs to a latency group if its address matches
1077 * the following formula: ((addr + offset) & mask) == match
1078 * It is, however, slow to check every single page if it matches a
1079 * particular latency group. As optimization we calculate end value by
1080 * using bit arithmetics.
1082 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset;
1083 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
1084 ret_end = m_end > end ? end : m_end;
1092 /* This must be invoked after performing all of the necessary
1093 * memblock_set_node() calls for 'nid'. We need to be able to get
1094 * correct data from get_pfn_range_for_nid().
1096 static void __init allocate_node_data(int nid)
1098 struct pglist_data *p;
1099 unsigned long start_pfn, end_pfn;
1100 #ifdef CONFIG_NEED_MULTIPLE_NODES
1102 NODE_DATA(nid) = memblock_alloc_node(sizeof(struct pglist_data),
1103 SMP_CACHE_BYTES, nid);
1104 if (!NODE_DATA(nid)) {
1105 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
1109 NODE_DATA(nid)->node_id = nid;
1114 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
1115 p->node_start_pfn = start_pfn;
1116 p->node_spanned_pages = end_pfn - start_pfn;
1119 static void init_node_masks_nonnuma(void)
1121 #ifdef CONFIG_NEED_MULTIPLE_NODES
1125 numadbg("Initializing tables for non-numa.\n");
1127 node_masks[0].mask = 0;
1128 node_masks[0].match = 0;
1131 #ifdef CONFIG_NEED_MULTIPLE_NODES
1132 for (i = 0; i < NR_CPUS; i++)
1133 numa_cpu_lookup_table[i] = 0;
1135 cpumask_setall(&numa_cpumask_lookup_table[0]);
1139 #ifdef CONFIG_NEED_MULTIPLE_NODES
1140 struct pglist_data *node_data[MAX_NUMNODES];
1142 EXPORT_SYMBOL(numa_cpu_lookup_table);
1143 EXPORT_SYMBOL(numa_cpumask_lookup_table);
1144 EXPORT_SYMBOL(node_data);
1146 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
1151 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
1152 u64 target = mdesc_arc_target(md, arc);
1155 val = mdesc_get_property(md, target,
1156 "cfg-handle", NULL);
1157 if (val && *val == cfg_handle)
1163 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
1166 u64 arc, candidate, best_latency = ~(u64)0;
1168 candidate = MDESC_NODE_NULL;
1169 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1170 u64 target = mdesc_arc_target(md, arc);
1171 const char *name = mdesc_node_name(md, target);
1174 if (strcmp(name, "pio-latency-group"))
1177 val = mdesc_get_property(md, target, "latency", NULL);
1181 if (*val < best_latency) {
1183 best_latency = *val;
1187 if (candidate == MDESC_NODE_NULL)
1190 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
1193 int of_node_to_nid(struct device_node *dp)
1195 const struct linux_prom64_registers *regs;
1196 struct mdesc_handle *md;
1201 /* This is the right thing to do on currently supported
1202 * SUN4U NUMA platforms as well, as the PCI controller does
1203 * not sit behind any particular memory controller.
1208 regs = of_get_property(dp, "reg", NULL);
1212 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1218 mdesc_for_each_node_by_name(md, grp, "group") {
1219 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1231 static void __init add_node_ranges(void)
1233 struct memblock_region *reg;
1234 unsigned long prev_max;
1237 prev_max = memblock.memory.max;
1239 for_each_memblock(memory, reg) {
1240 unsigned long size = reg->size;
1241 unsigned long start, end;
1245 while (start < end) {
1246 unsigned long this_end;
1249 this_end = memblock_nid_range(start, end, &nid);
1251 numadbg("Setting memblock NUMA node nid[%d] "
1252 "start[%lx] end[%lx]\n",
1253 nid, start, this_end);
1255 memblock_set_node(start, this_end - start,
1256 &memblock.memory, nid);
1257 if (memblock.memory.max != prev_max)
1258 goto memblock_resized;
1264 static int __init grab_mlgroups(struct mdesc_handle *md)
1266 unsigned long paddr;
1270 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1275 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup),
1280 mlgroups = __va(paddr);
1281 num_mlgroups = count;
1284 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1285 struct mdesc_mlgroup *m = &mlgroups[count++];
1290 val = mdesc_get_property(md, node, "latency", NULL);
1292 val = mdesc_get_property(md, node, "address-match", NULL);
1294 val = mdesc_get_property(md, node, "address-mask", NULL);
1297 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1298 "match[%llx] mask[%llx]\n",
1299 count - 1, m->node, m->latency, m->match, m->mask);
1305 static int __init grab_mblocks(struct mdesc_handle *md)
1307 unsigned long paddr;
1311 mdesc_for_each_node_by_name(md, node, "mblock")
1316 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock),
1321 mblocks = __va(paddr);
1322 num_mblocks = count;
1325 mdesc_for_each_node_by_name(md, node, "mblock") {
1326 struct mdesc_mblock *m = &mblocks[count++];
1329 val = mdesc_get_property(md, node, "base", NULL);
1331 val = mdesc_get_property(md, node, "size", NULL);
1333 val = mdesc_get_property(md, node,
1334 "address-congruence-offset", NULL);
1336 /* The address-congruence-offset property is optional.
1337 * Explicity zero it be identifty this.
1344 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1345 count - 1, m->base, m->size, m->offset);
1351 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1352 u64 grp, cpumask_t *mask)
1356 cpumask_clear(mask);
1358 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1359 u64 target = mdesc_arc_target(md, arc);
1360 const char *name = mdesc_node_name(md, target);
1363 if (strcmp(name, "cpu"))
1365 id = mdesc_get_property(md, target, "id", NULL);
1366 if (*id < nr_cpu_ids)
1367 cpumask_set_cpu(*id, mask);
1371 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1375 for (i = 0; i < num_mlgroups; i++) {
1376 struct mdesc_mlgroup *m = &mlgroups[i];
1377 if (m->node == node)
1383 int __node_distance(int from, int to)
1385 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1386 pr_warn("Returning default NUMA distance value for %d->%d\n",
1388 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1390 return numa_latency[from][to];
1392 EXPORT_SYMBOL(__node_distance);
1394 static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1398 for (i = 0; i < MAX_NUMNODES; i++) {
1399 struct node_mem_mask *n = &node_masks[i];
1401 if ((grp->mask == n->mask) && (grp->match == n->match))
1407 static void __init find_numa_latencies_for_group(struct mdesc_handle *md,
1412 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1414 u64 target = mdesc_arc_target(md, arc);
1415 struct mdesc_mlgroup *m = find_mlgroup(target);
1419 tnode = find_best_numa_node_for_mlgroup(m);
1420 if (tnode == MAX_NUMNODES)
1422 numa_latency[index][tnode] = m->latency;
1426 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1429 struct mdesc_mlgroup *candidate = NULL;
1430 u64 arc, best_latency = ~(u64)0;
1431 struct node_mem_mask *n;
1433 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1434 u64 target = mdesc_arc_target(md, arc);
1435 struct mdesc_mlgroup *m = find_mlgroup(target);
1438 if (m->latency < best_latency) {
1440 best_latency = m->latency;
1446 if (num_node_masks != index) {
1447 printk(KERN_ERR "Inconsistent NUMA state, "
1448 "index[%d] != num_node_masks[%d]\n",
1449 index, num_node_masks);
1453 n = &node_masks[num_node_masks++];
1455 n->mask = candidate->mask;
1456 n->match = candidate->match;
1458 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n",
1459 index, n->mask, n->match, candidate->latency);
1464 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1470 numa_parse_mdesc_group_cpus(md, grp, &mask);
1472 for_each_cpu(cpu, &mask)
1473 numa_cpu_lookup_table[cpu] = index;
1474 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1477 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1478 for_each_cpu(cpu, &mask)
1483 return numa_attach_mlgroup(md, grp, index);
1486 static int __init numa_parse_mdesc(void)
1488 struct mdesc_handle *md = mdesc_grab();
1489 int i, j, err, count;
1492 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1493 if (node == MDESC_NODE_NULL) {
1498 err = grab_mblocks(md);
1502 err = grab_mlgroups(md);
1507 mdesc_for_each_node_by_name(md, node, "group") {
1508 err = numa_parse_mdesc_group(md, node, count);
1515 mdesc_for_each_node_by_name(md, node, "group") {
1516 find_numa_latencies_for_group(md, node, count);
1520 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1521 for (i = 0; i < MAX_NUMNODES; i++) {
1522 u64 self_latency = numa_latency[i][i];
1524 for (j = 0; j < MAX_NUMNODES; j++) {
1525 numa_latency[i][j] =
1526 (numa_latency[i][j] * LOCAL_DISTANCE) /
1533 for (i = 0; i < num_node_masks; i++) {
1534 allocate_node_data(i);
1544 static int __init numa_parse_jbus(void)
1546 unsigned long cpu, index;
1548 /* NUMA node id is encoded in bits 36 and higher, and there is
1549 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1552 for_each_present_cpu(cpu) {
1553 numa_cpu_lookup_table[cpu] = index;
1554 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1555 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1556 node_masks[index].match = cpu << 36UL;
1560 num_node_masks = index;
1564 for (index = 0; index < num_node_masks; index++) {
1565 allocate_node_data(index);
1566 node_set_online(index);
1572 static int __init numa_parse_sun4u(void)
1574 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1577 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1578 if ((ver >> 32UL) == __JALAPENO_ID ||
1579 (ver >> 32UL) == __SERRANO_ID)
1580 return numa_parse_jbus();
1585 static int __init bootmem_init_numa(void)
1590 numadbg("bootmem_init_numa()\n");
1592 /* Some sane defaults for numa latency values */
1593 for (i = 0; i < MAX_NUMNODES; i++) {
1594 for (j = 0; j < MAX_NUMNODES; j++)
1595 numa_latency[i][j] = (i == j) ?
1596 LOCAL_DISTANCE : REMOTE_DISTANCE;
1600 if (tlb_type == hypervisor)
1601 err = numa_parse_mdesc();
1603 err = numa_parse_sun4u();
1610 static int bootmem_init_numa(void)
1617 static void __init bootmem_init_nonnuma(void)
1619 unsigned long top_of_ram = memblock_end_of_DRAM();
1620 unsigned long total_ram = memblock_phys_mem_size();
1622 numadbg("bootmem_init_nonnuma()\n");
1624 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1625 top_of_ram, total_ram);
1626 printk(KERN_INFO "Memory hole size: %ldMB\n",
1627 (top_of_ram - total_ram) >> 20);
1629 init_node_masks_nonnuma();
1630 memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0);
1631 allocate_node_data(0);
1635 static unsigned long __init bootmem_init(unsigned long phys_base)
1637 unsigned long end_pfn;
1639 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1640 max_pfn = max_low_pfn = end_pfn;
1641 min_low_pfn = (phys_base >> PAGE_SHIFT);
1643 if (bootmem_init_numa() < 0)
1644 bootmem_init_nonnuma();
1646 /* Dump memblock with node info. */
1647 memblock_dump_all();
1649 /* XXX cpu notifier XXX */
1651 sparse_memory_present_with_active_regions(MAX_NUMNODES);
1657 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1658 static int pall_ents __initdata;
1660 static unsigned long max_phys_bits = 40;
1662 bool kern_addr_valid(unsigned long addr)
1670 if ((long)addr < 0L) {
1671 unsigned long pa = __pa(addr);
1673 if ((pa >> max_phys_bits) != 0UL)
1676 return pfn_valid(pa >> PAGE_SHIFT);
1679 if (addr >= (unsigned long) KERNBASE &&
1680 addr < (unsigned long)&_end)
1683 pgd = pgd_offset_k(addr);
1687 p4d = p4d_offset(pgd, addr);
1691 pud = pud_offset(p4d, addr);
1695 if (pud_large(*pud))
1696 return pfn_valid(pud_pfn(*pud));
1698 pmd = pmd_offset(pud, addr);
1702 if (pmd_large(*pmd))
1703 return pfn_valid(pmd_pfn(*pmd));
1705 pte = pte_offset_kernel(pmd, addr);
1709 return pfn_valid(pte_pfn(*pte));
1711 EXPORT_SYMBOL(kern_addr_valid);
1713 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1717 const unsigned long mask16gb = (1UL << 34) - 1UL;
1718 u64 pte_val = vstart;
1720 /* Each PUD is 8GB */
1721 if ((vstart & mask16gb) ||
1722 (vend - vstart <= mask16gb)) {
1723 pte_val ^= kern_linear_pte_xor[2];
1724 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1726 return vstart + PUD_SIZE;
1729 pte_val ^= kern_linear_pte_xor[3];
1730 pte_val |= _PAGE_PUD_HUGE;
1732 vend = vstart + mask16gb + 1UL;
1733 while (vstart < vend) {
1734 pud_val(*pud) = pte_val;
1736 pte_val += PUD_SIZE;
1743 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1746 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1752 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1756 const unsigned long mask256mb = (1UL << 28) - 1UL;
1757 const unsigned long mask2gb = (1UL << 31) - 1UL;
1758 u64 pte_val = vstart;
1760 /* Each PMD is 8MB */
1761 if ((vstart & mask256mb) ||
1762 (vend - vstart <= mask256mb)) {
1763 pte_val ^= kern_linear_pte_xor[0];
1764 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1766 return vstart + PMD_SIZE;
1769 if ((vstart & mask2gb) ||
1770 (vend - vstart <= mask2gb)) {
1771 pte_val ^= kern_linear_pte_xor[1];
1772 pte_val |= _PAGE_PMD_HUGE;
1773 vend = vstart + mask256mb + 1UL;
1775 pte_val ^= kern_linear_pte_xor[2];
1776 pte_val |= _PAGE_PMD_HUGE;
1777 vend = vstart + mask2gb + 1UL;
1780 while (vstart < vend) {
1781 pmd_val(*pmd) = pte_val;
1783 pte_val += PMD_SIZE;
1791 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1794 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1800 static unsigned long __ref kernel_map_range(unsigned long pstart,
1801 unsigned long pend, pgprot_t prot,
1804 unsigned long vstart = PAGE_OFFSET + pstart;
1805 unsigned long vend = PAGE_OFFSET + pend;
1806 unsigned long alloc_bytes = 0UL;
1808 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1809 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1814 while (vstart < vend) {
1815 unsigned long this_end, paddr = __pa(vstart);
1816 pgd_t *pgd = pgd_offset_k(vstart);
1822 if (pgd_none(*pgd)) {
1825 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1829 alloc_bytes += PAGE_SIZE;
1830 pgd_populate(&init_mm, pgd, new);
1833 p4d = p4d_offset(pgd, vstart);
1834 if (p4d_none(*p4d)) {
1837 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1841 alloc_bytes += PAGE_SIZE;
1842 p4d_populate(&init_mm, p4d, new);
1845 pud = pud_offset(p4d, vstart);
1846 if (pud_none(*pud)) {
1849 if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1850 vstart = kernel_map_hugepud(vstart, vend, pud);
1853 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1857 alloc_bytes += PAGE_SIZE;
1858 pud_populate(&init_mm, pud, new);
1861 pmd = pmd_offset(pud, vstart);
1862 if (pmd_none(*pmd)) {
1865 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1866 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1869 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1873 alloc_bytes += PAGE_SIZE;
1874 pmd_populate_kernel(&init_mm, pmd, new);
1877 pte = pte_offset_kernel(pmd, vstart);
1878 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1879 if (this_end > vend)
1882 while (vstart < this_end) {
1883 pte_val(*pte) = (paddr | pgprot_val(prot));
1885 vstart += PAGE_SIZE;
1894 panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n",
1895 __func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1899 static void __init flush_all_kernel_tsbs(void)
1903 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1904 struct tsb *ent = &swapper_tsb[i];
1906 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1908 #ifndef CONFIG_DEBUG_PAGEALLOC
1909 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1910 struct tsb *ent = &swapper_4m_tsb[i];
1912 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1917 extern unsigned int kvmap_linear_patch[1];
1919 static void __init kernel_physical_mapping_init(void)
1921 unsigned long i, mem_alloced = 0UL;
1922 bool use_huge = true;
1924 #ifdef CONFIG_DEBUG_PAGEALLOC
1927 for (i = 0; i < pall_ents; i++) {
1928 unsigned long phys_start, phys_end;
1930 phys_start = pall[i].phys_addr;
1931 phys_end = phys_start + pall[i].reg_size;
1933 mem_alloced += kernel_map_range(phys_start, phys_end,
1934 PAGE_KERNEL, use_huge);
1937 printk("Allocated %ld bytes for kernel page tables.\n",
1940 kvmap_linear_patch[0] = 0x01000000; /* nop */
1941 flushi(&kvmap_linear_patch[0]);
1943 flush_all_kernel_tsbs();
1948 #ifdef CONFIG_DEBUG_PAGEALLOC
1949 void __kernel_map_pages(struct page *page, int numpages, int enable)
1951 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1952 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1954 kernel_map_range(phys_start, phys_end,
1955 (enable ? PAGE_KERNEL : __pgprot(0)), false);
1957 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1958 PAGE_OFFSET + phys_end);
1960 /* we should perform an IPI and flush all tlbs,
1961 * but that can deadlock->flush only current cpu.
1963 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1964 PAGE_OFFSET + phys_end);
1968 unsigned long __init find_ecache_flush_span(unsigned long size)
1972 for (i = 0; i < pavail_ents; i++) {
1973 if (pavail[i].reg_size >= size)
1974 return pavail[i].phys_addr;
1980 unsigned long PAGE_OFFSET;
1981 EXPORT_SYMBOL(PAGE_OFFSET);
1983 unsigned long VMALLOC_END = 0x0000010000000000UL;
1984 EXPORT_SYMBOL(VMALLOC_END);
1986 unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
1987 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1989 static void __init setup_page_offset(void)
1991 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1992 /* Cheetah/Panther support a full 64-bit virtual
1993 * address, so we can use all that our page tables
1996 sparc64_va_hole_top = 0xfff0000000000000UL;
1997 sparc64_va_hole_bottom = 0x0010000000000000UL;
2000 } else if (tlb_type == hypervisor) {
2001 switch (sun4v_chip_type) {
2002 case SUN4V_CHIP_NIAGARA1:
2003 case SUN4V_CHIP_NIAGARA2:
2004 /* T1 and T2 support 48-bit virtual addresses. */
2005 sparc64_va_hole_top = 0xffff800000000000UL;
2006 sparc64_va_hole_bottom = 0x0000800000000000UL;
2010 case SUN4V_CHIP_NIAGARA3:
2011 /* T3 supports 48-bit virtual addresses. */
2012 sparc64_va_hole_top = 0xffff800000000000UL;
2013 sparc64_va_hole_bottom = 0x0000800000000000UL;
2017 case SUN4V_CHIP_NIAGARA4:
2018 case SUN4V_CHIP_NIAGARA5:
2019 case SUN4V_CHIP_SPARC64X:
2020 case SUN4V_CHIP_SPARC_M6:
2021 /* T4 and later support 52-bit virtual addresses. */
2022 sparc64_va_hole_top = 0xfff8000000000000UL;
2023 sparc64_va_hole_bottom = 0x0008000000000000UL;
2026 case SUN4V_CHIP_SPARC_M7:
2027 case SUN4V_CHIP_SPARC_SN:
2028 /* M7 and later support 52-bit virtual addresses. */
2029 sparc64_va_hole_top = 0xfff8000000000000UL;
2030 sparc64_va_hole_bottom = 0x0008000000000000UL;
2033 case SUN4V_CHIP_SPARC_M8:
2035 /* M8 and later support 54-bit virtual addresses.
2036 * However, restricting M8 and above VA bits to 53
2037 * as 4-level page table cannot support more than
2040 sparc64_va_hole_top = 0xfff0000000000000UL;
2041 sparc64_va_hole_bottom = 0x0010000000000000UL;
2047 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
2048 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
2053 PAGE_OFFSET = sparc64_va_hole_top;
2054 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
2055 (sparc64_va_hole_bottom >> 2));
2057 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
2058 PAGE_OFFSET, max_phys_bits);
2059 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
2060 VMALLOC_START, VMALLOC_END);
2061 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
2062 VMEMMAP_BASE, VMEMMAP_BASE << 1);
2065 static void __init tsb_phys_patch(void)
2067 struct tsb_ldquad_phys_patch_entry *pquad;
2068 struct tsb_phys_patch_entry *p;
2070 pquad = &__tsb_ldquad_phys_patch;
2071 while (pquad < &__tsb_ldquad_phys_patch_end) {
2072 unsigned long addr = pquad->addr;
2074 if (tlb_type == hypervisor)
2075 *(unsigned int *) addr = pquad->sun4v_insn;
2077 *(unsigned int *) addr = pquad->sun4u_insn;
2079 __asm__ __volatile__("flush %0"
2086 p = &__tsb_phys_patch;
2087 while (p < &__tsb_phys_patch_end) {
2088 unsigned long addr = p->addr;
2090 *(unsigned int *) addr = p->insn;
2092 __asm__ __volatile__("flush %0"
2100 /* Don't mark as init, we give this to the Hypervisor. */
2101 #ifndef CONFIG_DEBUG_PAGEALLOC
2102 #define NUM_KTSB_DESCR 2
2104 #define NUM_KTSB_DESCR 1
2106 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
2108 /* The swapper TSBs are loaded with a base sequence of:
2110 * sethi %uhi(SYMBOL), REG1
2111 * sethi %hi(SYMBOL), REG2
2112 * or REG1, %ulo(SYMBOL), REG1
2113 * or REG2, %lo(SYMBOL), REG2
2114 * sllx REG1, 32, REG1
2115 * or REG1, REG2, REG1
2117 * When we use physical addressing for the TSB accesses, we patch the
2118 * first four instructions in the above sequence.
2121 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
2123 unsigned long high_bits, low_bits;
2125 high_bits = (pa >> 32) & 0xffffffff;
2126 low_bits = (pa >> 0) & 0xffffffff;
2128 while (start < end) {
2129 unsigned int *ia = (unsigned int *)(unsigned long)*start;
2131 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
2132 __asm__ __volatile__("flush %0" : : "r" (ia));
2134 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
2135 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
2137 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
2138 __asm__ __volatile__("flush %0" : : "r" (ia + 2));
2140 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
2141 __asm__ __volatile__("flush %0" : : "r" (ia + 3));
2147 static void ktsb_phys_patch(void)
2149 extern unsigned int __swapper_tsb_phys_patch;
2150 extern unsigned int __swapper_tsb_phys_patch_end;
2151 unsigned long ktsb_pa;
2153 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2154 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
2155 &__swapper_tsb_phys_patch_end, ktsb_pa);
2156 #ifndef CONFIG_DEBUG_PAGEALLOC
2158 extern unsigned int __swapper_4m_tsb_phys_patch;
2159 extern unsigned int __swapper_4m_tsb_phys_patch_end;
2160 ktsb_pa = (kern_base +
2161 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2162 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
2163 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
2168 static void __init sun4v_ktsb_init(void)
2170 unsigned long ktsb_pa;
2172 /* First KTSB for PAGE_SIZE mappings. */
2173 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2175 switch (PAGE_SIZE) {
2178 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
2179 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
2183 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
2184 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
2188 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
2189 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
2192 case 4 * 1024 * 1024:
2193 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
2194 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
2198 ktsb_descr[0].assoc = 1;
2199 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
2200 ktsb_descr[0].ctx_idx = 0;
2201 ktsb_descr[0].tsb_base = ktsb_pa;
2202 ktsb_descr[0].resv = 0;
2204 #ifndef CONFIG_DEBUG_PAGEALLOC
2205 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
2206 ktsb_pa = (kern_base +
2207 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2209 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
2210 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
2211 HV_PGSZ_MASK_256MB |
2213 HV_PGSZ_MASK_16GB) &
2215 ktsb_descr[1].assoc = 1;
2216 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
2217 ktsb_descr[1].ctx_idx = 0;
2218 ktsb_descr[1].tsb_base = ktsb_pa;
2219 ktsb_descr[1].resv = 0;
2223 void sun4v_ktsb_register(void)
2225 unsigned long pa, ret;
2227 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
2229 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
2231 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
2232 "errors with %lx\n", pa, ret);
2237 static void __init sun4u_linear_pte_xor_finalize(void)
2239 #ifndef CONFIG_DEBUG_PAGEALLOC
2240 /* This is where we would add Panther support for
2241 * 32MB and 256MB pages.
2246 static void __init sun4v_linear_pte_xor_finalize(void)
2248 unsigned long pagecv_flag;
2250 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
2251 * enables MCD error. Do not set bit 9 on M7 processor.
2253 switch (sun4v_chip_type) {
2254 case SUN4V_CHIP_SPARC_M7:
2255 case SUN4V_CHIP_SPARC_M8:
2256 case SUN4V_CHIP_SPARC_SN:
2260 pagecv_flag = _PAGE_CV_4V;
2263 #ifndef CONFIG_DEBUG_PAGEALLOC
2264 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
2265 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2267 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
2268 _PAGE_P_4V | _PAGE_W_4V);
2270 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2273 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2274 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2276 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2277 _PAGE_P_4V | _PAGE_W_4V);
2279 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2282 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2283 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2285 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2286 _PAGE_P_4V | _PAGE_W_4V);
2288 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2293 /* paging_init() sets up the page tables */
2295 static unsigned long last_valid_pfn;
2297 static void sun4u_pgprot_init(void);
2298 static void sun4v_pgprot_init(void);
2300 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2301 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2302 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2303 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2304 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2305 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2307 /* We need to exclude reserved regions. This exclusion will include
2308 * vmlinux and initrd. To be more precise the initrd size could be used to
2309 * compute a new lower limit because it is freed later during initialization.
2311 static void __init reduce_memory(phys_addr_t limit_ram)
2313 limit_ram += memblock_reserved_size();
2314 memblock_enforce_memory_limit(limit_ram);
2317 void __init paging_init(void)
2319 unsigned long end_pfn, shift, phys_base;
2320 unsigned long real_end, i;
2322 setup_page_offset();
2324 /* These build time checkes make sure that the dcache_dirty_cpu()
2325 * page->flags usage will work.
2327 * When a page gets marked as dcache-dirty, we store the
2328 * cpu number starting at bit 32 in the page->flags. Also,
2329 * functions like clear_dcache_dirty_cpu use the cpu mask
2330 * in 13-bit signed-immediate instruction fields.
2334 * Page flags must not reach into upper 32 bits that are used
2335 * for the cpu number
2337 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2340 * The bit fields placed in the high range must not reach below
2341 * the 32 bit boundary. Otherwise we cannot place the cpu field
2342 * at the 32 bit boundary.
2344 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2345 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2347 BUILD_BUG_ON(NR_CPUS > 4096);
2349 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2350 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2352 /* Invalidate both kernel TSBs. */
2353 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2354 #ifndef CONFIG_DEBUG_PAGEALLOC
2355 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2358 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2359 * bit on M7 processor. This is a conflicting usage of the same
2360 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2361 * Detection error on all pages and this will lead to problems
2362 * later. Kernel does not run with MCD enabled and hence rest
2363 * of the required steps to fully configure memory corruption
2364 * detection are not taken. We need to ensure TTE.mcde is not
2365 * set on M7 processor. Compute the value of cacheability
2366 * flag for use later taking this into consideration.
2368 switch (sun4v_chip_type) {
2369 case SUN4V_CHIP_SPARC_M7:
2370 case SUN4V_CHIP_SPARC_M8:
2371 case SUN4V_CHIP_SPARC_SN:
2372 page_cache4v_flag = _PAGE_CP_4V;
2375 page_cache4v_flag = _PAGE_CACHE_4V;
2379 if (tlb_type == hypervisor)
2380 sun4v_pgprot_init();
2382 sun4u_pgprot_init();
2384 if (tlb_type == cheetah_plus ||
2385 tlb_type == hypervisor) {
2390 if (tlb_type == hypervisor)
2391 sun4v_patch_tlb_handlers();
2393 /* Find available physical memory...
2395 * Read it twice in order to work around a bug in openfirmware.
2396 * The call to grab this table itself can cause openfirmware to
2397 * allocate memory, which in turn can take away some space from
2398 * the list of available memory. Reading it twice makes sure
2399 * we really do get the final value.
2401 read_obp_translations();
2402 read_obp_memory("reg", &pall[0], &pall_ents);
2403 read_obp_memory("available", &pavail[0], &pavail_ents);
2404 read_obp_memory("available", &pavail[0], &pavail_ents);
2406 phys_base = 0xffffffffffffffffUL;
2407 for (i = 0; i < pavail_ents; i++) {
2408 phys_base = min(phys_base, pavail[i].phys_addr);
2409 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2412 memblock_reserve(kern_base, kern_size);
2414 find_ramdisk(phys_base);
2416 if (cmdline_memory_size)
2417 reduce_memory(cmdline_memory_size);
2419 memblock_allow_resize();
2420 memblock_dump_all();
2422 set_bit(0, mmu_context_bmap);
2424 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2426 real_end = (unsigned long)_end;
2427 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2428 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2429 num_kernel_image_mappings);
2431 /* Set kernel pgd to upper alias so physical page computations
2434 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2436 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2438 inherit_prom_mappings();
2440 /* Ok, we can use our TLB miss and window trap handlers safely. */
2445 prom_build_devicetree();
2446 of_populate_present_mask();
2448 of_fill_in_cpu_data();
2451 if (tlb_type == hypervisor) {
2453 mdesc_populate_present_mask(cpu_all_mask);
2455 mdesc_fill_in_cpu_data(cpu_all_mask);
2457 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2459 sun4v_linear_pte_xor_finalize();
2462 sun4v_ktsb_register();
2464 unsigned long impl, ver;
2466 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2467 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2469 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2470 impl = ((ver >> 32) & 0xffff);
2471 if (impl == PANTHER_IMPL)
2472 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2473 HV_PGSZ_MASK_256MB);
2475 sun4u_linear_pte_xor_finalize();
2478 /* Flush the TLBs and the 4M TSB so that the updated linear
2479 * pte XOR settings are realized for all mappings.
2482 #ifndef CONFIG_DEBUG_PAGEALLOC
2483 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2487 /* Setup bootmem... */
2488 last_valid_pfn = end_pfn = bootmem_init(phys_base);
2490 kernel_physical_mapping_init();
2493 unsigned long max_zone_pfns[MAX_NR_ZONES];
2495 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2497 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2499 free_area_init(max_zone_pfns);
2502 printk("Booting Linux...\n");
2505 int page_in_phys_avail(unsigned long paddr)
2511 for (i = 0; i < pavail_ents; i++) {
2512 unsigned long start, end;
2514 start = pavail[i].phys_addr;
2515 end = start + pavail[i].reg_size;
2517 if (paddr >= start && paddr < end)
2520 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2522 #ifdef CONFIG_BLK_DEV_INITRD
2523 if (paddr >= __pa(initrd_start) &&
2524 paddr < __pa(PAGE_ALIGN(initrd_end)))
2531 static void __init register_page_bootmem_info(void)
2533 #ifdef CONFIG_NEED_MULTIPLE_NODES
2536 for_each_online_node(i)
2537 if (NODE_DATA(i)->node_spanned_pages)
2538 register_page_bootmem_info_node(NODE_DATA(i));
2541 void __init mem_init(void)
2543 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2545 memblock_free_all();
2548 * Must be done after boot memory is put on freelist, because here we
2549 * might set fields in deferred struct pages that have not yet been
2550 * initialized, and memblock_free_all() initializes all the reserved
2551 * deferred pages for us.
2553 register_page_bootmem_info();
2556 * Set up the zero page, mark it reserved, so that page count
2557 * is not manipulated when freeing the page from user ptes.
2559 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2560 if (mem_map_zero == NULL) {
2561 prom_printf("paging_init: Cannot alloc zero page.\n");
2564 mark_page_reserved(mem_map_zero);
2566 mem_init_print_info(NULL);
2568 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2569 cheetah_ecache_flush_init();
2572 void free_initmem(void)
2574 unsigned long addr, initend;
2577 /* If the physical memory maps were trimmed by kernel command
2578 * line options, don't even try freeing this initmem stuff up.
2579 * The kernel image could have been in the trimmed out region
2580 * and if so the freeing below will free invalid page structs.
2582 if (cmdline_memory_size)
2586 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2588 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2589 initend = (unsigned long)(__init_end) & PAGE_MASK;
2590 for (; addr < initend; addr += PAGE_SIZE) {
2594 ((unsigned long) __va(kern_base)) -
2595 ((unsigned long) KERNBASE));
2596 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2599 free_reserved_page(virt_to_page(page));
2603 pgprot_t PAGE_KERNEL __read_mostly;
2604 EXPORT_SYMBOL(PAGE_KERNEL);
2606 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2607 pgprot_t PAGE_COPY __read_mostly;
2609 pgprot_t PAGE_SHARED __read_mostly;
2610 EXPORT_SYMBOL(PAGE_SHARED);
2612 unsigned long pg_iobits __read_mostly;
2614 unsigned long _PAGE_IE __read_mostly;
2615 EXPORT_SYMBOL(_PAGE_IE);
2617 unsigned long _PAGE_E __read_mostly;
2618 EXPORT_SYMBOL(_PAGE_E);
2620 unsigned long _PAGE_CACHE __read_mostly;
2621 EXPORT_SYMBOL(_PAGE_CACHE);
2623 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2624 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2625 int node, struct vmem_altmap *altmap)
2627 unsigned long pte_base;
2629 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2630 _PAGE_CP_4U | _PAGE_CV_4U |
2631 _PAGE_P_4U | _PAGE_W_4U);
2632 if (tlb_type == hypervisor)
2633 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2634 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2636 pte_base |= _PAGE_PMD_HUGE;
2638 vstart = vstart & PMD_MASK;
2639 vend = ALIGN(vend, PMD_SIZE);
2640 for (; vstart < vend; vstart += PMD_SIZE) {
2641 pgd_t *pgd = vmemmap_pgd_populate(vstart, node);
2650 p4d = vmemmap_p4d_populate(pgd, vstart, node);
2654 pud = vmemmap_pud_populate(p4d, vstart, node);
2658 pmd = pmd_offset(pud, vstart);
2659 pte = pmd_val(*pmd);
2660 if (!(pte & _PAGE_VALID)) {
2661 void *block = vmemmap_alloc_block(PMD_SIZE, node);
2666 pmd_val(*pmd) = pte_base | __pa(block);
2673 void vmemmap_free(unsigned long start, unsigned long end,
2674 struct vmem_altmap *altmap)
2677 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2679 static void prot_init_common(unsigned long page_none,
2680 unsigned long page_shared,
2681 unsigned long page_copy,
2682 unsigned long page_readonly,
2683 unsigned long page_exec_bit)
2685 PAGE_COPY = __pgprot(page_copy);
2686 PAGE_SHARED = __pgprot(page_shared);
2688 protection_map[0x0] = __pgprot(page_none);
2689 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2690 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2691 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2692 protection_map[0x4] = __pgprot(page_readonly);
2693 protection_map[0x5] = __pgprot(page_readonly);
2694 protection_map[0x6] = __pgprot(page_copy);
2695 protection_map[0x7] = __pgprot(page_copy);
2696 protection_map[0x8] = __pgprot(page_none);
2697 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2698 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2699 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2700 protection_map[0xc] = __pgprot(page_readonly);
2701 protection_map[0xd] = __pgprot(page_readonly);
2702 protection_map[0xe] = __pgprot(page_shared);
2703 protection_map[0xf] = __pgprot(page_shared);
2706 static void __init sun4u_pgprot_init(void)
2708 unsigned long page_none, page_shared, page_copy, page_readonly;
2709 unsigned long page_exec_bit;
2712 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2713 _PAGE_CACHE_4U | _PAGE_P_4U |
2714 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2716 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2717 _PAGE_CACHE_4U | _PAGE_P_4U |
2718 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2719 _PAGE_EXEC_4U | _PAGE_L_4U);
2721 _PAGE_IE = _PAGE_IE_4U;
2722 _PAGE_E = _PAGE_E_4U;
2723 _PAGE_CACHE = _PAGE_CACHE_4U;
2725 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2726 __ACCESS_BITS_4U | _PAGE_E_4U);
2728 #ifdef CONFIG_DEBUG_PAGEALLOC
2729 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2731 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2734 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2735 _PAGE_P_4U | _PAGE_W_4U);
2737 for (i = 1; i < 4; i++)
2738 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2740 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2741 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2742 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2745 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2746 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2747 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2748 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2749 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2750 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2751 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2753 page_exec_bit = _PAGE_EXEC_4U;
2755 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2759 static void __init sun4v_pgprot_init(void)
2761 unsigned long page_none, page_shared, page_copy, page_readonly;
2762 unsigned long page_exec_bit;
2765 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2766 page_cache4v_flag | _PAGE_P_4V |
2767 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2769 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2771 _PAGE_IE = _PAGE_IE_4V;
2772 _PAGE_E = _PAGE_E_4V;
2773 _PAGE_CACHE = page_cache4v_flag;
2775 #ifdef CONFIG_DEBUG_PAGEALLOC
2776 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2778 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2781 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2784 for (i = 1; i < 4; i++)
2785 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2787 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2788 __ACCESS_BITS_4V | _PAGE_E_4V);
2790 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2791 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2792 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2793 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2795 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2796 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2797 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2798 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2799 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2800 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2801 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2803 page_exec_bit = _PAGE_EXEC_4V;
2805 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2809 unsigned long pte_sz_bits(unsigned long sz)
2811 if (tlb_type == hypervisor) {
2815 return _PAGE_SZ8K_4V;
2817 return _PAGE_SZ64K_4V;
2819 return _PAGE_SZ512K_4V;
2820 case 4 * 1024 * 1024:
2821 return _PAGE_SZ4MB_4V;
2827 return _PAGE_SZ8K_4U;
2829 return _PAGE_SZ64K_4U;
2831 return _PAGE_SZ512K_4U;
2832 case 4 * 1024 * 1024:
2833 return _PAGE_SZ4MB_4U;
2838 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2842 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2843 pte_val(pte) |= (((unsigned long)space) << 32);
2844 pte_val(pte) |= pte_sz_bits(page_size);
2849 static unsigned long kern_large_tte(unsigned long paddr)
2853 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2854 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2855 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2856 if (tlb_type == hypervisor)
2857 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2858 page_cache4v_flag | _PAGE_P_4V |
2859 _PAGE_EXEC_4V | _PAGE_W_4V);
2864 /* If not locked, zap it. */
2865 void __flush_tlb_all(void)
2867 unsigned long pstate;
2870 __asm__ __volatile__("flushw\n\t"
2871 "rdpr %%pstate, %0\n\t"
2872 "wrpr %0, %1, %%pstate"
2875 if (tlb_type == hypervisor) {
2876 sun4v_mmu_demap_all();
2877 } else if (tlb_type == spitfire) {
2878 for (i = 0; i < 64; i++) {
2879 /* Spitfire Errata #32 workaround */
2880 /* NOTE: Always runs on spitfire, so no
2881 * cheetah+ page size encodings.
2883 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2887 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2889 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2890 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2893 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2894 spitfire_put_dtlb_data(i, 0x0UL);
2897 /* Spitfire Errata #32 workaround */
2898 /* NOTE: Always runs on spitfire, so no
2899 * cheetah+ page size encodings.
2901 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2905 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2907 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2908 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2911 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2912 spitfire_put_itlb_data(i, 0x0UL);
2915 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2916 cheetah_flush_dtlb_all();
2917 cheetah_flush_itlb_all();
2919 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2923 pte_t *pte_alloc_one_kernel(struct mm_struct *mm)
2925 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2929 pte = (pte_t *) page_address(page);
2934 pgtable_t pte_alloc_one(struct mm_struct *mm)
2936 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2939 if (!pgtable_pte_page_ctor(page)) {
2940 free_unref_page(page);
2943 return (pte_t *) page_address(page);
2946 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2948 free_page((unsigned long)pte);
2951 static void __pte_free(pgtable_t pte)
2953 struct page *page = virt_to_page(pte);
2955 pgtable_pte_page_dtor(page);
2959 void pte_free(struct mm_struct *mm, pgtable_t pte)
2964 void pgtable_free(void *table, bool is_page)
2969 kmem_cache_free(pgtable_cache, table);
2972 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2973 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2976 unsigned long pte, flags;
2977 struct mm_struct *mm;
2980 if (!pmd_large(entry) || !pmd_young(entry))
2983 pte = pmd_val(entry);
2985 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2986 if (!(pte & _PAGE_VALID))
2989 /* We are fabricating 8MB pages using 4MB real hw pages. */
2990 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2994 spin_lock_irqsave(&mm->context.lock, flags);
2996 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2997 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
3000 spin_unlock_irqrestore(&mm->context.lock, flags);
3002 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
3004 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
3005 static void context_reload(void *__data)
3007 struct mm_struct *mm = __data;
3009 if (mm == current->mm)
3010 load_secondary_context(mm);
3013 void hugetlb_setup(struct pt_regs *regs)
3015 struct mm_struct *mm = current->mm;
3016 struct tsb_config *tp;
3018 if (faulthandler_disabled() || !mm) {
3019 const struct exception_table_entry *entry;
3021 entry = search_exception_tables(regs->tpc);
3023 regs->tpc = entry->fixup;
3024 regs->tnpc = regs->tpc + 4;
3027 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
3028 die_if_kernel("HugeTSB in atomic", regs);
3031 tp = &mm->context.tsb_block[MM_TSB_HUGE];
3032 if (likely(tp->tsb == NULL))
3033 tsb_grow(mm, MM_TSB_HUGE, 0);
3035 tsb_context_switch(mm);
3038 /* On UltraSPARC-III+ and later, configure the second half of
3039 * the Data-TLB for huge pages.
3041 if (tlb_type == cheetah_plus) {
3042 bool need_context_reload = false;
3045 spin_lock_irq(&ctx_alloc_lock);
3046 ctx = mm->context.sparc64_ctx_val;
3047 ctx &= ~CTX_PGSZ_MASK;
3048 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
3049 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
3051 if (ctx != mm->context.sparc64_ctx_val) {
3052 /* When changing the page size fields, we
3053 * must perform a context flush so that no
3054 * stale entries match. This flush must
3055 * occur with the original context register
3058 do_flush_tlb_mm(mm);
3060 /* Reload the context register of all processors
3061 * also executing in this address space.
3063 mm->context.sparc64_ctx_val = ctx;
3064 need_context_reload = true;
3066 spin_unlock_irq(&ctx_alloc_lock);
3068 if (need_context_reload)
3069 on_each_cpu(context_reload, mm, 0);
3074 static struct resource code_resource = {
3075 .name = "Kernel code",
3076 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3079 static struct resource data_resource = {
3080 .name = "Kernel data",
3081 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3084 static struct resource bss_resource = {
3085 .name = "Kernel bss",
3086 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3089 static inline resource_size_t compute_kern_paddr(void *addr)
3091 return (resource_size_t) (addr - KERNBASE + kern_base);
3094 static void __init kernel_lds_init(void)
3096 code_resource.start = compute_kern_paddr(_text);
3097 code_resource.end = compute_kern_paddr(_etext - 1);
3098 data_resource.start = compute_kern_paddr(_etext);
3099 data_resource.end = compute_kern_paddr(_edata - 1);
3100 bss_resource.start = compute_kern_paddr(__bss_start);
3101 bss_resource.end = compute_kern_paddr(_end - 1);
3104 static int __init report_memory(void)
3107 struct resource *res;
3111 for (i = 0; i < pavail_ents; i++) {
3112 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
3115 pr_warn("Failed to allocate source.\n");
3119 res->name = "System RAM";
3120 res->start = pavail[i].phys_addr;
3121 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
3122 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
3124 if (insert_resource(&iomem_resource, res) < 0) {
3125 pr_warn("Resource insertion failed.\n");
3129 insert_resource(res, &code_resource);
3130 insert_resource(res, &data_resource);
3131 insert_resource(res, &bss_resource);
3136 arch_initcall(report_memory);
3139 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
3141 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range
3144 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
3146 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
3147 if (start < LOW_OBP_ADDRESS) {
3148 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
3149 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
3151 if (end > HI_OBP_ADDRESS) {
3152 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
3153 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
3156 flush_tsb_kernel_range(start, end);
3157 do_flush_tlb_kernel_range(start, end);
3161 void copy_user_highpage(struct page *to, struct page *from,
3162 unsigned long vaddr, struct vm_area_struct *vma)
3166 vfrom = kmap_atomic(from);
3167 vto = kmap_atomic(to);
3168 copy_user_page(vto, vfrom, vaddr, to);
3170 kunmap_atomic(vfrom);
3172 /* If this page has ADI enabled, copy over any ADI tags
3175 if (vma->vm_flags & VM_SPARC_ADI) {
3176 unsigned long pfrom, pto, i, adi_tag;
3178 pfrom = page_to_phys(from);
3179 pto = page_to_phys(to);
3181 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3182 asm volatile("ldxa [%1] %2, %0\n\t"
3184 : "r" (i), "i" (ASI_MCD_REAL));
3185 asm volatile("stxa %0, [%1] %2\n\t"
3187 : "r" (adi_tag), "r" (pto),
3188 "i" (ASI_MCD_REAL));
3189 pto += adi_blksize();
3191 asm volatile("membar #Sync\n\t");
3194 EXPORT_SYMBOL(copy_user_highpage);
3196 void copy_highpage(struct page *to, struct page *from)
3200 vfrom = kmap_atomic(from);
3201 vto = kmap_atomic(to);
3202 copy_page(vto, vfrom);
3204 kunmap_atomic(vfrom);
3206 /* If this platform is ADI enabled, copy any ADI tags
3209 if (adi_capable()) {
3210 unsigned long pfrom, pto, i, adi_tag;
3212 pfrom = page_to_phys(from);
3213 pto = page_to_phys(to);
3215 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3216 asm volatile("ldxa [%1] %2, %0\n\t"
3218 : "r" (i), "i" (ASI_MCD_REAL));
3219 asm volatile("stxa %0, [%1] %2\n\t"
3221 : "r" (adi_tag), "r" (pto),
3222 "i" (ASI_MCD_REAL));
3223 pto += adi_blksize();
3225 asm volatile("membar #Sync\n\t");
3228 EXPORT_SYMBOL(copy_highpage);