1 /* arch/sparc64/kernel/traps.c
3 * Copyright (C) 1995,1997,2008 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
8 * I like traps on v9, :))))
11 #include <linux/module.h>
12 #include <linux/sched.h>
13 #include <linux/linkage.h>
14 #include <linux/kernel.h>
15 #include <linux/signal.h>
16 #include <linux/smp.h>
18 #include <linux/init.h>
19 #include <linux/kdebug.h>
22 #include <asm/delay.h>
23 #include <asm/system.h>
24 #include <asm/ptrace.h>
25 #include <asm/oplib.h>
27 #include <asm/pgtable.h>
28 #include <asm/unistd.h>
29 #include <asm/uaccess.h>
30 #include <asm/fpumacro.h>
33 #include <asm/estate.h>
34 #include <asm/chafsr.h>
35 #include <asm/sfafsr.h>
36 #include <asm/psrcompat.h>
37 #include <asm/processor.h>
38 #include <asm/timer.h>
41 #include <asm/memctrl.h>
46 /* When an irrecoverable trap occurs at tl > 0, the trap entry
47 * code logs the trap state registers at every level in the trap
48 * stack. It is found at (pt_regs + sizeof(pt_regs)) and the layout
61 static void dump_tl1_traplog(struct tl1_traplog *p)
65 printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, "
66 "dumping track stack.\n", p->tl);
68 limit = (tlb_type == hypervisor) ? 2 : 4;
69 for (i = 0; i < limit; i++) {
71 "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
72 "TNPC[%016lx] TT[%lx]\n",
74 p->trapstack[i].tstate, p->trapstack[i].tpc,
75 p->trapstack[i].tnpc, p->trapstack[i].tt);
76 printk("TRAPLOG: TPC<%pS>\n", (void *) p->trapstack[i].tpc);
80 void bad_trap(struct pt_regs *regs, long lvl)
85 if (notify_die(DIE_TRAP, "bad trap", regs,
86 0, lvl, SIGTRAP) == NOTIFY_STOP)
90 sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
91 die_if_kernel(buffer, regs);
95 if (regs->tstate & TSTATE_PRIV) {
96 sprintf(buffer, "Kernel bad sw trap %lx", lvl);
97 die_if_kernel(buffer, regs);
99 if (test_thread_flag(TIF_32BIT)) {
100 regs->tpc &= 0xffffffff;
101 regs->tnpc &= 0xffffffff;
103 info.si_signo = SIGILL;
105 info.si_code = ILL_ILLTRP;
106 info.si_addr = (void __user *)regs->tpc;
107 info.si_trapno = lvl;
108 force_sig_info(SIGILL, &info, current);
111 void bad_trap_tl1(struct pt_regs *regs, long lvl)
115 if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
116 0, lvl, SIGTRAP) == NOTIFY_STOP)
119 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
121 sprintf (buffer, "Bad trap %lx at tl>0", lvl);
122 die_if_kernel (buffer, regs);
125 #ifdef CONFIG_DEBUG_BUGVERBOSE
126 void do_BUG(const char *file, int line)
129 printk("kernel BUG at %s:%d!\n", file, line);
131 EXPORT_SYMBOL(do_BUG);
134 static DEFINE_SPINLOCK(dimm_handler_lock);
135 static dimm_printer_t dimm_handler;
137 static int sprintf_dimm(int synd_code, unsigned long paddr, char *buf, int buflen)
142 spin_lock_irqsave(&dimm_handler_lock, flags);
144 ret = dimm_handler(synd_code, paddr, buf, buflen);
145 } else if (tlb_type == spitfire) {
146 if (prom_getunumber(synd_code, paddr, buf, buflen) == -1)
152 spin_unlock_irqrestore(&dimm_handler_lock, flags);
157 int register_dimm_printer(dimm_printer_t func)
162 spin_lock_irqsave(&dimm_handler_lock, flags);
167 spin_unlock_irqrestore(&dimm_handler_lock, flags);
171 EXPORT_SYMBOL_GPL(register_dimm_printer);
173 void unregister_dimm_printer(dimm_printer_t func)
177 spin_lock_irqsave(&dimm_handler_lock, flags);
178 if (dimm_handler == func)
180 spin_unlock_irqrestore(&dimm_handler_lock, flags);
182 EXPORT_SYMBOL_GPL(unregister_dimm_printer);
184 void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
188 if (notify_die(DIE_TRAP, "instruction access exception", regs,
189 0, 0x8, SIGTRAP) == NOTIFY_STOP)
192 if (regs->tstate & TSTATE_PRIV) {
193 printk("spitfire_insn_access_exception: SFSR[%016lx] "
194 "SFAR[%016lx], going.\n", sfsr, sfar);
195 die_if_kernel("Iax", regs);
197 if (test_thread_flag(TIF_32BIT)) {
198 regs->tpc &= 0xffffffff;
199 regs->tnpc &= 0xffffffff;
201 info.si_signo = SIGSEGV;
203 info.si_code = SEGV_MAPERR;
204 info.si_addr = (void __user *)regs->tpc;
206 force_sig_info(SIGSEGV, &info, current);
209 void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
211 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
212 0, 0x8, SIGTRAP) == NOTIFY_STOP)
215 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
216 spitfire_insn_access_exception(regs, sfsr, sfar);
219 void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
221 unsigned short type = (type_ctx >> 16);
222 unsigned short ctx = (type_ctx & 0xffff);
225 if (notify_die(DIE_TRAP, "instruction access exception", regs,
226 0, 0x8, SIGTRAP) == NOTIFY_STOP)
229 if (regs->tstate & TSTATE_PRIV) {
230 printk("sun4v_insn_access_exception: ADDR[%016lx] "
231 "CTX[%04x] TYPE[%04x], going.\n",
233 die_if_kernel("Iax", regs);
236 if (test_thread_flag(TIF_32BIT)) {
237 regs->tpc &= 0xffffffff;
238 regs->tnpc &= 0xffffffff;
240 info.si_signo = SIGSEGV;
242 info.si_code = SEGV_MAPERR;
243 info.si_addr = (void __user *) addr;
245 force_sig_info(SIGSEGV, &info, current);
248 void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
250 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
251 0, 0x8, SIGTRAP) == NOTIFY_STOP)
254 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
255 sun4v_insn_access_exception(regs, addr, type_ctx);
258 void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
262 if (notify_die(DIE_TRAP, "data access exception", regs,
263 0, 0x30, SIGTRAP) == NOTIFY_STOP)
266 if (regs->tstate & TSTATE_PRIV) {
267 /* Test if this comes from uaccess places. */
268 const struct exception_table_entry *entry;
270 entry = search_exception_tables(regs->tpc);
272 /* Ouch, somebody is trying VM hole tricks on us... */
273 #ifdef DEBUG_EXCEPTIONS
274 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
275 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
276 regs->tpc, entry->fixup);
278 regs->tpc = entry->fixup;
279 regs->tnpc = regs->tpc + 4;
283 printk("spitfire_data_access_exception: SFSR[%016lx] "
284 "SFAR[%016lx], going.\n", sfsr, sfar);
285 die_if_kernel("Dax", regs);
288 info.si_signo = SIGSEGV;
290 info.si_code = SEGV_MAPERR;
291 info.si_addr = (void __user *)sfar;
293 force_sig_info(SIGSEGV, &info, current);
296 void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
298 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
299 0, 0x30, SIGTRAP) == NOTIFY_STOP)
302 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
303 spitfire_data_access_exception(regs, sfsr, sfar);
306 void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
308 unsigned short type = (type_ctx >> 16);
309 unsigned short ctx = (type_ctx & 0xffff);
312 if (notify_die(DIE_TRAP, "data access exception", regs,
313 0, 0x8, SIGTRAP) == NOTIFY_STOP)
316 if (regs->tstate & TSTATE_PRIV) {
317 printk("sun4v_data_access_exception: ADDR[%016lx] "
318 "CTX[%04x] TYPE[%04x], going.\n",
320 die_if_kernel("Dax", regs);
323 if (test_thread_flag(TIF_32BIT)) {
324 regs->tpc &= 0xffffffff;
325 regs->tnpc &= 0xffffffff;
327 info.si_signo = SIGSEGV;
329 info.si_code = SEGV_MAPERR;
330 info.si_addr = (void __user *) addr;
332 force_sig_info(SIGSEGV, &info, current);
335 void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
337 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
338 0, 0x8, SIGTRAP) == NOTIFY_STOP)
341 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
342 sun4v_data_access_exception(regs, addr, type_ctx);
346 #include "pci_impl.h"
349 /* When access exceptions happen, we must do this. */
350 static void spitfire_clean_and_reenable_l1_caches(void)
354 if (tlb_type != spitfire)
358 for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
359 spitfire_put_icache_tag(va, 0x0);
360 spitfire_put_dcache_tag(va, 0x0);
363 /* Re-enable in LSU. */
364 __asm__ __volatile__("flush %%g6\n\t"
366 "stxa %0, [%%g0] %1\n\t"
369 : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
370 LSU_CONTROL_IM | LSU_CONTROL_DM),
371 "i" (ASI_LSU_CONTROL)
375 static void spitfire_enable_estate_errors(void)
377 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
380 : "r" (ESTATE_ERR_ALL),
381 "i" (ASI_ESTATE_ERROR_EN));
384 static char ecc_syndrome_table[] = {
385 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
386 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
387 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
388 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
389 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
390 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
391 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
392 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
393 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
394 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
395 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
396 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
397 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
398 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
399 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
400 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
401 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
402 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
403 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
404 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
405 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
406 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
407 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
408 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
409 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
410 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
411 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
412 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
413 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
414 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
415 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
416 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
419 static char *syndrome_unknown = "<Unknown>";
421 static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long bit)
423 unsigned short scode;
424 char memmod_str[64], *p;
427 scode = ecc_syndrome_table[udbl & 0xff];
428 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
429 p = syndrome_unknown;
432 printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
433 "Memory Module \"%s\"\n",
434 smp_processor_id(), scode, p);
438 scode = ecc_syndrome_table[udbh & 0xff];
439 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
440 p = syndrome_unknown;
443 printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
444 "Memory Module \"%s\"\n",
445 smp_processor_id(), scode, p);
450 static void spitfire_cee_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, int tl1, struct pt_regs *regs)
453 printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
454 "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx] TL>1[%d]\n",
455 smp_processor_id(), afsr, afar, udbl, udbh, tl1);
457 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_CE);
459 /* We always log it, even if someone is listening for this
462 notify_die(DIE_TRAP, "Correctable ECC Error", regs,
463 0, TRAP_TYPE_CEE, SIGTRAP);
465 /* The Correctable ECC Error trap does not disable I/D caches. So
466 * we only have to restore the ESTATE Error Enable register.
468 spitfire_enable_estate_errors();
471 static void spitfire_ue_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long tt, int tl1, struct pt_regs *regs)
475 printk(KERN_WARNING "CPU[%d]: Uncorrectable Error AFSR[%lx] "
476 "AFAR[%lx] UDBL[%lx] UDBH[%ld] TT[%lx] TL>1[%d]\n",
477 smp_processor_id(), afsr, afar, udbl, udbh, tt, tl1);
479 /* XXX add more human friendly logging of the error status
480 * XXX as is implemented for cheetah
483 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_UE);
485 /* We always log it, even if someone is listening for this
488 notify_die(DIE_TRAP, "Uncorrectable Error", regs,
491 if (regs->tstate & TSTATE_PRIV) {
493 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
494 die_if_kernel("UE", regs);
497 /* XXX need more intelligent processing here, such as is implemented
498 * XXX for cheetah errors, in fact if the E-cache still holds the
499 * XXX line with bad parity this will loop
502 spitfire_clean_and_reenable_l1_caches();
503 spitfire_enable_estate_errors();
505 if (test_thread_flag(TIF_32BIT)) {
506 regs->tpc &= 0xffffffff;
507 regs->tnpc &= 0xffffffff;
509 info.si_signo = SIGBUS;
511 info.si_code = BUS_OBJERR;
512 info.si_addr = (void *)0;
514 force_sig_info(SIGBUS, &info, current);
517 void spitfire_access_error(struct pt_regs *regs, unsigned long status_encoded, unsigned long afar)
519 unsigned long afsr, tt, udbh, udbl;
522 afsr = (status_encoded & SFSTAT_AFSR_MASK) >> SFSTAT_AFSR_SHIFT;
523 tt = (status_encoded & SFSTAT_TRAP_TYPE) >> SFSTAT_TRAP_TYPE_SHIFT;
524 tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0;
525 udbl = (status_encoded & SFSTAT_UDBL_MASK) >> SFSTAT_UDBL_SHIFT;
526 udbh = (status_encoded & SFSTAT_UDBH_MASK) >> SFSTAT_UDBH_SHIFT;
529 if (tt == TRAP_TYPE_DAE &&
530 pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
531 spitfire_clean_and_reenable_l1_caches();
532 spitfire_enable_estate_errors();
534 pci_poke_faulted = 1;
535 regs->tnpc = regs->tpc + 4;
540 if (afsr & SFAFSR_UE)
541 spitfire_ue_log(afsr, afar, udbh, udbl, tt, tl1, regs);
543 if (tt == TRAP_TYPE_CEE) {
544 /* Handle the case where we took a CEE trap, but ACK'd
545 * only the UE state in the UDB error registers.
547 if (afsr & SFAFSR_UE) {
548 if (udbh & UDBE_CE) {
549 __asm__ __volatile__(
550 "stxa %0, [%1] %2\n\t"
553 : "r" (udbh & UDBE_CE),
554 "r" (0x0), "i" (ASI_UDB_ERROR_W));
556 if (udbl & UDBE_CE) {
557 __asm__ __volatile__(
558 "stxa %0, [%1] %2\n\t"
561 : "r" (udbl & UDBE_CE),
562 "r" (0x18), "i" (ASI_UDB_ERROR_W));
566 spitfire_cee_log(afsr, afar, udbh, udbl, tl1, regs);
570 int cheetah_pcache_forced_on;
572 void cheetah_enable_pcache(void)
576 printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
579 __asm__ __volatile__("ldxa [%%g0] %1, %0"
581 : "i" (ASI_DCU_CONTROL_REG));
582 dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
583 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
586 : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
589 /* Cheetah error trap handling. */
590 static unsigned long ecache_flush_physbase;
591 static unsigned long ecache_flush_linesize;
592 static unsigned long ecache_flush_size;
594 /* This table is ordered in priority of errors and matches the
595 * AFAR overwrite policy as well.
598 struct afsr_error_table {
603 static const char CHAFSR_PERR_msg[] =
604 "System interface protocol error";
605 static const char CHAFSR_IERR_msg[] =
606 "Internal processor error";
607 static const char CHAFSR_ISAP_msg[] =
608 "System request parity error on incoming addresss";
609 static const char CHAFSR_UCU_msg[] =
610 "Uncorrectable E-cache ECC error for ifetch/data";
611 static const char CHAFSR_UCC_msg[] =
612 "SW Correctable E-cache ECC error for ifetch/data";
613 static const char CHAFSR_UE_msg[] =
614 "Uncorrectable system bus data ECC error for read";
615 static const char CHAFSR_EDU_msg[] =
616 "Uncorrectable E-cache ECC error for stmerge/blkld";
617 static const char CHAFSR_EMU_msg[] =
618 "Uncorrectable system bus MTAG error";
619 static const char CHAFSR_WDU_msg[] =
620 "Uncorrectable E-cache ECC error for writeback";
621 static const char CHAFSR_CPU_msg[] =
622 "Uncorrectable ECC error for copyout";
623 static const char CHAFSR_CE_msg[] =
624 "HW corrected system bus data ECC error for read";
625 static const char CHAFSR_EDC_msg[] =
626 "HW corrected E-cache ECC error for stmerge/blkld";
627 static const char CHAFSR_EMC_msg[] =
628 "HW corrected system bus MTAG ECC error";
629 static const char CHAFSR_WDC_msg[] =
630 "HW corrected E-cache ECC error for writeback";
631 static const char CHAFSR_CPC_msg[] =
632 "HW corrected ECC error for copyout";
633 static const char CHAFSR_TO_msg[] =
634 "Unmapped error from system bus";
635 static const char CHAFSR_BERR_msg[] =
636 "Bus error response from system bus";
637 static const char CHAFSR_IVC_msg[] =
638 "HW corrected system bus data ECC error for ivec read";
639 static const char CHAFSR_IVU_msg[] =
640 "Uncorrectable system bus data ECC error for ivec read";
641 static struct afsr_error_table __cheetah_error_table[] = {
642 { CHAFSR_PERR, CHAFSR_PERR_msg },
643 { CHAFSR_IERR, CHAFSR_IERR_msg },
644 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
645 { CHAFSR_UCU, CHAFSR_UCU_msg },
646 { CHAFSR_UCC, CHAFSR_UCC_msg },
647 { CHAFSR_UE, CHAFSR_UE_msg },
648 { CHAFSR_EDU, CHAFSR_EDU_msg },
649 { CHAFSR_EMU, CHAFSR_EMU_msg },
650 { CHAFSR_WDU, CHAFSR_WDU_msg },
651 { CHAFSR_CPU, CHAFSR_CPU_msg },
652 { CHAFSR_CE, CHAFSR_CE_msg },
653 { CHAFSR_EDC, CHAFSR_EDC_msg },
654 { CHAFSR_EMC, CHAFSR_EMC_msg },
655 { CHAFSR_WDC, CHAFSR_WDC_msg },
656 { CHAFSR_CPC, CHAFSR_CPC_msg },
657 { CHAFSR_TO, CHAFSR_TO_msg },
658 { CHAFSR_BERR, CHAFSR_BERR_msg },
659 /* These two do not update the AFAR. */
660 { CHAFSR_IVC, CHAFSR_IVC_msg },
661 { CHAFSR_IVU, CHAFSR_IVU_msg },
664 static const char CHPAFSR_DTO_msg[] =
665 "System bus unmapped error for prefetch/storequeue-read";
666 static const char CHPAFSR_DBERR_msg[] =
667 "System bus error for prefetch/storequeue-read";
668 static const char CHPAFSR_THCE_msg[] =
669 "Hardware corrected E-cache Tag ECC error";
670 static const char CHPAFSR_TSCE_msg[] =
671 "SW handled correctable E-cache Tag ECC error";
672 static const char CHPAFSR_TUE_msg[] =
673 "Uncorrectable E-cache Tag ECC error";
674 static const char CHPAFSR_DUE_msg[] =
675 "System bus uncorrectable data ECC error due to prefetch/store-fill";
676 static struct afsr_error_table __cheetah_plus_error_table[] = {
677 { CHAFSR_PERR, CHAFSR_PERR_msg },
678 { CHAFSR_IERR, CHAFSR_IERR_msg },
679 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
680 { CHAFSR_UCU, CHAFSR_UCU_msg },
681 { CHAFSR_UCC, CHAFSR_UCC_msg },
682 { CHAFSR_UE, CHAFSR_UE_msg },
683 { CHAFSR_EDU, CHAFSR_EDU_msg },
684 { CHAFSR_EMU, CHAFSR_EMU_msg },
685 { CHAFSR_WDU, CHAFSR_WDU_msg },
686 { CHAFSR_CPU, CHAFSR_CPU_msg },
687 { CHAFSR_CE, CHAFSR_CE_msg },
688 { CHAFSR_EDC, CHAFSR_EDC_msg },
689 { CHAFSR_EMC, CHAFSR_EMC_msg },
690 { CHAFSR_WDC, CHAFSR_WDC_msg },
691 { CHAFSR_CPC, CHAFSR_CPC_msg },
692 { CHAFSR_TO, CHAFSR_TO_msg },
693 { CHAFSR_BERR, CHAFSR_BERR_msg },
694 { CHPAFSR_DTO, CHPAFSR_DTO_msg },
695 { CHPAFSR_DBERR, CHPAFSR_DBERR_msg },
696 { CHPAFSR_THCE, CHPAFSR_THCE_msg },
697 { CHPAFSR_TSCE, CHPAFSR_TSCE_msg },
698 { CHPAFSR_TUE, CHPAFSR_TUE_msg },
699 { CHPAFSR_DUE, CHPAFSR_DUE_msg },
700 /* These two do not update the AFAR. */
701 { CHAFSR_IVC, CHAFSR_IVC_msg },
702 { CHAFSR_IVU, CHAFSR_IVU_msg },
705 static const char JPAFSR_JETO_msg[] =
706 "System interface protocol error, hw timeout caused";
707 static const char JPAFSR_SCE_msg[] =
708 "Parity error on system snoop results";
709 static const char JPAFSR_JEIC_msg[] =
710 "System interface protocol error, illegal command detected";
711 static const char JPAFSR_JEIT_msg[] =
712 "System interface protocol error, illegal ADTYPE detected";
713 static const char JPAFSR_OM_msg[] =
714 "Out of range memory error has occurred";
715 static const char JPAFSR_ETP_msg[] =
716 "Parity error on L2 cache tag SRAM";
717 static const char JPAFSR_UMS_msg[] =
718 "Error due to unsupported store";
719 static const char JPAFSR_RUE_msg[] =
720 "Uncorrectable ECC error from remote cache/memory";
721 static const char JPAFSR_RCE_msg[] =
722 "Correctable ECC error from remote cache/memory";
723 static const char JPAFSR_BP_msg[] =
724 "JBUS parity error on returned read data";
725 static const char JPAFSR_WBP_msg[] =
726 "JBUS parity error on data for writeback or block store";
727 static const char JPAFSR_FRC_msg[] =
728 "Foreign read to DRAM incurring correctable ECC error";
729 static const char JPAFSR_FRU_msg[] =
730 "Foreign read to DRAM incurring uncorrectable ECC error";
731 static struct afsr_error_table __jalapeno_error_table[] = {
732 { JPAFSR_JETO, JPAFSR_JETO_msg },
733 { JPAFSR_SCE, JPAFSR_SCE_msg },
734 { JPAFSR_JEIC, JPAFSR_JEIC_msg },
735 { JPAFSR_JEIT, JPAFSR_JEIT_msg },
736 { CHAFSR_PERR, CHAFSR_PERR_msg },
737 { CHAFSR_IERR, CHAFSR_IERR_msg },
738 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
739 { CHAFSR_UCU, CHAFSR_UCU_msg },
740 { CHAFSR_UCC, CHAFSR_UCC_msg },
741 { CHAFSR_UE, CHAFSR_UE_msg },
742 { CHAFSR_EDU, CHAFSR_EDU_msg },
743 { JPAFSR_OM, JPAFSR_OM_msg },
744 { CHAFSR_WDU, CHAFSR_WDU_msg },
745 { CHAFSR_CPU, CHAFSR_CPU_msg },
746 { CHAFSR_CE, CHAFSR_CE_msg },
747 { CHAFSR_EDC, CHAFSR_EDC_msg },
748 { JPAFSR_ETP, JPAFSR_ETP_msg },
749 { CHAFSR_WDC, CHAFSR_WDC_msg },
750 { CHAFSR_CPC, CHAFSR_CPC_msg },
751 { CHAFSR_TO, CHAFSR_TO_msg },
752 { CHAFSR_BERR, CHAFSR_BERR_msg },
753 { JPAFSR_UMS, JPAFSR_UMS_msg },
754 { JPAFSR_RUE, JPAFSR_RUE_msg },
755 { JPAFSR_RCE, JPAFSR_RCE_msg },
756 { JPAFSR_BP, JPAFSR_BP_msg },
757 { JPAFSR_WBP, JPAFSR_WBP_msg },
758 { JPAFSR_FRC, JPAFSR_FRC_msg },
759 { JPAFSR_FRU, JPAFSR_FRU_msg },
760 /* These two do not update the AFAR. */
761 { CHAFSR_IVU, CHAFSR_IVU_msg },
764 static struct afsr_error_table *cheetah_error_table;
765 static unsigned long cheetah_afsr_errors;
767 struct cheetah_err_info *cheetah_error_log;
769 static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
771 struct cheetah_err_info *p;
772 int cpu = smp_processor_id();
774 if (!cheetah_error_log)
777 p = cheetah_error_log + (cpu * 2);
778 if ((afsr & CHAFSR_TL1) != 0UL)
784 extern unsigned int tl0_icpe[], tl1_icpe[];
785 extern unsigned int tl0_dcpe[], tl1_dcpe[];
786 extern unsigned int tl0_fecc[], tl1_fecc[];
787 extern unsigned int tl0_cee[], tl1_cee[];
788 extern unsigned int tl0_iae[], tl1_iae[];
789 extern unsigned int tl0_dae[], tl1_dae[];
790 extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
791 extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
792 extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
793 extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
794 extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
796 void __init cheetah_ecache_flush_init(void)
798 unsigned long largest_size, smallest_linesize, order, ver;
801 /* Scan all cpu device tree nodes, note two values:
802 * 1) largest E-cache size
803 * 2) smallest E-cache line size
806 smallest_linesize = ~0UL;
808 for (i = 0; i < NR_CPUS; i++) {
811 val = cpu_data(i).ecache_size;
815 if (val > largest_size)
818 val = cpu_data(i).ecache_line_size;
819 if (val < smallest_linesize)
820 smallest_linesize = val;
824 if (largest_size == 0UL || smallest_linesize == ~0UL) {
825 prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
830 ecache_flush_size = (2 * largest_size);
831 ecache_flush_linesize = smallest_linesize;
833 ecache_flush_physbase = find_ecache_flush_span(ecache_flush_size);
835 if (ecache_flush_physbase == ~0UL) {
836 prom_printf("cheetah_ecache_flush_init: Cannot find %d byte "
837 "contiguous physical memory.\n",
842 /* Now allocate error trap reporting scoreboard. */
843 sz = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
844 for (order = 0; order < MAX_ORDER; order++) {
845 if ((PAGE_SIZE << order) >= sz)
848 cheetah_error_log = (struct cheetah_err_info *)
849 __get_free_pages(GFP_KERNEL, order);
850 if (!cheetah_error_log) {
851 prom_printf("cheetah_ecache_flush_init: Failed to allocate "
852 "error logging scoreboard (%d bytes).\n", sz);
855 memset(cheetah_error_log, 0, PAGE_SIZE << order);
857 /* Mark all AFSRs as invalid so that the trap handler will
858 * log new new information there.
860 for (i = 0; i < 2 * NR_CPUS; i++)
861 cheetah_error_log[i].afsr = CHAFSR_INVALID;
863 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
864 if ((ver >> 32) == __JALAPENO_ID ||
865 (ver >> 32) == __SERRANO_ID) {
866 cheetah_error_table = &__jalapeno_error_table[0];
867 cheetah_afsr_errors = JPAFSR_ERRORS;
868 } else if ((ver >> 32) == 0x003e0015) {
869 cheetah_error_table = &__cheetah_plus_error_table[0];
870 cheetah_afsr_errors = CHPAFSR_ERRORS;
872 cheetah_error_table = &__cheetah_error_table[0];
873 cheetah_afsr_errors = CHAFSR_ERRORS;
876 /* Now patch trap tables. */
877 memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
878 memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
879 memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
880 memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
881 memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
882 memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
883 memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
884 memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
885 if (tlb_type == cheetah_plus) {
886 memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
887 memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
888 memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
889 memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
894 static void cheetah_flush_ecache(void)
896 unsigned long flush_base = ecache_flush_physbase;
897 unsigned long flush_linesize = ecache_flush_linesize;
898 unsigned long flush_size = ecache_flush_size;
900 __asm__ __volatile__("1: subcc %0, %4, %0\n\t"
901 " bne,pt %%xcc, 1b\n\t"
902 " ldxa [%2 + %0] %3, %%g0\n\t"
904 : "0" (flush_size), "r" (flush_base),
905 "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
908 static void cheetah_flush_ecache_line(unsigned long physaddr)
912 physaddr &= ~(8UL - 1UL);
913 physaddr = (ecache_flush_physbase +
914 (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
915 alias = physaddr + (ecache_flush_size >> 1UL);
916 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
917 "ldxa [%1] %2, %%g0\n\t"
920 : "r" (physaddr), "r" (alias),
921 "i" (ASI_PHYS_USE_EC));
924 /* Unfortunately, the diagnostic access to the I-cache tags we need to
925 * use to clear the thing interferes with I-cache coherency transactions.
927 * So we must only flush the I-cache when it is disabled.
929 static void __cheetah_flush_icache(void)
931 unsigned int icache_size, icache_line_size;
934 icache_size = local_cpu_data().icache_size;
935 icache_line_size = local_cpu_data().icache_line_size;
937 /* Clear the valid bits in all the tags. */
938 for (addr = 0; addr < icache_size; addr += icache_line_size) {
939 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
942 : "r" (addr | (2 << 3)),
947 static void cheetah_flush_icache(void)
949 unsigned long dcu_save;
951 /* Save current DCU, disable I-cache. */
952 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
953 "or %0, %2, %%g1\n\t"
954 "stxa %%g1, [%%g0] %1\n\t"
957 : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
960 __cheetah_flush_icache();
962 /* Restore DCU register */
963 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
966 : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
969 static void cheetah_flush_dcache(void)
971 unsigned int dcache_size, dcache_line_size;
974 dcache_size = local_cpu_data().dcache_size;
975 dcache_line_size = local_cpu_data().dcache_line_size;
977 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
978 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
981 : "r" (addr), "i" (ASI_DCACHE_TAG));
985 /* In order to make the even parity correct we must do two things.
986 * First, we clear DC_data_parity and set DC_utag to an appropriate value.
987 * Next, we clear out all 32-bytes of data for that line. Data of
988 * all-zero + tag parity value of zero == correct parity.
990 static void cheetah_plus_zap_dcache_parity(void)
992 unsigned int dcache_size, dcache_line_size;
995 dcache_size = local_cpu_data().dcache_size;
996 dcache_line_size = local_cpu_data().dcache_line_size;
998 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
999 unsigned long tag = (addr >> 14);
1002 __asm__ __volatile__("membar #Sync\n\t"
1003 "stxa %0, [%1] %2\n\t"
1006 : "r" (tag), "r" (addr),
1007 "i" (ASI_DCACHE_UTAG));
1008 for (line = addr; line < addr + dcache_line_size; line += 8)
1009 __asm__ __volatile__("membar #Sync\n\t"
1010 "stxa %%g0, [%0] %1\n\t"
1014 "i" (ASI_DCACHE_DATA));
1018 /* Conversion tables used to frob Cheetah AFSR syndrome values into
1019 * something palatable to the memory controller driver get_unumber
1043 static unsigned char cheetah_ecc_syntab[] = {
1044 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1045 /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
1046 /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
1047 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1048 /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
1049 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1050 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1051 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1052 /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
1053 /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
1054 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1055 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1056 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1057 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1058 /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1059 /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1060 /*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
1061 /*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
1062 /*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
1063 /*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
1064 /*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
1065 /*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
1066 /*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
1067 /*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
1068 /*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
1069 /*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
1070 /*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
1071 /*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
1072 /*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
1073 /*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
1074 /*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
1075 /*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
1077 static unsigned char cheetah_mtag_syntab[] = {
1088 /* Return the highest priority error conditon mentioned. */
1089 static inline unsigned long cheetah_get_hipri(unsigned long afsr)
1091 unsigned long tmp = 0;
1094 for (i = 0; cheetah_error_table[i].mask; i++) {
1095 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
1101 static const char *cheetah_get_string(unsigned long bit)
1105 for (i = 0; cheetah_error_table[i].mask; i++) {
1106 if ((bit & cheetah_error_table[i].mask) != 0UL)
1107 return cheetah_error_table[i].name;
1112 static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1113 unsigned long afsr, unsigned long afar, int recoverable)
1115 unsigned long hipri;
1118 printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
1119 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1121 (afsr & CHAFSR_TL1) ? 1 : 0);
1122 printk("%s" "ERROR(%d): TPC[%lx] TNPC[%lx] O7[%lx] TSTATE[%lx]\n",
1123 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1124 regs->tpc, regs->tnpc, regs->u_regs[UREG_I7], regs->tstate);
1125 printk("%s" "ERROR(%d): ",
1126 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id());
1127 printk("TPC<%pS>\n", (void *) regs->tpc);
1128 printk("%s" "ERROR(%d): M_SYND(%lx), E_SYND(%lx)%s%s\n",
1129 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1130 (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
1131 (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
1132 (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
1133 (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
1134 hipri = cheetah_get_hipri(afsr);
1135 printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
1136 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1137 hipri, cheetah_get_string(hipri));
1139 /* Try to get unumber if relevant. */
1140 #define ESYND_ERRORS (CHAFSR_IVC | CHAFSR_IVU | \
1141 CHAFSR_CPC | CHAFSR_CPU | \
1142 CHAFSR_UE | CHAFSR_CE | \
1143 CHAFSR_EDC | CHAFSR_EDU | \
1144 CHAFSR_UCC | CHAFSR_UCU | \
1145 CHAFSR_WDU | CHAFSR_WDC)
1146 #define MSYND_ERRORS (CHAFSR_EMC | CHAFSR_EMU)
1147 if (afsr & ESYND_ERRORS) {
1151 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1152 syndrome = cheetah_ecc_syntab[syndrome];
1153 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1155 printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1156 (recoverable ? KERN_WARNING : KERN_CRIT),
1157 smp_processor_id(), unum);
1158 } else if (afsr & MSYND_ERRORS) {
1162 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1163 syndrome = cheetah_mtag_syntab[syndrome];
1164 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1166 printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1167 (recoverable ? KERN_WARNING : KERN_CRIT),
1168 smp_processor_id(), unum);
1171 /* Now dump the cache snapshots. */
1172 printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx]\n",
1173 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1174 (int) info->dcache_index,
1178 printk("%s" "ERROR(%d): D-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n",
1179 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1180 info->dcache_data[0],
1181 info->dcache_data[1],
1182 info->dcache_data[2],
1183 info->dcache_data[3]);
1184 printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx] "
1185 "u[%016llx] l[%016llx]\n",
1186 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1187 (int) info->icache_index,
1192 info->icache_lower);
1193 printk("%s" "ERROR(%d): I-cache INSN0[%016llx] INSN1[%016llx] INSN2[%016llx] INSN3[%016llx]\n",
1194 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1195 info->icache_data[0],
1196 info->icache_data[1],
1197 info->icache_data[2],
1198 info->icache_data[3]);
1199 printk("%s" "ERROR(%d): I-cache INSN4[%016llx] INSN5[%016llx] INSN6[%016llx] INSN7[%016llx]\n",
1200 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1201 info->icache_data[4],
1202 info->icache_data[5],
1203 info->icache_data[6],
1204 info->icache_data[7]);
1205 printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016llx]\n",
1206 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1207 (int) info->ecache_index, info->ecache_tag);
1208 printk("%s" "ERROR(%d): E-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n",
1209 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1210 info->ecache_data[0],
1211 info->ecache_data[1],
1212 info->ecache_data[2],
1213 info->ecache_data[3]);
1215 afsr = (afsr & ~hipri) & cheetah_afsr_errors;
1216 while (afsr != 0UL) {
1217 unsigned long bit = cheetah_get_hipri(afsr);
1219 printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
1220 (recoverable ? KERN_WARNING : KERN_CRIT),
1221 bit, cheetah_get_string(bit));
1227 printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
1230 static int cheetah_recheck_errors(struct cheetah_err_info *logp)
1232 unsigned long afsr, afar;
1235 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1238 if ((afsr & cheetah_afsr_errors) != 0) {
1240 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1248 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1250 : : "r" (afsr), "i" (ASI_AFSR));
1255 void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1257 struct cheetah_err_info local_snapshot, *p;
1261 cheetah_flush_ecache();
1263 p = cheetah_get_error_log(afsr);
1265 prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
1267 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1268 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1272 /* Grab snapshot of logged error. */
1273 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1275 /* If the current trap snapshot does not match what the
1276 * trap handler passed along into our args, big trouble.
1277 * In such a case, mark the local copy as invalid.
1279 * Else, it matches and we mark the afsr in the non-local
1280 * copy as invalid so we may log new error traps there.
1282 if (p->afsr != afsr || p->afar != afar)
1283 local_snapshot.afsr = CHAFSR_INVALID;
1285 p->afsr = CHAFSR_INVALID;
1287 cheetah_flush_icache();
1288 cheetah_flush_dcache();
1290 /* Re-enable I-cache/D-cache */
1291 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1292 "or %%g1, %1, %%g1\n\t"
1293 "stxa %%g1, [%%g0] %0\n\t"
1296 : "i" (ASI_DCU_CONTROL_REG),
1297 "i" (DCU_DC | DCU_IC)
1300 /* Re-enable error reporting */
1301 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1302 "or %%g1, %1, %%g1\n\t"
1303 "stxa %%g1, [%%g0] %0\n\t"
1306 : "i" (ASI_ESTATE_ERROR_EN),
1307 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1310 /* Decide if we can continue after handling this trap and
1311 * logging the error.
1314 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1317 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1318 * error was logged while we had error reporting traps disabled.
1320 if (cheetah_recheck_errors(&local_snapshot)) {
1321 unsigned long new_afsr = local_snapshot.afsr;
1323 /* If we got a new asynchronous error, die... */
1324 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1325 CHAFSR_WDU | CHAFSR_CPU |
1326 CHAFSR_IVU | CHAFSR_UE |
1327 CHAFSR_BERR | CHAFSR_TO))
1332 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1335 panic("Irrecoverable Fast-ECC error trap.\n");
1337 /* Flush E-cache to kick the error trap handlers out. */
1338 cheetah_flush_ecache();
1341 /* Try to fix a correctable error by pushing the line out from
1342 * the E-cache. Recheck error reporting registers to see if the
1343 * problem is intermittent.
1345 static int cheetah_fix_ce(unsigned long physaddr)
1347 unsigned long orig_estate;
1348 unsigned long alias1, alias2;
1351 /* Make sure correctable error traps are disabled. */
1352 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t"
1353 "andn %0, %1, %%g1\n\t"
1354 "stxa %%g1, [%%g0] %2\n\t"
1356 : "=&r" (orig_estate)
1357 : "i" (ESTATE_ERROR_CEEN),
1358 "i" (ASI_ESTATE_ERROR_EN)
1361 /* We calculate alias addresses that will force the
1362 * cache line in question out of the E-cache. Then
1363 * we bring it back in with an atomic instruction so
1364 * that we get it in some modified/exclusive state,
1365 * then we displace it again to try and get proper ECC
1366 * pushed back into the system.
1368 physaddr &= ~(8UL - 1UL);
1369 alias1 = (ecache_flush_physbase +
1370 (physaddr & ((ecache_flush_size >> 1) - 1)));
1371 alias2 = alias1 + (ecache_flush_size >> 1);
1372 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t"
1373 "ldxa [%1] %3, %%g0\n\t"
1374 "casxa [%2] %3, %%g0, %%g0\n\t"
1375 "ldxa [%0] %3, %%g0\n\t"
1376 "ldxa [%1] %3, %%g0\n\t"
1379 : "r" (alias1), "r" (alias2),
1380 "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1382 /* Did that trigger another error? */
1383 if (cheetah_recheck_errors(NULL)) {
1384 /* Try one more time. */
1385 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
1387 : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1388 if (cheetah_recheck_errors(NULL))
1393 /* No new error, intermittent problem. */
1397 /* Restore error enables. */
1398 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1400 : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
1405 /* Return non-zero if PADDR is a valid physical memory address. */
1406 static int cheetah_check_main_memory(unsigned long paddr)
1408 unsigned long vaddr = PAGE_OFFSET + paddr;
1410 if (vaddr > (unsigned long) high_memory)
1413 return kern_addr_valid(vaddr);
1416 void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1418 struct cheetah_err_info local_snapshot, *p;
1419 int recoverable, is_memory;
1421 p = cheetah_get_error_log(afsr);
1423 prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
1425 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1426 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1430 /* Grab snapshot of logged error. */
1431 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1433 /* If the current trap snapshot does not match what the
1434 * trap handler passed along into our args, big trouble.
1435 * In such a case, mark the local copy as invalid.
1437 * Else, it matches and we mark the afsr in the non-local
1438 * copy as invalid so we may log new error traps there.
1440 if (p->afsr != afsr || p->afar != afar)
1441 local_snapshot.afsr = CHAFSR_INVALID;
1443 p->afsr = CHAFSR_INVALID;
1445 is_memory = cheetah_check_main_memory(afar);
1447 if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
1448 /* XXX Might want to log the results of this operation
1449 * XXX somewhere... -DaveM
1451 cheetah_fix_ce(afar);
1455 int flush_all, flush_line;
1457 flush_all = flush_line = 0;
1458 if ((afsr & CHAFSR_EDC) != 0UL) {
1459 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
1463 } else if ((afsr & CHAFSR_CPC) != 0UL) {
1464 if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
1470 /* Trap handler only disabled I-cache, flush it. */
1471 cheetah_flush_icache();
1473 /* Re-enable I-cache */
1474 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1475 "or %%g1, %1, %%g1\n\t"
1476 "stxa %%g1, [%%g0] %0\n\t"
1479 : "i" (ASI_DCU_CONTROL_REG),
1484 cheetah_flush_ecache();
1485 else if (flush_line)
1486 cheetah_flush_ecache_line(afar);
1489 /* Re-enable error reporting */
1490 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1491 "or %%g1, %1, %%g1\n\t"
1492 "stxa %%g1, [%%g0] %0\n\t"
1495 : "i" (ASI_ESTATE_ERROR_EN),
1496 "i" (ESTATE_ERROR_CEEN)
1499 /* Decide if we can continue after handling this trap and
1500 * logging the error.
1503 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1506 /* Re-check AFSR/AFAR */
1507 (void) cheetah_recheck_errors(&local_snapshot);
1510 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1513 panic("Irrecoverable Correctable-ECC error trap.\n");
1516 void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1518 struct cheetah_err_info local_snapshot, *p;
1519 int recoverable, is_memory;
1522 /* Check for the special PCI poke sequence. */
1523 if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
1524 cheetah_flush_icache();
1525 cheetah_flush_dcache();
1527 /* Re-enable I-cache/D-cache */
1528 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1529 "or %%g1, %1, %%g1\n\t"
1530 "stxa %%g1, [%%g0] %0\n\t"
1533 : "i" (ASI_DCU_CONTROL_REG),
1534 "i" (DCU_DC | DCU_IC)
1537 /* Re-enable error reporting */
1538 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1539 "or %%g1, %1, %%g1\n\t"
1540 "stxa %%g1, [%%g0] %0\n\t"
1543 : "i" (ASI_ESTATE_ERROR_EN),
1544 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1547 (void) cheetah_recheck_errors(NULL);
1549 pci_poke_faulted = 1;
1551 regs->tnpc = regs->tpc + 4;
1556 p = cheetah_get_error_log(afsr);
1558 prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
1560 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1561 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1565 /* Grab snapshot of logged error. */
1566 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1568 /* If the current trap snapshot does not match what the
1569 * trap handler passed along into our args, big trouble.
1570 * In such a case, mark the local copy as invalid.
1572 * Else, it matches and we mark the afsr in the non-local
1573 * copy as invalid so we may log new error traps there.
1575 if (p->afsr != afsr || p->afar != afar)
1576 local_snapshot.afsr = CHAFSR_INVALID;
1578 p->afsr = CHAFSR_INVALID;
1580 is_memory = cheetah_check_main_memory(afar);
1583 int flush_all, flush_line;
1585 flush_all = flush_line = 0;
1586 if ((afsr & CHAFSR_EDU) != 0UL) {
1587 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
1591 } else if ((afsr & CHAFSR_BERR) != 0UL) {
1592 if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
1598 cheetah_flush_icache();
1599 cheetah_flush_dcache();
1601 /* Re-enable I/D caches */
1602 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1603 "or %%g1, %1, %%g1\n\t"
1604 "stxa %%g1, [%%g0] %0\n\t"
1607 : "i" (ASI_DCU_CONTROL_REG),
1608 "i" (DCU_IC | DCU_DC)
1612 cheetah_flush_ecache();
1613 else if (flush_line)
1614 cheetah_flush_ecache_line(afar);
1617 /* Re-enable error reporting */
1618 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1619 "or %%g1, %1, %%g1\n\t"
1620 "stxa %%g1, [%%g0] %0\n\t"
1623 : "i" (ASI_ESTATE_ERROR_EN),
1624 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1627 /* Decide if we can continue after handling this trap and
1628 * logging the error.
1631 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1634 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1635 * error was logged while we had error reporting traps disabled.
1637 if (cheetah_recheck_errors(&local_snapshot)) {
1638 unsigned long new_afsr = local_snapshot.afsr;
1640 /* If we got a new asynchronous error, die... */
1641 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1642 CHAFSR_WDU | CHAFSR_CPU |
1643 CHAFSR_IVU | CHAFSR_UE |
1644 CHAFSR_BERR | CHAFSR_TO))
1649 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1651 /* "Recoverable" here means we try to yank the page from ever
1652 * being newly used again. This depends upon a few things:
1653 * 1) Must be main memory, and AFAR must be valid.
1654 * 2) If we trapped from user, OK.
1655 * 3) Else, if we trapped from kernel we must find exception
1656 * table entry (ie. we have to have been accessing user
1659 * If AFAR is not in main memory, or we trapped from kernel
1660 * and cannot find an exception table entry, it is unacceptable
1661 * to try and continue.
1663 if (recoverable && is_memory) {
1664 if ((regs->tstate & TSTATE_PRIV) == 0UL) {
1665 /* OK, usermode access. */
1668 const struct exception_table_entry *entry;
1670 entry = search_exception_tables(regs->tpc);
1672 /* OK, kernel access to userspace. */
1676 /* BAD, privileged state is corrupted. */
1681 if (pfn_valid(afar >> PAGE_SHIFT))
1682 get_page(pfn_to_page(afar >> PAGE_SHIFT));
1686 /* Only perform fixup if we still have a
1687 * recoverable condition.
1690 regs->tpc = entry->fixup;
1691 regs->tnpc = regs->tpc + 4;
1700 panic("Irrecoverable deferred error trap.\n");
1703 /* Handle a D/I cache parity error trap. TYPE is encoded as:
1705 * Bit0: 0=dcache,1=icache
1706 * Bit1: 0=recoverable,1=unrecoverable
1708 * The hardware has disabled both the I-cache and D-cache in
1709 * the %dcr register.
1711 void cheetah_plus_parity_error(int type, struct pt_regs *regs)
1714 __cheetah_flush_icache();
1716 cheetah_plus_zap_dcache_parity();
1717 cheetah_flush_dcache();
1719 /* Re-enable I-cache/D-cache */
1720 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1721 "or %%g1, %1, %%g1\n\t"
1722 "stxa %%g1, [%%g0] %0\n\t"
1725 : "i" (ASI_DCU_CONTROL_REG),
1726 "i" (DCU_DC | DCU_IC)
1730 printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1732 (type & 0x1) ? 'I' : 'D',
1734 printk(KERN_EMERG "TPC<%pS>\n", (void *) regs->tpc);
1735 panic("Irrecoverable Cheetah+ parity error.");
1738 printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1740 (type & 0x1) ? 'I' : 'D',
1742 printk(KERN_WARNING "TPC<%pS>\n", (void *) regs->tpc);
1745 struct sun4v_error_entry {
1750 #define SUN4V_ERR_TYPE_UNDEFINED 0
1751 #define SUN4V_ERR_TYPE_UNCORRECTED_RES 1
1752 #define SUN4V_ERR_TYPE_PRECISE_NONRES 2
1753 #define SUN4V_ERR_TYPE_DEFERRED_NONRES 3
1754 #define SUN4V_ERR_TYPE_WARNING_RES 4
1757 #define SUN4V_ERR_ATTRS_PROCESSOR 0x00000001
1758 #define SUN4V_ERR_ATTRS_MEMORY 0x00000002
1759 #define SUN4V_ERR_ATTRS_PIO 0x00000004
1760 #define SUN4V_ERR_ATTRS_INT_REGISTERS 0x00000008
1761 #define SUN4V_ERR_ATTRS_FPU_REGISTERS 0x00000010
1762 #define SUN4V_ERR_ATTRS_USER_MODE 0x01000000
1763 #define SUN4V_ERR_ATTRS_PRIV_MODE 0x02000000
1764 #define SUN4V_ERR_ATTRS_RES_QUEUE_FULL 0x80000000
1772 static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1773 static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1775 static const char *sun4v_err_type_to_str(u32 type)
1778 case SUN4V_ERR_TYPE_UNDEFINED:
1780 case SUN4V_ERR_TYPE_UNCORRECTED_RES:
1781 return "uncorrected resumable";
1782 case SUN4V_ERR_TYPE_PRECISE_NONRES:
1783 return "precise nonresumable";
1784 case SUN4V_ERR_TYPE_DEFERRED_NONRES:
1785 return "deferred nonresumable";
1786 case SUN4V_ERR_TYPE_WARNING_RES:
1787 return "warning resumable";
1793 static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt)
1797 printk("%s: Reporting on cpu %d\n", pfx, cpu);
1798 printk("%s: err_handle[%llx] err_stick[%llx] err_type[%08x:%s]\n",
1800 ent->err_handle, ent->err_stick,
1802 sun4v_err_type_to_str(ent->err_type));
1803 printk("%s: err_attrs[%08x:%s %s %s %s %s %s %s %s]\n",
1806 ((ent->err_attrs & SUN4V_ERR_ATTRS_PROCESSOR) ?
1808 ((ent->err_attrs & SUN4V_ERR_ATTRS_MEMORY) ?
1810 ((ent->err_attrs & SUN4V_ERR_ATTRS_PIO) ?
1812 ((ent->err_attrs & SUN4V_ERR_ATTRS_INT_REGISTERS) ?
1813 "integer-regs" : ""),
1814 ((ent->err_attrs & SUN4V_ERR_ATTRS_FPU_REGISTERS) ?
1816 ((ent->err_attrs & SUN4V_ERR_ATTRS_USER_MODE) ?
1818 ((ent->err_attrs & SUN4V_ERR_ATTRS_PRIV_MODE) ?
1820 ((ent->err_attrs & SUN4V_ERR_ATTRS_RES_QUEUE_FULL) ?
1821 "queue-full" : ""));
1822 printk("%s: err_raddr[%016llx] err_size[%u] err_cpu[%u]\n",
1824 ent->err_raddr, ent->err_size, ent->err_cpu);
1828 if ((cnt = atomic_read(ocnt)) != 0) {
1829 atomic_set(ocnt, 0);
1831 printk("%s: Queue overflowed %d times.\n",
1836 /* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate.
1837 * Log the event and clear the first word of the entry.
1839 void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)
1841 struct sun4v_error_entry *ent, local_copy;
1842 struct trap_per_cpu *tb;
1843 unsigned long paddr;
1848 tb = &trap_block[cpu];
1849 paddr = tb->resum_kernel_buf_pa + offset;
1852 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1854 /* We have a local copy now, so release the entry. */
1855 ent->err_handle = 0;
1860 if (ent->err_type == SUN4V_ERR_TYPE_WARNING_RES) {
1861 /* If err_type is 0x4, it's a powerdown request. Do
1862 * not do the usual resumable error log because that
1863 * makes it look like some abnormal error.
1865 printk(KERN_INFO "Power down request...\n");
1866 kill_cad_pid(SIGINT, 1);
1870 sun4v_log_error(regs, &local_copy, cpu,
1871 KERN_ERR "RESUMABLE ERROR",
1872 &sun4v_resum_oflow_cnt);
1875 /* If we try to printk() we'll probably make matters worse, by trying
1876 * to retake locks this cpu already holds or causing more errors. So
1877 * just bump a counter, and we'll report these counter bumps above.
1879 void sun4v_resum_overflow(struct pt_regs *regs)
1881 atomic_inc(&sun4v_resum_oflow_cnt);
1884 /* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate.
1885 * Log the event, clear the first word of the entry, and die.
1887 void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)
1889 struct sun4v_error_entry *ent, local_copy;
1890 struct trap_per_cpu *tb;
1891 unsigned long paddr;
1896 tb = &trap_block[cpu];
1897 paddr = tb->nonresum_kernel_buf_pa + offset;
1900 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1902 /* We have a local copy now, so release the entry. */
1903 ent->err_handle = 0;
1909 /* Check for the special PCI poke sequence. */
1910 if (pci_poke_in_progress && pci_poke_cpu == cpu) {
1911 pci_poke_faulted = 1;
1913 regs->tnpc = regs->tpc + 4;
1918 sun4v_log_error(regs, &local_copy, cpu,
1919 KERN_EMERG "NON-RESUMABLE ERROR",
1920 &sun4v_nonresum_oflow_cnt);
1922 panic("Non-resumable error.");
1925 /* If we try to printk() we'll probably make matters worse, by trying
1926 * to retake locks this cpu already holds or causing more errors. So
1927 * just bump a counter, and we'll report these counter bumps above.
1929 void sun4v_nonresum_overflow(struct pt_regs *regs)
1931 /* XXX Actually even this can make not that much sense. Perhaps
1932 * XXX we should just pull the plug and panic directly from here?
1934 atomic_inc(&sun4v_nonresum_oflow_cnt);
1937 unsigned long sun4v_err_itlb_vaddr;
1938 unsigned long sun4v_err_itlb_ctx;
1939 unsigned long sun4v_err_itlb_pte;
1940 unsigned long sun4v_err_itlb_error;
1942 void sun4v_itlb_error_report(struct pt_regs *regs, int tl)
1945 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1947 printk(KERN_EMERG "SUN4V-ITLB: Error at TPC[%lx], tl %d\n",
1949 printk(KERN_EMERG "SUN4V-ITLB: TPC<%pS>\n", (void *) regs->tpc);
1950 printk(KERN_EMERG "SUN4V-ITLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
1951 printk(KERN_EMERG "SUN4V-ITLB: O7<%pS>\n",
1952 (void *) regs->u_regs[UREG_I7]);
1953 printk(KERN_EMERG "SUN4V-ITLB: vaddr[%lx] ctx[%lx] "
1954 "pte[%lx] error[%lx]\n",
1955 sun4v_err_itlb_vaddr, sun4v_err_itlb_ctx,
1956 sun4v_err_itlb_pte, sun4v_err_itlb_error);
1961 unsigned long sun4v_err_dtlb_vaddr;
1962 unsigned long sun4v_err_dtlb_ctx;
1963 unsigned long sun4v_err_dtlb_pte;
1964 unsigned long sun4v_err_dtlb_error;
1966 void sun4v_dtlb_error_report(struct pt_regs *regs, int tl)
1969 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1971 printk(KERN_EMERG "SUN4V-DTLB: Error at TPC[%lx], tl %d\n",
1973 printk(KERN_EMERG "SUN4V-DTLB: TPC<%pS>\n", (void *) regs->tpc);
1974 printk(KERN_EMERG "SUN4V-DTLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
1975 printk(KERN_EMERG "SUN4V-DTLB: O7<%pS>\n",
1976 (void *) regs->u_regs[UREG_I7]);
1977 printk(KERN_EMERG "SUN4V-DTLB: vaddr[%lx] ctx[%lx] "
1978 "pte[%lx] error[%lx]\n",
1979 sun4v_err_dtlb_vaddr, sun4v_err_dtlb_ctx,
1980 sun4v_err_dtlb_pte, sun4v_err_dtlb_error);
1985 void hypervisor_tlbop_error(unsigned long err, unsigned long op)
1987 printk(KERN_CRIT "SUN4V: TLB hv call error %lu for op %lu\n",
1991 void hypervisor_tlbop_error_xcall(unsigned long err, unsigned long op)
1993 printk(KERN_CRIT "SUN4V: XCALL TLB hv call error %lu for op %lu\n",
1997 void do_fpe_common(struct pt_regs *regs)
1999 if (regs->tstate & TSTATE_PRIV) {
2000 regs->tpc = regs->tnpc;
2003 unsigned long fsr = current_thread_info()->xfsr[0];
2006 if (test_thread_flag(TIF_32BIT)) {
2007 regs->tpc &= 0xffffffff;
2008 regs->tnpc &= 0xffffffff;
2010 info.si_signo = SIGFPE;
2012 info.si_addr = (void __user *)regs->tpc;
2014 info.si_code = __SI_FAULT;
2015 if ((fsr & 0x1c000) == (1 << 14)) {
2017 info.si_code = FPE_FLTINV;
2018 else if (fsr & 0x08)
2019 info.si_code = FPE_FLTOVF;
2020 else if (fsr & 0x04)
2021 info.si_code = FPE_FLTUND;
2022 else if (fsr & 0x02)
2023 info.si_code = FPE_FLTDIV;
2024 else if (fsr & 0x01)
2025 info.si_code = FPE_FLTRES;
2027 force_sig_info(SIGFPE, &info, current);
2031 void do_fpieee(struct pt_regs *regs)
2033 if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
2034 0, 0x24, SIGFPE) == NOTIFY_STOP)
2037 do_fpe_common(regs);
2040 extern int do_mathemu(struct pt_regs *, struct fpustate *);
2042 void do_fpother(struct pt_regs *regs)
2044 struct fpustate *f = FPUSTATE;
2047 if (notify_die(DIE_TRAP, "fpu exception other", regs,
2048 0, 0x25, SIGFPE) == NOTIFY_STOP)
2051 switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
2052 case (2 << 14): /* unfinished_FPop */
2053 case (3 << 14): /* unimplemented_FPop */
2054 ret = do_mathemu(regs, f);
2059 do_fpe_common(regs);
2062 void do_tof(struct pt_regs *regs)
2066 if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
2067 0, 0x26, SIGEMT) == NOTIFY_STOP)
2070 if (regs->tstate & TSTATE_PRIV)
2071 die_if_kernel("Penguin overflow trap from kernel mode", regs);
2072 if (test_thread_flag(TIF_32BIT)) {
2073 regs->tpc &= 0xffffffff;
2074 regs->tnpc &= 0xffffffff;
2076 info.si_signo = SIGEMT;
2078 info.si_code = EMT_TAGOVF;
2079 info.si_addr = (void __user *)regs->tpc;
2081 force_sig_info(SIGEMT, &info, current);
2084 void do_div0(struct pt_regs *regs)
2088 if (notify_die(DIE_TRAP, "integer division by zero", regs,
2089 0, 0x28, SIGFPE) == NOTIFY_STOP)
2092 if (regs->tstate & TSTATE_PRIV)
2093 die_if_kernel("TL0: Kernel divide by zero.", regs);
2094 if (test_thread_flag(TIF_32BIT)) {
2095 regs->tpc &= 0xffffffff;
2096 regs->tnpc &= 0xffffffff;
2098 info.si_signo = SIGFPE;
2100 info.si_code = FPE_INTDIV;
2101 info.si_addr = (void __user *)regs->tpc;
2103 force_sig_info(SIGFPE, &info, current);
2106 static void instruction_dump(unsigned int *pc)
2110 if ((((unsigned long) pc) & 3))
2113 printk("Instruction DUMP:");
2114 for (i = -3; i < 6; i++)
2115 printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
2119 static void user_instruction_dump(unsigned int __user *pc)
2122 unsigned int buf[9];
2124 if ((((unsigned long) pc) & 3))
2127 if (copy_from_user(buf, pc - 3, sizeof(buf)))
2130 printk("Instruction DUMP:");
2131 for (i = 0; i < 9; i++)
2132 printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
2136 void show_stack(struct task_struct *tsk, unsigned long *_ksp)
2138 unsigned long fp, thread_base, ksp;
2139 struct thread_info *tp;
2142 ksp = (unsigned long) _ksp;
2145 tp = task_thread_info(tsk);
2148 asm("mov %%fp, %0" : "=r" (ksp));
2152 if (tp == current_thread_info())
2155 fp = ksp + STACK_BIAS;
2156 thread_base = (unsigned long) tp;
2158 printk("Call Trace:\n");
2160 struct sparc_stackf *sf;
2161 struct pt_regs *regs;
2164 if (!kstack_valid(tp, fp))
2166 sf = (struct sparc_stackf *) fp;
2167 regs = (struct pt_regs *) (sf + 1);
2169 if (kstack_is_trap_frame(tp, regs)) {
2170 if (!(regs->tstate & TSTATE_PRIV))
2173 fp = regs->u_regs[UREG_I6] + STACK_BIAS;
2175 pc = sf->callers_pc;
2176 fp = (unsigned long)sf->fp + STACK_BIAS;
2179 printk(" [%016lx] %pS\n", pc, (void *) pc);
2180 } while (++count < 16);
2183 void dump_stack(void)
2185 show_stack(current, NULL);
2188 EXPORT_SYMBOL(dump_stack);
2190 static inline int is_kernel_stack(struct task_struct *task,
2191 struct reg_window *rw)
2193 unsigned long rw_addr = (unsigned long) rw;
2194 unsigned long thread_base, thread_end;
2196 if (rw_addr < PAGE_OFFSET) {
2197 if (task != &init_task)
2201 thread_base = (unsigned long) task_stack_page(task);
2202 thread_end = thread_base + sizeof(union thread_union);
2203 if (rw_addr >= thread_base &&
2204 rw_addr < thread_end &&
2211 static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
2213 unsigned long fp = rw->ins[6];
2218 return (struct reg_window *) (fp + STACK_BIAS);
2221 void die_if_kernel(char *str, struct pt_regs *regs)
2223 static int die_counter;
2226 /* Amuse the user. */
2229 " \"@'/ .. \\`@\"\n"
2233 printk("%s(%d): %s [#%d]\n", current->comm, task_pid_nr(current), str, ++die_counter);
2234 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
2235 __asm__ __volatile__("flushw");
2237 add_taint(TAINT_DIE);
2238 if (regs->tstate & TSTATE_PRIV) {
2239 struct reg_window *rw = (struct reg_window *)
2240 (regs->u_regs[UREG_FP] + STACK_BIAS);
2242 /* Stop the back trace when we hit userland or we
2243 * find some badly aligned kernel stack.
2247 is_kernel_stack(current, rw)) {
2248 printk("Caller[%016lx]: %pS\n", rw->ins[7],
2249 (void *) rw->ins[7]);
2251 rw = kernel_stack_up(rw);
2253 instruction_dump ((unsigned int *) regs->tpc);
2255 if (test_thread_flag(TIF_32BIT)) {
2256 regs->tpc &= 0xffffffff;
2257 regs->tnpc &= 0xffffffff;
2259 user_instruction_dump ((unsigned int __user *) regs->tpc);
2261 if (regs->tstate & TSTATE_PRIV)
2265 EXPORT_SYMBOL(die_if_kernel);
2267 #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2268 #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19))
2270 extern int handle_popc(u32 insn, struct pt_regs *regs);
2271 extern int handle_ldf_stq(u32 insn, struct pt_regs *regs);
2273 void do_illegal_instruction(struct pt_regs *regs)
2275 unsigned long pc = regs->tpc;
2276 unsigned long tstate = regs->tstate;
2280 if (notify_die(DIE_TRAP, "illegal instruction", regs,
2281 0, 0x10, SIGILL) == NOTIFY_STOP)
2284 if (tstate & TSTATE_PRIV)
2285 die_if_kernel("Kernel illegal instruction", regs);
2286 if (test_thread_flag(TIF_32BIT))
2288 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
2289 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
2290 if (handle_popc(insn, regs))
2292 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
2293 if (handle_ldf_stq(insn, regs))
2295 } else if (tlb_type == hypervisor) {
2296 if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) {
2297 if (!vis_emul(regs, insn))
2300 struct fpustate *f = FPUSTATE;
2302 /* XXX maybe verify XFSR bits like
2303 * XXX do_fpother() does?
2305 if (do_mathemu(regs, f))
2310 info.si_signo = SIGILL;
2312 info.si_code = ILL_ILLOPC;
2313 info.si_addr = (void __user *)pc;
2315 force_sig_info(SIGILL, &info, current);
2318 extern void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn);
2320 void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
2324 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2325 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2328 if (regs->tstate & TSTATE_PRIV) {
2329 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2332 info.si_signo = SIGBUS;
2334 info.si_code = BUS_ADRALN;
2335 info.si_addr = (void __user *)sfar;
2337 force_sig_info(SIGBUS, &info, current);
2340 void sun4v_do_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
2344 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2345 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2348 if (regs->tstate & TSTATE_PRIV) {
2349 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2352 info.si_signo = SIGBUS;
2354 info.si_code = BUS_ADRALN;
2355 info.si_addr = (void __user *) addr;
2357 force_sig_info(SIGBUS, &info, current);
2360 void do_privop(struct pt_regs *regs)
2364 if (notify_die(DIE_TRAP, "privileged operation", regs,
2365 0, 0x11, SIGILL) == NOTIFY_STOP)
2368 if (test_thread_flag(TIF_32BIT)) {
2369 regs->tpc &= 0xffffffff;
2370 regs->tnpc &= 0xffffffff;
2372 info.si_signo = SIGILL;
2374 info.si_code = ILL_PRVOPC;
2375 info.si_addr = (void __user *)regs->tpc;
2377 force_sig_info(SIGILL, &info, current);
2380 void do_privact(struct pt_regs *regs)
2385 /* Trap level 1 stuff or other traps we should never see... */
2386 void do_cee(struct pt_regs *regs)
2388 die_if_kernel("TL0: Cache Error Exception", regs);
2391 void do_cee_tl1(struct pt_regs *regs)
2393 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2394 die_if_kernel("TL1: Cache Error Exception", regs);
2397 void do_dae_tl1(struct pt_regs *regs)
2399 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2400 die_if_kernel("TL1: Data Access Exception", regs);
2403 void do_iae_tl1(struct pt_regs *regs)
2405 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2406 die_if_kernel("TL1: Instruction Access Exception", regs);
2409 void do_div0_tl1(struct pt_regs *regs)
2411 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2412 die_if_kernel("TL1: DIV0 Exception", regs);
2415 void do_fpdis_tl1(struct pt_regs *regs)
2417 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2418 die_if_kernel("TL1: FPU Disabled", regs);
2421 void do_fpieee_tl1(struct pt_regs *regs)
2423 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2424 die_if_kernel("TL1: FPU IEEE Exception", regs);
2427 void do_fpother_tl1(struct pt_regs *regs)
2429 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2430 die_if_kernel("TL1: FPU Other Exception", regs);
2433 void do_ill_tl1(struct pt_regs *regs)
2435 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2436 die_if_kernel("TL1: Illegal Instruction Exception", regs);
2439 void do_irq_tl1(struct pt_regs *regs)
2441 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2442 die_if_kernel("TL1: IRQ Exception", regs);
2445 void do_lddfmna_tl1(struct pt_regs *regs)
2447 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2448 die_if_kernel("TL1: LDDF Exception", regs);
2451 void do_stdfmna_tl1(struct pt_regs *regs)
2453 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2454 die_if_kernel("TL1: STDF Exception", regs);
2457 void do_paw(struct pt_regs *regs)
2459 die_if_kernel("TL0: Phys Watchpoint Exception", regs);
2462 void do_paw_tl1(struct pt_regs *regs)
2464 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2465 die_if_kernel("TL1: Phys Watchpoint Exception", regs);
2468 void do_vaw(struct pt_regs *regs)
2470 die_if_kernel("TL0: Virt Watchpoint Exception", regs);
2473 void do_vaw_tl1(struct pt_regs *regs)
2475 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2476 die_if_kernel("TL1: Virt Watchpoint Exception", regs);
2479 void do_tof_tl1(struct pt_regs *regs)
2481 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2482 die_if_kernel("TL1: Tag Overflow Exception", regs);
2485 void do_getpsr(struct pt_regs *regs)
2487 regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
2488 regs->tpc = regs->tnpc;
2490 if (test_thread_flag(TIF_32BIT)) {
2491 regs->tpc &= 0xffffffff;
2492 regs->tnpc &= 0xffffffff;
2496 struct trap_per_cpu trap_block[NR_CPUS];
2498 /* This can get invoked before sched_init() so play it super safe
2499 * and use hard_smp_processor_id().
2501 void notrace init_cur_cpu_trap(struct thread_info *t)
2503 int cpu = hard_smp_processor_id();
2504 struct trap_per_cpu *p = &trap_block[cpu];
2510 extern void thread_info_offsets_are_bolixed_dave(void);
2511 extern void trap_per_cpu_offsets_are_bolixed_dave(void);
2512 extern void tsb_config_offsets_are_bolixed_dave(void);
2514 /* Only invoked on boot processor. */
2515 void __init trap_init(void)
2517 /* Compile time sanity check. */
2518 if (TI_TASK != offsetof(struct thread_info, task) ||
2519 TI_FLAGS != offsetof(struct thread_info, flags) ||
2520 TI_CPU != offsetof(struct thread_info, cpu) ||
2521 TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
2522 TI_KSP != offsetof(struct thread_info, ksp) ||
2523 TI_FAULT_ADDR != offsetof(struct thread_info, fault_address) ||
2524 TI_KREGS != offsetof(struct thread_info, kregs) ||
2525 TI_UTRAPS != offsetof(struct thread_info, utraps) ||
2526 TI_EXEC_DOMAIN != offsetof(struct thread_info, exec_domain) ||
2527 TI_REG_WINDOW != offsetof(struct thread_info, reg_window) ||
2528 TI_RWIN_SPTRS != offsetof(struct thread_info, rwbuf_stkptrs) ||
2529 TI_GSR != offsetof(struct thread_info, gsr) ||
2530 TI_XFSR != offsetof(struct thread_info, xfsr) ||
2531 TI_USER_CNTD0 != offsetof(struct thread_info, user_cntd0) ||
2532 TI_USER_CNTD1 != offsetof(struct thread_info, user_cntd1) ||
2533 TI_KERN_CNTD0 != offsetof(struct thread_info, kernel_cntd0) ||
2534 TI_KERN_CNTD1 != offsetof(struct thread_info, kernel_cntd1) ||
2535 TI_PCR != offsetof(struct thread_info, pcr_reg) ||
2536 TI_PRE_COUNT != offsetof(struct thread_info, preempt_count) ||
2537 TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
2538 TI_SYS_NOERROR != offsetof(struct thread_info, syscall_noerror) ||
2539 TI_RESTART_BLOCK != offsetof(struct thread_info, restart_block) ||
2540 TI_KUNA_REGS != offsetof(struct thread_info, kern_una_regs) ||
2541 TI_KUNA_INSN != offsetof(struct thread_info, kern_una_insn) ||
2542 TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2543 (TI_FPREGS & (64 - 1)))
2544 thread_info_offsets_are_bolixed_dave();
2546 if (TRAP_PER_CPU_THREAD != offsetof(struct trap_per_cpu, thread) ||
2547 (TRAP_PER_CPU_PGD_PADDR !=
2548 offsetof(struct trap_per_cpu, pgd_paddr)) ||
2549 (TRAP_PER_CPU_CPU_MONDO_PA !=
2550 offsetof(struct trap_per_cpu, cpu_mondo_pa)) ||
2551 (TRAP_PER_CPU_DEV_MONDO_PA !=
2552 offsetof(struct trap_per_cpu, dev_mondo_pa)) ||
2553 (TRAP_PER_CPU_RESUM_MONDO_PA !=
2554 offsetof(struct trap_per_cpu, resum_mondo_pa)) ||
2555 (TRAP_PER_CPU_RESUM_KBUF_PA !=
2556 offsetof(struct trap_per_cpu, resum_kernel_buf_pa)) ||
2557 (TRAP_PER_CPU_NONRESUM_MONDO_PA !=
2558 offsetof(struct trap_per_cpu, nonresum_mondo_pa)) ||
2559 (TRAP_PER_CPU_NONRESUM_KBUF_PA !=
2560 offsetof(struct trap_per_cpu, nonresum_kernel_buf_pa)) ||
2561 (TRAP_PER_CPU_FAULT_INFO !=
2562 offsetof(struct trap_per_cpu, fault_info)) ||
2563 (TRAP_PER_CPU_CPU_MONDO_BLOCK_PA !=
2564 offsetof(struct trap_per_cpu, cpu_mondo_block_pa)) ||
2565 (TRAP_PER_CPU_CPU_LIST_PA !=
2566 offsetof(struct trap_per_cpu, cpu_list_pa)) ||
2567 (TRAP_PER_CPU_TSB_HUGE !=
2568 offsetof(struct trap_per_cpu, tsb_huge)) ||
2569 (TRAP_PER_CPU_TSB_HUGE_TEMP !=
2570 offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
2571 (TRAP_PER_CPU_IRQ_WORKLIST_PA !=
2572 offsetof(struct trap_per_cpu, irq_worklist_pa)) ||
2573 (TRAP_PER_CPU_CPU_MONDO_QMASK !=
2574 offsetof(struct trap_per_cpu, cpu_mondo_qmask)) ||
2575 (TRAP_PER_CPU_DEV_MONDO_QMASK !=
2576 offsetof(struct trap_per_cpu, dev_mondo_qmask)) ||
2577 (TRAP_PER_CPU_RESUM_QMASK !=
2578 offsetof(struct trap_per_cpu, resum_qmask)) ||
2579 (TRAP_PER_CPU_NONRESUM_QMASK !=
2580 offsetof(struct trap_per_cpu, nonresum_qmask)))
2581 trap_per_cpu_offsets_are_bolixed_dave();
2583 if ((TSB_CONFIG_TSB !=
2584 offsetof(struct tsb_config, tsb)) ||
2585 (TSB_CONFIG_RSS_LIMIT !=
2586 offsetof(struct tsb_config, tsb_rss_limit)) ||
2587 (TSB_CONFIG_NENTRIES !=
2588 offsetof(struct tsb_config, tsb_nentries)) ||
2589 (TSB_CONFIG_REG_VAL !=
2590 offsetof(struct tsb_config, tsb_reg_val)) ||
2591 (TSB_CONFIG_MAP_VADDR !=
2592 offsetof(struct tsb_config, tsb_map_vaddr)) ||
2593 (TSB_CONFIG_MAP_PTE !=
2594 offsetof(struct tsb_config, tsb_map_pte)))
2595 tsb_config_offsets_are_bolixed_dave();
2597 /* Attach to the address space of init_task. On SMP we
2598 * do this in smp.c:smp_callin for other cpus.
2600 atomic_inc(&init_mm.mm_count);
2601 current->active_mm = &init_mm;