arch/sparc/kernel/pci_sabre.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* pci_sabre.c: Sabre specific PCI controller support.
   3  *
   4  * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
   5  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
   6  * Copyright (C) 1999 Jakub Jelinek   (jakub@redhat.com)
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <linux/init.h>
  13 #include <linux/export.h>
  14 #include <linux/slab.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/of_device.h>
  17
  18 #include <asm/apb.h>
  19 #include <asm/iommu.h>
  20 #include <asm/irq.h>
  21 #include <asm/prom.h>
  22 #include <asm/upa.h>
  23
  24 #include "pci_impl.h"
  25 #include "iommu_common.h"
  26 #include "psycho_common.h"
  27
  28 #define DRIVER_NAME     "sabre"
  29 #define PFX             DRIVER_NAME ": "
  30
  31 /* SABRE PCI controller register offsets and definitions. */
  32 #define SABRE_UE_AFSR           0x0030UL
  33 #define  SABRE_UEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
  34 #define  SABRE_UEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
  35 #define  SABRE_UEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
  36 #define  SABRE_UEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
  37 #define  SABRE_UEAFSR_SDTE       0x0200000000000000UL   /* Secondary DMA Translation Error */
  38 #define  SABRE_UEAFSR_PDTE       0x0100000000000000UL   /* Primary DMA Translation Error */
  39 #define  SABRE_UEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
  40 #define  SABRE_UEAFSR_OFF        0x00000000e0000000UL   /* Offset (AFAR bits [5:3] */
  41 #define  SABRE_UEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
  42 #define SABRE_UECE_AFAR         0x0038UL
  43 #define SABRE_CE_AFSR           0x0040UL
  44 #define  SABRE_CEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
  45 #define  SABRE_CEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
  46 #define  SABRE_CEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
  47 #define  SABRE_CEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
  48 #define  SABRE_CEAFSR_ESYND      0x00ff000000000000UL   /* ECC Syndrome */
  49 #define  SABRE_CEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
  50 #define  SABRE_CEAFSR_OFF        0x00000000e0000000UL   /* Offset */
  51 #define  SABRE_CEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
  52 #define SABRE_UECE_AFAR_ALIAS   0x0048UL        /* Aliases to 0x0038 */
  53 #define SABRE_IOMMU_CONTROL     0x0200UL
  54 #define  SABRE_IOMMUCTRL_ERRSTS  0x0000000006000000UL   /* Error status bits */
  55 #define  SABRE_IOMMUCTRL_ERR     0x0000000001000000UL   /* Error present in IOTLB */
  56 #define  SABRE_IOMMUCTRL_LCKEN   0x0000000000800000UL   /* IOTLB lock enable */
  57 #define  SABRE_IOMMUCTRL_LCKPTR  0x0000000000780000UL   /* IOTLB lock pointer */
  58 #define  SABRE_IOMMUCTRL_TSBSZ   0x0000000000070000UL   /* TSB Size */
  59 #define  SABRE_IOMMU_TSBSZ_1K   0x0000000000000000
  60 #define  SABRE_IOMMU_TSBSZ_2K   0x0000000000010000
  61 #define  SABRE_IOMMU_TSBSZ_4K   0x0000000000020000
  62 #define  SABRE_IOMMU_TSBSZ_8K   0x0000000000030000
  63 #define  SABRE_IOMMU_TSBSZ_16K  0x0000000000040000
  64 #define  SABRE_IOMMU_TSBSZ_32K  0x0000000000050000
  65 #define  SABRE_IOMMU_TSBSZ_64K  0x0000000000060000
  66 #define  SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
  67 #define  SABRE_IOMMUCTRL_TBWSZ   0x0000000000000004UL   /* TSB assumed page size */
  68 #define  SABRE_IOMMUCTRL_DENAB   0x0000000000000002UL   /* Diagnostic Mode Enable */
  69 #define  SABRE_IOMMUCTRL_ENAB    0x0000000000000001UL   /* IOMMU Enable */
  70 #define SABRE_IOMMU_TSBBASE     0x0208UL
  71 #define SABRE_IOMMU_FLUSH       0x0210UL
  72 #define SABRE_IMAP_A_SLOT0      0x0c00UL
  73 #define SABRE_IMAP_B_SLOT0      0x0c20UL
  74 #define SABRE_IMAP_SCSI         0x1000UL
  75 #define SABRE_IMAP_ETH          0x1008UL
  76 #define SABRE_IMAP_BPP          0x1010UL
  77 #define SABRE_IMAP_AU_REC       0x1018UL
  78 #define SABRE_IMAP_AU_PLAY      0x1020UL
  79 #define SABRE_IMAP_PFAIL        0x1028UL
  80 #define SABRE_IMAP_KMS          0x1030UL
  81 #define SABRE_IMAP_FLPY         0x1038UL
  82 #define SABRE_IMAP_SHW          0x1040UL
  83 #define SABRE_IMAP_KBD          0x1048UL
  84 #define SABRE_IMAP_MS           0x1050UL
  85 #define SABRE_IMAP_SER          0x1058UL
  86 #define SABRE_IMAP_UE           0x1070UL
  87 #define SABRE_IMAP_CE           0x1078UL
  88 #define SABRE_IMAP_PCIERR       0x1080UL
  89 #define SABRE_IMAP_GFX          0x1098UL
  90 #define SABRE_IMAP_EUPA         0x10a0UL
  91 #define SABRE_ICLR_A_SLOT0      0x1400UL
  92 #define SABRE_ICLR_B_SLOT0      0x1480UL
  93 #define SABRE_ICLR_SCSI         0x1800UL
  94 #define SABRE_ICLR_ETH          0x1808UL
  95 #define SABRE_ICLR_BPP          0x1810UL
  96 #define SABRE_ICLR_AU_REC       0x1818UL
  97 #define SABRE_ICLR_AU_PLAY      0x1820UL
  98 #define SABRE_ICLR_PFAIL        0x1828UL
  99 #define SABRE_ICLR_KMS          0x1830UL
 100 #define SABRE_ICLR_FLPY         0x1838UL
 101 #define SABRE_ICLR_SHW          0x1840UL
 102 #define SABRE_ICLR_KBD          0x1848UL
 103 #define SABRE_ICLR_MS           0x1850UL
 104 #define SABRE_ICLR_SER          0x1858UL
 105 #define SABRE_ICLR_UE           0x1870UL
 106 #define SABRE_ICLR_CE           0x1878UL
 107 #define SABRE_ICLR_PCIERR       0x1880UL
 108 #define SABRE_WRSYNC            0x1c20UL
 109 #define SABRE_PCICTRL           0x2000UL
 110 #define  SABRE_PCICTRL_MRLEN     0x0000001000000000UL   /* Use MemoryReadLine for block loads/stores */
 111 #define  SABRE_PCICTRL_SERR      0x0000000400000000UL   /* Set when SERR asserted on PCI bus */
 112 #define  SABRE_PCICTRL_ARBPARK   0x0000000000200000UL   /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
 113 #define  SABRE_PCICTRL_CPUPRIO   0x0000000000100000UL   /* Ultra-IIi granted every other bus cycle */
 114 #define  SABRE_PCICTRL_ARBPRIO   0x00000000000f0000UL   /* Slot which is granted every other bus cycle */
 115 #define  SABRE_PCICTRL_ERREN     0x0000000000000100UL   /* PCI Error Interrupt Enable */
 116 #define  SABRE_PCICTRL_RTRYWE    0x0000000000000080UL   /* DMA Flow Control 0=wait-if-possible 1=retry */
 117 #define  SABRE_PCICTRL_AEN       0x000000000000000fUL   /* Slot PCI arbitration enables */
 118 #define SABRE_PIOAFSR           0x2010UL
 119 #define  SABRE_PIOAFSR_PMA       0x8000000000000000UL   /* Primary Master Abort */
 120 #define  SABRE_PIOAFSR_PTA       0x4000000000000000UL   /* Primary Target Abort */
 121 #define  SABRE_PIOAFSR_PRTRY     0x2000000000000000UL   /* Primary Excessive Retries */
 122 #define  SABRE_PIOAFSR_PPERR     0x1000000000000000UL   /* Primary Parity Error */
 123 #define  SABRE_PIOAFSR_SMA       0x0800000000000000UL   /* Secondary Master Abort */
 124 #define  SABRE_PIOAFSR_STA       0x0400000000000000UL   /* Secondary Target Abort */
 125 #define  SABRE_PIOAFSR_SRTRY     0x0200000000000000UL   /* Secondary Excessive Retries */
 126 #define  SABRE_PIOAFSR_SPERR     0x0100000000000000UL   /* Secondary Parity Error */
 127 #define  SABRE_PIOAFSR_BMSK      0x0000ffff00000000UL   /* Byte Mask */
 128 #define  SABRE_PIOAFSR_BLK       0x0000000080000000UL   /* Was Block Operation */
 129 #define SABRE_PIOAFAR           0x2018UL
 130 #define SABRE_PCIDIAG           0x2020UL
 131 #define  SABRE_PCIDIAG_DRTRY     0x0000000000000040UL   /* Disable PIO Retry Limit */
 132 #define  SABRE_PCIDIAG_IPAPAR    0x0000000000000008UL   /* Invert PIO Address Parity */
 133 #define  SABRE_PCIDIAG_IPDPAR    0x0000000000000004UL   /* Invert PIO Data Parity */
 134 #define  SABRE_PCIDIAG_IDDPAR    0x0000000000000002UL   /* Invert DMA Data Parity */
 135 #define  SABRE_PCIDIAG_ELPBK     0x0000000000000001UL   /* Loopback Enable - not supported */
 136 #define SABRE_PCITASR           0x2028UL
 137 #define  SABRE_PCITASR_EF        0x0000000000000080UL   /* Respond to 0xe0000000-0xffffffff */
 138 #define  SABRE_PCITASR_CD        0x0000000000000040UL   /* Respond to 0xc0000000-0xdfffffff */
 139 #define  SABRE_PCITASR_AB        0x0000000000000020UL   /* Respond to 0xa0000000-0xbfffffff */
 140 #define  SABRE_PCITASR_89        0x0000000000000010UL   /* Respond to 0x80000000-0x9fffffff */
 141 #define  SABRE_PCITASR_67        0x0000000000000008UL   /* Respond to 0x60000000-0x7fffffff */
 142 #define  SABRE_PCITASR_45        0x0000000000000004UL   /* Respond to 0x40000000-0x5fffffff */
 143 #define  SABRE_PCITASR_23        0x0000000000000002UL   /* Respond to 0x20000000-0x3fffffff */
 144 #define  SABRE_PCITASR_01        0x0000000000000001UL   /* Respond to 0x00000000-0x1fffffff */
 145 #define SABRE_PIOBUF_DIAG       0x5000UL
 146 #define SABRE_DMABUF_DIAGLO     0x5100UL
 147 #define SABRE_DMABUF_DIAGHI     0x51c0UL
 148 #define SABRE_IMAP_GFX_ALIAS    0x6000UL        /* Aliases to 0x1098 */
 149 #define SABRE_IMAP_EUPA_ALIAS   0x8000UL        /* Aliases to 0x10a0 */
 150 #define SABRE_IOMMU_VADIAG      0xa400UL
 151 #define SABRE_IOMMU_TCDIAG      0xa408UL
 152 #define SABRE_IOMMU_TAG         0xa580UL
 153 #define  SABRE_IOMMUTAG_ERRSTS   0x0000000001800000UL   /* Error status bits */
 154 #define  SABRE_IOMMUTAG_ERR      0x0000000000400000UL   /* Error present */
 155 #define  SABRE_IOMMUTAG_WRITE    0x0000000000200000UL   /* Page is writable */
 156 #define  SABRE_IOMMUTAG_STREAM   0x0000000000100000UL   /* Streamable bit - unused */
 157 #define  SABRE_IOMMUTAG_SIZE     0x0000000000080000UL   /* 0=8k 1=16k */
 158 #define  SABRE_IOMMUTAG_VPN      0x000000000007ffffUL   /* Virtual Page Number [31:13] */
 159 #define SABRE_IOMMU_DATA        0xa600UL
 160 #define SABRE_IOMMUDATA_VALID    0x0000000040000000UL   /* Valid */
 161 #define SABRE_IOMMUDATA_USED     0x0000000020000000UL   /* Used (for LRU algorithm) */
 162 #define SABRE_IOMMUDATA_CACHE    0x0000000010000000UL   /* Cacheable */
 163 #define SABRE_IOMMUDATA_PPN      0x00000000001fffffUL   /* Physical Page Number [33:13] */
 164 #define SABRE_PCI_IRQSTATE      0xa800UL
 165 #define SABRE_OBIO_IRQSTATE     0xa808UL
 166 #define SABRE_FFBCFG            0xf000UL
 167 #define  SABRE_FFBCFG_SPRQS      0x000000000f000000     /* Slave P_RQST queue size */
 168 #define  SABRE_FFBCFG_ONEREAD    0x0000000000004000     /* Slave supports one outstanding read */
 169 #define SABRE_MCCTRL0           0xf010UL
 170 #define  SABRE_MCCTRL0_RENAB     0x0000000080000000     /* Refresh Enable */
 171 #define  SABRE_MCCTRL0_EENAB     0x0000000010000000     /* Enable all ECC functions */
 172 #define  SABRE_MCCTRL0_11BIT     0x0000000000001000     /* Enable 11-bit column addressing */
 173 #define  SABRE_MCCTRL0_DPP       0x0000000000000f00     /* DIMM Pair Present Bits */
 174 #define  SABRE_MCCTRL0_RINTVL    0x00000000000000ff     /* Refresh Interval */
 175 #define SABRE_MCCTRL1           0xf018UL
 176 #define  SABRE_MCCTRL1_AMDC      0x0000000038000000     /* Advance Memdata Clock */
 177 #define  SABRE_MCCTRL1_ARDC      0x0000000007000000     /* Advance DRAM Read Data Clock */
 178 #define  SABRE_MCCTRL1_CSR       0x0000000000e00000     /* CAS to RAS delay for CBR refresh */
 179 #define  SABRE_MCCTRL1_CASRW     0x00000000001c0000     /* CAS length for read/write */
 180 #define  SABRE_MCCTRL1_RCD       0x0000000000038000     /* RAS to CAS delay */
 181 #define  SABRE_MCCTRL1_CP        0x0000000000007000     /* CAS Precharge */
 182 #define  SABRE_MCCTRL1_RP        0x0000000000000e00     /* RAS Precharge */
 183 #define  SABRE_MCCTRL1_RAS       0x00000000000001c0     /* Length of RAS for refresh */
 184 #define  SABRE_MCCTRL1_CASRW2    0x0000000000000038     /* Must be same as CASRW */
 185 #define  SABRE_MCCTRL1_RSC       0x0000000000000007     /* RAS after CAS hold time */
 186 #define SABRE_RESETCTRL         0xf020UL
 187
 188 #define SABRE_CONFIGSPACE       0x001000000UL
 189 #define SABRE_IOSPACE           0x002000000UL
 190 #define SABRE_IOSPACE_SIZE      0x000ffffffUL
 191 #define SABRE_MEMSPACE          0x100000000UL
 192 #define SABRE_MEMSPACE_SIZE     0x07fffffffUL
 193
 194 static int hummingbird_p;
 195 static struct pci_bus *sabre_root_bus;
 196
 197 static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
 198 {
 199         struct pci_pbm_info *pbm = dev_id;
 200         unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR;
 201         unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
 202         unsigned long afsr, afar, error_bits;
 203         int reported;
 204
 205         /* Latch uncorrectable error status. */
 206         afar = upa_readq(afar_reg);
 207         afsr = upa_readq(afsr_reg);
 208
 209         /* Clear the primary/secondary error status bits. */
 210         error_bits = afsr &
 211                 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
 212                  SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
 213                  SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
 214         if (!error_bits)
 215                 return IRQ_NONE;
 216         upa_writeq(error_bits, afsr_reg);
 217
 218         /* Log the error. */
 219         printk("%s: Uncorrectable Error, primary error type[%s%s]\n",
 220                pbm->name,
 221                ((error_bits & SABRE_UEAFSR_PDRD) ?
 222                 "DMA Read" :
 223                 ((error_bits & SABRE_UEAFSR_PDWR) ?
 224                  "DMA Write" : "???")),
 225                ((error_bits & SABRE_UEAFSR_PDTE) ?
 226                 ":Translation Error" : ""));
 227         printk("%s: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
 228                pbm->name,
 229                (afsr & SABRE_UEAFSR_BMSK) >> 32UL,
 230                (afsr & SABRE_UEAFSR_OFF) >> 29UL,
 231                ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
 232         printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
 233         printk("%s: UE Secondary errors [", pbm->name);
 234         reported = 0;
 235         if (afsr & SABRE_UEAFSR_SDRD) {
 236                 reported++;
 237                 printk("(DMA Read)");
 238         }
 239         if (afsr & SABRE_UEAFSR_SDWR) {
 240                 reported++;
 241                 printk("(DMA Write)");
 242         }
 243         if (afsr & SABRE_UEAFSR_SDTE) {
 244                 reported++;
 245                 printk("(Translation Error)");
 246         }
 247         if (!reported)
 248                 printk("(none)");
 249         printk("]\n");
 250
 251         /* Interrogate IOMMU for error status. */
 252         psycho_check_iommu_error(pbm, afsr, afar, UE_ERR);
 253
 254         return IRQ_HANDLED;
 255 }
 256
 257 static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
 258 {
 259         struct pci_pbm_info *pbm = dev_id;
 260         unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR;
 261         unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
 262         unsigned long afsr, afar, error_bits;
 263         int reported;
 264
 265         /* Latch error status. */
 266         afar = upa_readq(afar_reg);
 267         afsr = upa_readq(afsr_reg);
 268
 269         /* Clear primary/secondary error status bits. */
 270         error_bits = afsr &
 271                 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
 272                  SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
 273         if (!error_bits)
 274                 return IRQ_NONE;
 275         upa_writeq(error_bits, afsr_reg);
 276
 277         /* Log the error. */
 278         printk("%s: Correctable Error, primary error type[%s]\n",
 279                pbm->name,
 280                ((error_bits & SABRE_CEAFSR_PDRD) ?
 281                 "DMA Read" :
 282                 ((error_bits & SABRE_CEAFSR_PDWR) ?
 283                  "DMA Write" : "???")));
 284
 285         /* XXX Use syndrome and afar to print out module string just like
 286          * XXX UDB CE trap handler does... -DaveM
 287          */
 288         printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
 289                "was_block(%d)\n",
 290                pbm->name,
 291                (afsr & SABRE_CEAFSR_ESYND) >> 48UL,
 292                (afsr & SABRE_CEAFSR_BMSK) >> 32UL,
 293                (afsr & SABRE_CEAFSR_OFF) >> 29UL,
 294                ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
 295         printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
 296         printk("%s: CE Secondary errors [", pbm->name);
 297         reported = 0;
 298         if (afsr & SABRE_CEAFSR_SDRD) {
 299                 reported++;
 300                 printk("(DMA Read)");
 301         }
 302         if (afsr & SABRE_CEAFSR_SDWR) {
 303                 reported++;
 304                 printk("(DMA Write)");
 305         }
 306         if (!reported)
 307                 printk("(none)");
 308         printk("]\n");
 309
 310         return IRQ_HANDLED;
 311 }
 312
 313 static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
 314 {
 315         struct device_node *dp = pbm->op->dev.of_node;
 316         struct platform_device *op;
 317         unsigned long base = pbm->controller_regs;
 318         u64 tmp;
 319         int err;
 320
 321         if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)
 322                 dp = dp->parent;
 323
 324         op = of_find_device_by_node(dp);
 325         if (!op)
 326                 return;
 327
 328         /* Sabre/Hummingbird IRQ property layout is:
 329          * 0: PCI ERR
 330          * 1: UE ERR
 331          * 2: CE ERR
 332          * 3: POWER FAIL
 333          */
 334         if (op->archdata.num_irqs < 4)
 335                 return;
 336
 337         /* We clear the error bits in the appropriate AFSR before
 338          * registering the handler so that we don't get spurious
 339          * interrupts.
 340          */
 341         upa_writeq((SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
 342                     SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
 343                     SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE),
 344                    base + SABRE_UE_AFSR);
 345
 346         err = request_irq(op->archdata.irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);
 347         if (err)
 348                 printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n",
 349                        pbm->name, err);
 350
 351         upa_writeq((SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
 352                     SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR),
 353                    base + SABRE_CE_AFSR);
 354
 355
 356         err = request_irq(op->archdata.irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);
 357         if (err)
 358                 printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n",
 359                        pbm->name, err);
 360         err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, 0,
 361                           "SABRE_PCIERR", pbm);
 362         if (err)
 363                 printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n",
 364                        pbm->name, err);
 365
 366         tmp = upa_readq(base + SABRE_PCICTRL);
 367         tmp |= SABRE_PCICTRL_ERREN;
 368         upa_writeq(tmp, base + SABRE_PCICTRL);
 369 }
 370
 371 static void apb_init(struct pci_bus *sabre_bus)
 372 {
 373         struct pci_dev *pdev;
 374
 375         list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
 376                 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
 377                     pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
 378                         u16 word16;
 379
 380                         pci_read_config_word(pdev, PCI_COMMAND, &word16);
 381                         word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
 382                                 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
 383                                 PCI_COMMAND_IO;
 384                         pci_write_config_word(pdev, PCI_COMMAND, word16);
 385
 386                         /* Status register bits are "write 1 to clear". */
 387                         pci_write_config_word(pdev, PCI_STATUS, 0xffff);
 388                         pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff);
 389
 390                         /* Use a primary/seconday latency timer value
 391                          * of 64.
 392                          */
 393                         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
 394                         pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64);
 395
 396                         /* Enable reporting/forwarding of master aborts,
 397                          * parity, and SERR.
 398                          */
 399                         pci_write_config_byte(pdev, PCI_BRIDGE_CONTROL,
 400                                               (PCI_BRIDGE_CTL_PARITY |
 401                                                PCI_BRIDGE_CTL_SERR |
 402                                                PCI_BRIDGE_CTL_MASTER_ABORT));
 403                 }
 404         }
 405 }
 406
 407 static void sabre_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
 408 {
 409         static int once;
 410
 411         /* The APB bridge speaks to the Sabre host PCI bridge
 412          * at 66Mhz, but the front side of APB runs at 33Mhz
 413          * for both segments.
 414          *
 415          * Hummingbird systems do not use APB, so they run
 416          * at 66MHZ.
 417          */
 418         if (hummingbird_p)
 419                 pbm->is_66mhz_capable = 1;
 420         else
 421                 pbm->is_66mhz_capable = 0;
 422
 423         /* This driver has not been verified to handle
 424          * multiple SABREs yet, so trap this.
 425          *
 426          * Also note that the SABRE host bridge is hardwired
 427          * to live at bus 0.
 428          */
 429         if (once != 0) {
 430                 printk(KERN_ERR PFX "Multiple controllers unsupported.\n");
 431                 return;
 432         }
 433         once++;
 434
 435         pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
 436         if (!pbm->pci_bus)
 437                 return;
 438
 439         sabre_root_bus = pbm->pci_bus;
 440
 441         apb_init(pbm->pci_bus);
 442
 443         sabre_register_error_handlers(pbm);
 444 }
 445
 446 static void sabre_pbm_init(struct pci_pbm_info *pbm,
 447                            struct platform_device *op)
 448 {
 449         psycho_pbm_init_common(pbm, op, "SABRE", PBM_CHIP_TYPE_SABRE);
 450         pbm->pci_afsr = pbm->controller_regs + SABRE_PIOAFSR;
 451         pbm->pci_afar = pbm->controller_regs + SABRE_PIOAFAR;
 452         pbm->pci_csr = pbm->controller_regs + SABRE_PCICTRL;
 453         sabre_scan_bus(pbm, &op->dev);
 454 }
 455
 456 static const struct of_device_id sabre_match[];
 457 static int sabre_probe(struct platform_device *op)
 458 {
 459         const struct of_device_id *match;
 460         const struct linux_prom64_registers *pr_regs;
 461         struct device_node *dp = op->dev.of_node;
 462         struct pci_pbm_info *pbm;
 463         u32 upa_portid, dma_mask;
 464         struct iommu *iommu;
 465         int tsbsize, err;
 466         const u32 *vdma;
 467         u64 clear_irq;
 468
 469         match = of_match_device(sabre_match, &op->dev);
 470         hummingbird_p = match && (match->data != NULL);
 471         if (!hummingbird_p) {
 472                 struct device_node *cpu_dp;
 473
 474                 /* Of course, Sun has to encode things a thousand
 475                  * different ways, inconsistently.
 476                  */
 477                 for_each_node_by_type(cpu_dp, "cpu") {
 478                         if (of_node_name_eq(cpu_dp, "SUNW,UltraSPARC-IIe"))
 479                                 hummingbird_p = 1;
 480                 }
 481         }
 482
 483         err = -ENOMEM;
 484         pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
 485         if (!pbm) {
 486                 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
 487                 goto out_err;
 488         }
 489
 490         iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
 491         if (!iommu) {
 492                 printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
 493                 goto out_free_controller;
 494         }
 495
 496         pbm->iommu = iommu;
 497
 498         upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
 499
 500         pbm->portid = upa_portid;
 501
 502         /*
 503          * Map in SABRE register set and report the presence of this SABRE.
 504          */
 505
 506         pr_regs = of_get_property(dp, "reg", NULL);
 507         err = -ENODEV;
 508         if (!pr_regs) {
 509                 printk(KERN_ERR PFX "No reg property\n");
 510                 goto out_free_iommu;
 511         }
 512
 513         /*
 514          * First REG in property is base of entire SABRE register space.
 515          */
 516         pbm->controller_regs = pr_regs[0].phys_addr;
 517
 518         /* Clear interrupts */
 519
 520         /* PCI first */
 521         for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
 522                 upa_writeq(0x0UL, pbm->controller_regs + clear_irq);
 523
 524         /* Then OBIO */
 525         for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
 526                 upa_writeq(0x0UL, pbm->controller_regs + clear_irq);
 527
 528         /* Error interrupts are enabled later after the bus scan. */
 529         upa_writeq((SABRE_PCICTRL_MRLEN   | SABRE_PCICTRL_SERR |
 530                     SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN),
 531                    pbm->controller_regs + SABRE_PCICTRL);
 532
 533         /* Now map in PCI config space for entire SABRE. */
 534         pbm->config_space = pbm->controller_regs + SABRE_CONFIGSPACE;
 535
 536         vdma = of_get_property(dp, "virtual-dma", NULL);
 537         if (!vdma) {
 538                 printk(KERN_ERR PFX "No virtual-dma property\n");
 539                 goto out_free_iommu;
 540         }
 541
 542         dma_mask = vdma[0];
 543         switch(vdma[1]) {
 544                 case 0x20000000:
 545                         dma_mask |= 0x1fffffff;
 546                         tsbsize = 64;
 547                         break;
 548                 case 0x40000000:
 549                         dma_mask |= 0x3fffffff;
 550                         tsbsize = 128;
 551                         break;
 552
 553                 case 0x80000000:
 554                         dma_mask |= 0x7fffffff;
 555                         tsbsize = 128;
 556                         break;
 557                 default:
 558                         printk(KERN_ERR PFX "Strange virtual-dma size.\n");
 559                         goto out_free_iommu;
 560         }
 561
 562         err = psycho_iommu_init(pbm, tsbsize, vdma[0], dma_mask, SABRE_WRSYNC);
 563         if (err)
 564                 goto out_free_iommu;
 565
 566         /*
 567          * Look for APB underneath.
 568          */
 569         sabre_pbm_init(pbm, op);
 570
 571         pbm->next = pci_pbm_root;
 572         pci_pbm_root = pbm;
 573
 574         dev_set_drvdata(&op->dev, pbm);
 575
 576         return 0;
 577
 578 out_free_iommu:
 579         kfree(pbm->iommu);
 580
 581 out_free_controller:
 582         kfree(pbm);
 583
 584 out_err:
 585         return err;
 586 }
 587
 588 static const struct of_device_id sabre_match[] = {
 589         {
 590                 .name = "pci",
 591                 .compatible = "pci108e,a001",
 592                 .data = (void *) 1,
 593         },
 594         {
 595                 .name = "pci",
 596                 .compatible = "pci108e,a000",
 597         },
 598         {},
 599 };
 600
 601 static struct platform_driver sabre_driver = {
 602         .driver = {
 603                 .name = DRIVER_NAME,
 604                 .of_match_table = sabre_match,
 605         },
 606         .probe          = sabre_probe,
 607 };
 608
 609 static int __init sabre_init(void)
 610 {
 611         return platform_driver_register(&sabre_driver);
 612 }
 613
 614 subsys_initcall(sabre_init);