1 // SPDX-License-Identifier: GPL-2.0
3 * 'traps.c' handles hardware traps and faults after we have saved some
6 * SuperH version: Copyright (C) 1999 Niibe Yutaka
7 * Copyright (C) 2000 Philipp Rumpf
8 * Copyright (C) 2000 David Howells
9 * Copyright (C) 2002 - 2010 Paul Mundt
11 #include <linux/kernel.h>
12 #include <linux/ptrace.h>
13 #include <linux/hardirq.h>
14 #include <linux/init.h>
15 #include <linux/spinlock.h>
16 #include <linux/kallsyms.h>
18 #include <linux/bug.h>
19 #include <linux/debug_locks.h>
20 #include <linux/kdebug.h>
21 #include <linux/limits.h>
22 #include <linux/sysfs.h>
23 #include <linux/uaccess.h>
24 #include <linux/perf_event.h>
25 #include <linux/sched/task_stack.h>
27 #include <asm/alignment.h>
29 #include <asm/kprobes.h>
30 #include <asm/traps.h>
31 #include <asm/bl_bit.h>
34 # define TRAP_RESERVED_INST 4
35 # define TRAP_ILLEGAL_SLOT_INST 6
36 # define TRAP_ADDRESS_ERROR 9
37 # ifdef CONFIG_CPU_SH2A
39 # define TRAP_FPU_ERROR 13
40 # define TRAP_DIVZERO_ERROR 17
41 # define TRAP_DIVOVF_ERROR 18
44 #define TRAP_RESERVED_INST 12
45 #define TRAP_ILLEGAL_SLOT_INST 13
48 static inline void sign_extend(unsigned int count, unsigned char *dst)
50 #ifdef __LITTLE_ENDIAN__
51 if ((count == 1) && dst[0] & 0x80) {
56 if ((count == 2) && dst[1] & 0x80) {
61 if ((count == 1) && dst[3] & 0x80) {
66 if ((count == 2) && dst[2] & 0x80) {
73 static struct mem_access user_mem_access = {
79 * handle an instruction that does an unaligned memory access by emulating the
81 * - note that PC _may not_ point to the faulting instruction
82 * (if that instruction is in a branch delay slot)
83 * - return 0 if emulation okay, -EFAULT on existential error
85 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
86 struct mem_access *ma)
88 int ret, index, count;
89 unsigned long *rm, *rn;
90 unsigned char *src, *dst;
91 unsigned char __user *srcu, *dstu;
93 index = (instruction>>8)&15; /* 0x0F00 */
94 rn = ®s->regs[index];
96 index = (instruction>>4)&15; /* 0x00F0 */
97 rm = ®s->regs[index];
99 count = 1<<(instruction&3);
102 case 1: inc_unaligned_byte_access(); break;
103 case 2: inc_unaligned_word_access(); break;
104 case 4: inc_unaligned_dword_access(); break;
105 case 8: inc_unaligned_multi_access(); break;
109 switch (instruction>>12) {
110 case 0: /* mov.[bwl] to/from memory via r0+rn */
111 if (instruction & 8) {
113 srcu = (unsigned char __user *)*rm;
114 srcu += regs->regs[0];
115 dst = (unsigned char *)rn;
116 *(unsigned long *)dst = 0;
118 #if !defined(__LITTLE_ENDIAN__)
121 if (ma->from(dst, srcu, count))
124 sign_extend(count, dst);
127 src = (unsigned char *)rm;
128 #if !defined(__LITTLE_ENDIAN__)
131 dstu = (unsigned char __user *)*rn;
132 dstu += regs->regs[0];
134 if (ma->to(dstu, src, count))
140 case 1: /* mov.l Rm,@(disp,Rn) */
141 src = (unsigned char*) rm;
142 dstu = (unsigned char __user *)*rn;
143 dstu += (instruction&0x000F)<<2;
145 if (ma->to(dstu, src, 4))
150 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
153 src = (unsigned char*) rm;
154 dstu = (unsigned char __user *)*rn;
155 #if !defined(__LITTLE_ENDIAN__)
158 if (ma->to(dstu, src, count))
163 case 5: /* mov.l @(disp,Rm),Rn */
164 srcu = (unsigned char __user *)*rm;
165 srcu += (instruction & 0x000F) << 2;
166 dst = (unsigned char *)rn;
167 *(unsigned long *)dst = 0;
169 if (ma->from(dst, srcu, 4))
174 case 6: /* mov.[bwl] from memory, possibly with post-increment */
175 srcu = (unsigned char __user *)*rm;
178 dst = (unsigned char*) rn;
179 *(unsigned long*)dst = 0;
181 #if !defined(__LITTLE_ENDIAN__)
184 if (ma->from(dst, srcu, count))
186 sign_extend(count, dst);
191 switch ((instruction&0xFF00)>>8) {
192 case 0x81: /* mov.w R0,@(disp,Rn) */
193 src = (unsigned char *) ®s->regs[0];
194 #if !defined(__LITTLE_ENDIAN__)
197 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
198 dstu += (instruction & 0x000F) << 1;
200 if (ma->to(dstu, src, 2))
205 case 0x85: /* mov.w @(disp,Rm),R0 */
206 srcu = (unsigned char __user *)*rm;
207 srcu += (instruction & 0x000F) << 1;
208 dst = (unsigned char *) ®s->regs[0];
209 *(unsigned long *)dst = 0;
211 #if !defined(__LITTLE_ENDIAN__)
214 if (ma->from(dst, srcu, 2))
222 case 9: /* mov.w @(disp,PC),Rn */
223 srcu = (unsigned char __user *)regs->pc;
225 srcu += (instruction & 0x00FF) << 1;
226 dst = (unsigned char *)rn;
227 *(unsigned long *)dst = 0;
229 #if !defined(__LITTLE_ENDIAN__)
233 if (ma->from(dst, srcu, 2))
239 case 0xd: /* mov.l @(disp,PC),Rn */
240 srcu = (unsigned char __user *)(regs->pc & ~0x3);
242 srcu += (instruction & 0x00FF) << 2;
243 dst = (unsigned char *)rn;
244 *(unsigned long *)dst = 0;
246 if (ma->from(dst, srcu, 4))
254 /* Argh. Address not only misaligned but also non-existent.
255 * Raise an EFAULT and see if it's trapped
257 die_if_no_fixup("Fault in unaligned fixup", regs, 0);
262 * emulate the instruction in the delay slot
263 * - fetches the instruction from PC+2
265 static inline int handle_delayslot(struct pt_regs *regs,
266 insn_size_t old_instruction,
267 struct mem_access *ma)
269 insn_size_t instruction;
270 void __user *addr = (void __user *)(regs->pc +
271 instruction_size(old_instruction));
273 if (copy_from_user(&instruction, addr, sizeof(instruction))) {
274 /* the instruction-fetch faulted */
279 die("delay-slot-insn faulting in handle_unaligned_delayslot",
283 return handle_unaligned_ins(instruction, regs, ma);
287 * handle an instruction that does an unaligned memory access
288 * - have to be careful of branch delay-slot instructions that fault
290 * - if the branch would be taken PC points to the branch
291 * - if the branch would not be taken, PC points to delay-slot
293 * - PC always points to delayed branch
294 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
297 /* Macros to determine offset from current PC for branch instructions */
298 /* Explicit type coercion is used to force sign extension where needed */
299 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
300 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
302 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
303 struct mem_access *ma, int expected,
304 unsigned long address)
310 * XXX: We can't handle mixed 16/32-bit instructions yet
312 if (instruction_size(instruction) != 2)
315 index = (instruction>>8)&15; /* 0x0F00 */
316 rm = regs->regs[index];
319 * Log the unexpected fixups, and then pass them on to perf.
321 * We intentionally don't report the expected cases to perf as
322 * otherwise the trapped I/O case will skew the results too much
326 unaligned_fixups_notify(current, instruction, regs);
327 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1,
332 switch (instruction&0xF000) {
334 if (instruction==0x000B) {
336 ret = handle_delayslot(regs, instruction, ma);
340 else if ((instruction&0x00FF)==0x0023) {
342 ret = handle_delayslot(regs, instruction, ma);
346 else if ((instruction&0x00FF)==0x0003) {
348 ret = handle_delayslot(regs, instruction, ma);
350 regs->pr = regs->pc + 4;
355 /* mov.[bwl] to/from memory via r0+rn */
360 case 0x1000: /* mov.l Rm,@(disp,Rn) */
363 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
367 if ((instruction&0x00FF)==0x002B) {
369 ret = handle_delayslot(regs, instruction, ma);
373 else if ((instruction&0x00FF)==0x000B) {
375 ret = handle_delayslot(regs, instruction, ma);
377 regs->pr = regs->pc + 4;
382 /* mov.[bwl] to/from memory via r0+rn */
387 case 0x5000: /* mov.l @(disp,Rm),Rn */
390 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
393 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
394 switch (instruction&0x0F00) {
395 case 0x0100: /* mov.w R0,@(disp,Rm) */
397 case 0x0500: /* mov.w @(disp,Rm),R0 */
399 case 0x0B00: /* bf lab - no delayslot*/
402 case 0x0F00: /* bf/s lab */
403 ret = handle_delayslot(regs, instruction, ma);
405 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
406 if ((regs->sr & 0x00000001) != 0)
407 regs->pc += 4; /* next after slot */
410 regs->pc += SH_PC_8BIT_OFFSET(instruction);
413 case 0x0900: /* bt lab - no delayslot */
416 case 0x0D00: /* bt/s lab */
417 ret = handle_delayslot(regs, instruction, ma);
419 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
420 if ((regs->sr & 0x00000001) == 0)
421 regs->pc += 4; /* next after slot */
424 regs->pc += SH_PC_8BIT_OFFSET(instruction);
430 case 0x9000: /* mov.w @(disp,Rm),Rn */
433 case 0xA000: /* bra label */
434 ret = handle_delayslot(regs, instruction, ma);
436 regs->pc += SH_PC_12BIT_OFFSET(instruction);
439 case 0xB000: /* bsr label */
440 ret = handle_delayslot(regs, instruction, ma);
442 regs->pr = regs->pc + 4;
443 regs->pc += SH_PC_12BIT_OFFSET(instruction);
447 case 0xD000: /* mov.l @(disp,Rm),Rn */
452 /* handle non-delay-slot instruction */
454 ret = handle_unaligned_ins(instruction, regs, ma);
456 regs->pc += instruction_size(instruction);
461 * Handle various address error exceptions:
462 * - instruction address error:
464 * PC >= 0x80000000 in user mode
465 * - data address error (read and write)
466 * misaligned data access
467 * access to >= 0x80000000 is user mode
468 * Unfortuntaly we can't distinguish between instruction address error
469 * and data address errors caused by read accesses.
471 asmlinkage void do_address_error(struct pt_regs *regs,
472 unsigned long writeaccess,
473 unsigned long address)
475 unsigned long error_code = 0;
477 insn_size_t instruction;
480 /* Intentional ifdef */
481 #ifdef CONFIG_CPU_HAS_SR_RB
482 error_code = lookup_exception_vector();
485 if (user_mode(regs)) {
486 int si_code = BUS_ADRERR;
487 unsigned int user_action;
490 inc_unaligned_user_access();
492 oldfs = force_uaccess_begin();
493 if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
494 sizeof(instruction))) {
495 force_uaccess_end(oldfs);
498 force_uaccess_end(oldfs);
500 /* shout about userspace fixups */
501 unaligned_fixups_notify(current, instruction, regs);
503 user_action = unaligned_user_action();
504 if (user_action & UM_FIXUP)
506 if (user_action & UM_SIGNAL)
510 regs->pc += instruction_size(instruction);
515 /* bad PC is not something we can fix */
517 si_code = BUS_ADRALN;
521 oldfs = force_uaccess_begin();
522 tmp = handle_unaligned_access(instruction, regs,
525 force_uaccess_end(oldfs);
530 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
531 "access (PC %lx PR %lx)\n", current->comm, regs->pc,
534 force_sig_fault(SIGBUS, si_code, (void __user *)address);
536 inc_unaligned_kernel_access();
539 die("unaligned program counter", regs, error_code);
542 if (copy_from_user(&instruction, (void __user *)(regs->pc),
543 sizeof(instruction))) {
544 /* Argh. Fault on the instruction itself.
545 This should never happen non-SMP
548 die("insn faulting in do_address_error", regs, 0);
551 unaligned_fixups_notify(current, instruction, regs);
553 handle_unaligned_access(instruction, regs, &user_mem_access,
561 * SH-DSP support gerg@snapgear.com.
563 int is_dsp_inst(struct pt_regs *regs)
565 unsigned short inst = 0;
568 * Safe guard if DSP mode is already enabled or we're lacking
569 * the DSP altogether.
571 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
574 get_user(inst, ((unsigned short *) regs->pc));
578 /* Check for any type of DSP or support instruction */
579 if ((inst == 0xf000) || (inst == 0x4000))
585 #define is_dsp_inst(regs) (0)
586 #endif /* CONFIG_SH_DSP */
588 #ifdef CONFIG_CPU_SH2A
589 asmlinkage void do_divide_error(unsigned long r4)
594 case TRAP_DIVZERO_ERROR:
597 case TRAP_DIVOVF_ERROR:
601 /* Let gcc know unhandled cases don't make it past here */
604 force_sig_fault(SIGFPE, code, NULL);
608 asmlinkage void do_reserved_inst(void)
610 struct pt_regs *regs = current_pt_regs();
611 unsigned long error_code;
613 #ifdef CONFIG_SH_FPU_EMU
614 unsigned short inst = 0;
617 get_user(inst, (unsigned short*)regs->pc);
619 err = do_fpu_inst(inst, regs);
621 regs->pc += instruction_size(inst);
624 /* not a FPU inst. */
628 /* Check if it's a DSP instruction */
629 if (is_dsp_inst(regs)) {
630 /* Enable DSP mode, and restart instruction. */
633 current->thread.dsp_status.status |= SR_DSP;
638 error_code = lookup_exception_vector();
642 die_if_no_fixup("reserved instruction", regs, error_code);
645 #ifdef CONFIG_SH_FPU_EMU
646 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
649 * bfs: 8fxx: PC+=d*2+4;
650 * bts: 8dxx: PC+=d*2+4;
651 * bra: axxx: PC+=D*2+4;
652 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
653 * braf:0x23: PC+=Rn*2+4;
654 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
656 * jsr: 4x0b: PC=Rn after PR=PC+4;
659 if (((inst & 0xf000) == 0xb000) || /* bsr */
660 ((inst & 0xf0ff) == 0x0003) || /* bsrf */
661 ((inst & 0xf0ff) == 0x400b)) /* jsr */
662 regs->pr = regs->pc + 4;
664 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */
665 regs->pc += SH_PC_8BIT_OFFSET(inst);
669 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */
670 regs->pc += SH_PC_12BIT_OFFSET(inst);
674 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */
675 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
679 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */
680 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
684 if ((inst & 0xffff) == 0x000b) { /* rts */
693 asmlinkage void do_illegal_slot_inst(void)
695 struct pt_regs *regs = current_pt_regs();
698 if (kprobe_handle_illslot(regs->pc) == 0)
701 #ifdef CONFIG_SH_FPU_EMU
702 get_user(inst, (unsigned short *)regs->pc + 1);
703 if (!do_fpu_inst(inst, regs)) {
704 get_user(inst, (unsigned short *)regs->pc);
705 if (!emulate_branch(inst, regs))
707 /* fault in branch.*/
709 /* not a FPU inst. */
712 inst = lookup_exception_vector();
716 die_if_no_fixup("illegal slot instruction", regs, inst);
719 asmlinkage void do_exception_error(void)
723 ex = lookup_exception_vector();
724 die_if_kernel("exception", current_pt_regs(), ex);
727 void per_cpu_trap_init(void)
729 extern void *vbr_base;
731 /* NOTE: The VBR value should be at P1
732 (or P2, virtural "fixed" address space).
733 It's definitely should not in physical address. */
735 asm volatile("ldc %0, vbr"
740 /* disable exception blocking now when the vbr has been setup */
744 void *set_exception_table_vec(unsigned int vec, void *handler)
746 extern void *exception_handling_table[];
749 old_handler = exception_handling_table[vec];
750 exception_handling_table[vec] = handler;
754 void __init trap_init(void)
756 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
757 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
759 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
760 defined(CONFIG_SH_FPU_EMU)
762 * For SH-4 lacking an FPU, treat floating point instructions as
763 * reserved. They'll be handled in the math-emu case, or faulted on
766 set_exception_table_evt(0x800, do_reserved_inst);
767 set_exception_table_evt(0x820, do_illegal_slot_inst);
768 #elif defined(CONFIG_SH_FPU)
769 set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
770 set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
773 #ifdef CONFIG_CPU_SH2
774 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
776 #ifdef CONFIG_CPU_SH2A
777 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
778 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
780 set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
785 set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);