1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4/probe.c
5 * CPU Subtype Probing for SH-4.
7 * Copyright (C) 2001 - 2007 Paul Mundt
8 * Copyright (C) 2003 Richard Curnow
10 #include <linux/init.h>
12 #include <asm/processor.h>
13 #include <asm/cache.h>
17 unsigned long pvr, prr, cvr;
20 static unsigned long sizes[16] = {
28 pvr = (__raw_readl(CCN_PVR) >> 8) & 0xffffff;
29 prr = (__raw_readl(CCN_PRR) >> 4) & 0xff;
30 cvr = (__raw_readl(CCN_CVR));
33 * Setup some sane SH-4 defaults for the icache
35 boot_cpu_data.icache.way_incr = (1 << 13);
36 boot_cpu_data.icache.entry_shift = 5;
37 boot_cpu_data.icache.sets = 256;
38 boot_cpu_data.icache.ways = 1;
39 boot_cpu_data.icache.linesz = L1_CACHE_BYTES;
42 * And again for the dcache ..
44 boot_cpu_data.dcache.way_incr = (1 << 14);
45 boot_cpu_data.dcache.entry_shift = 5;
46 boot_cpu_data.dcache.sets = 512;
47 boot_cpu_data.dcache.ways = 1;
48 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
50 /* We don't know the chip cut */
51 boot_cpu_data.cut_major = boot_cpu_data.cut_minor = -1;
54 * Setup some generic flags we can probe on SH-4A parts
56 if (((pvr >> 16) & 0xff) == 0x10) {
57 boot_cpu_data.family = CPU_FAMILY_SH4A;
59 if ((cvr & 0x10000000) == 0) {
60 boot_cpu_data.flags |= CPU_HAS_DSP;
61 boot_cpu_data.family = CPU_FAMILY_SH4AL_DSP;
64 boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER;
65 boot_cpu_data.cut_major = pvr & 0x7f;
67 boot_cpu_data.icache.ways = 4;
68 boot_cpu_data.dcache.ways = 4;
70 /* And some SH-4 defaults.. */
71 boot_cpu_data.flags |= CPU_HAS_PTEA | CPU_HAS_FPU;
72 boot_cpu_data.family = CPU_FAMILY_SH4;
75 /* FPU detection works for almost everyone */
76 if ((cvr & 0x20000000))
77 boot_cpu_data.flags |= CPU_HAS_FPU;
79 /* Mask off the upper chip ID */
83 * Probe the underlying processor version/revision and
84 * adjust cpu_data setup accordingly.
88 boot_cpu_data.type = CPU_SH7750;
89 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG |
93 boot_cpu_data.type = CPU_SH7750S;
94 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG |
98 boot_cpu_data.type = CPU_SH7751;
102 boot_cpu_data.type = CPU_SH7770;
107 boot_cpu_data.type = CPU_SH7781;
108 else if (prr == 0xa1)
109 boot_cpu_data.type = CPU_SH7763;
111 boot_cpu_data.type = CPU_SH7780;
117 boot_cpu_data.type = CPU_SH7343;
121 boot_cpu_data.type = CPU_SH7785;
125 boot_cpu_data.type = CPU_SH7786;
126 boot_cpu_data.flags |= CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE;
132 boot_cpu_data.type = CPU_SH7723;
133 boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
136 boot_cpu_data.type = CPU_SH7366;
140 boot_cpu_data.type = CPU_SH7722;
147 boot_cpu_data.type = CPU_SH7724;
148 boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
152 boot_cpu_data.type = CPU_SH7757;
155 case 0x40: /* yon-ten-go */
156 boot_cpu_data.type = CPU_SH7372;
158 case 0xE0: /* 0x4E0 */
159 boot_cpu_data.type = CPU_SH7734; /* SH7733/SH7734 */
164 case 0x4000: /* 1st cut */
165 case 0x4001: /* 2nd cut */
166 boot_cpu_data.type = CPU_SHX3;
169 boot_cpu_data.type = CPU_SH4_501;
170 boot_cpu_data.flags &= ~CPU_HAS_FPU;
171 boot_cpu_data.icache.ways = 2;
172 boot_cpu_data.dcache.ways = 2;
175 boot_cpu_data.type = CPU_SH4_202;
176 boot_cpu_data.icache.ways = 2;
177 boot_cpu_data.dcache.ways = 2;
179 case 0x500 ... 0x501:
182 boot_cpu_data.type = CPU_SH7750R;
185 boot_cpu_data.type = CPU_SH7751R;
188 boot_cpu_data.type = CPU_SH7760;
192 boot_cpu_data.icache.ways = 2;
193 boot_cpu_data.dcache.ways = 2;
199 * On anything that's not a direct-mapped cache, look to the CVR
200 * for I/D-cache specifics.
202 if (boot_cpu_data.icache.ways > 1) {
203 size = sizes[(cvr >> 20) & 0xf];
204 boot_cpu_data.icache.way_incr = (size >> 1);
205 boot_cpu_data.icache.sets = (size >> 6);
209 /* And the rest of the D-cache */
210 if (boot_cpu_data.dcache.ways > 1) {
211 size = sizes[(cvr >> 16) & 0xf];
212 boot_cpu_data.dcache.way_incr = (size >> 1);
213 boot_cpu_data.dcache.sets = (size >> 6);
217 * SH-4A's have an optional PIPT L2.
219 if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
221 * Verify that it really has something hooked up, this
222 * is the safety net for CPUs that have optional L2
223 * support yet do not implement it.
225 if ((cvr & 0xf) == 0)
226 boot_cpu_data.flags &= ~CPU_HAS_L2_CACHE;
229 * Silicon and specifications have clearly never
235 * Size calculation is much more sensible
236 * than it is for the L1.
238 * Sizes are 128KB, 256KB, 512KB, and 1MB.
240 size = (cvr & 0xf) << 17;
242 boot_cpu_data.scache.way_incr = (1 << 16);
243 boot_cpu_data.scache.entry_shift = 5;
244 boot_cpu_data.scache.ways = 4;
245 boot_cpu_data.scache.linesz = L1_CACHE_BYTES;
247 boot_cpu_data.scache.entry_mask =
248 (boot_cpu_data.scache.way_incr -
249 boot_cpu_data.scache.linesz);
251 boot_cpu_data.scache.sets = size /
252 (boot_cpu_data.scache.linesz *
253 boot_cpu_data.scache.ways);
255 boot_cpu_data.scache.way_size =
256 (boot_cpu_data.scache.sets *
257 boot_cpu_data.scache.linesz);