1 // SPDX-License-Identifier: GPL-2.0
3 * Access to PCI I/O memory from user space programs.
5 * Copyright IBM Corp. 2014
6 * Author(s): Alexey Ishchuk <aishchuk@linux.vnet.ibm.com>
8 #include <linux/kernel.h>
9 #include <linux/syscalls.h>
10 #include <linux/init.h>
12 #include <linux/errno.h>
13 #include <linux/pci.h>
14 #include <asm/pci_io.h>
15 #include <asm/pci_debug.h>
17 static inline void zpci_err_mmio(u8 cc, u8 status, u64 offset)
23 } data = {offset, cc, status};
25 zpci_err_hex(&data, sizeof(data));
28 static inline int __pcistb_mio_inuser(
29 void __iomem *ioaddr, const void __user *src,
36 "0: .insn rsy,0xeb00000000d4,%[len],%[ioaddr],%[src]\n"
40 EX_TABLE(0b, 2b) EX_TABLE(1b, 2b)
41 : [cc] "+d" (cc), [len] "+d" (len)
42 : [ioaddr] "a" (ioaddr), [src] "Q" (*((u8 __force *)src))
44 *status = len >> 24 & 0xff;
48 static inline int __pcistg_mio_inuser(
49 void __iomem *ioaddr, const void __user *src,
52 register u64 addr asm("2") = (u64 __force) ioaddr;
53 register u64 len asm("3") = ulen;
60 * copy 0 < @len <= 8 bytes from @src into the right most bytes of
61 * a register, then store it to PCI at @ioaddr while in secondary
62 * address space. pcistg then uses the user mappings.
66 "0: llgc %[tmp],0(%[src])\n"
67 " sllg %[val],%[val],8\n"
69 " ogr %[val],%[tmp]\n"
71 "1: .insn rre,0xb9d40000,%[val],%[ioaddr]\n"
75 EX_TABLE(0b, 3b) EX_TABLE(1b, 3b) EX_TABLE(2b, 3b)
77 [src] "+a" (src), [cnt] "+d" (cnt),
78 [val] "+d" (val), [tmp] "=d" (tmp),
79 [len] "+d" (len), [cc] "+d" (cc),
82 *status = len >> 24 & 0xff;
84 /* did we read everything from user memory? */
91 static inline int __memcpy_toio_inuser(void __iomem *dst,
92 const void __user *src, size_t n)
101 size = zpci_get_max_write_size((u64 __force) dst,
102 (u64 __force) src, n,
103 ZPCI_MAX_WRITE_SIZE);
104 if (size > 8) /* main path */
105 rc = __pcistb_mio_inuser(dst, src, size, &status);
107 rc = __pcistg_mio_inuser(dst, src, size, &status);
115 zpci_err_mmio(rc, status, (__force u64) dst);
119 SYSCALL_DEFINE3(s390_pci_mmio_write, unsigned long, mmio_addr,
120 const void __user *, user_buffer, size_t, length)
123 void __iomem *io_addr;
125 struct vm_area_struct *vma;
130 if (!zpci_is_enabled())
133 if (length <= 0 || PAGE_SIZE - (mmio_addr & ~PAGE_MASK) < length)
137 * We only support write access to MIO capable devices if we are on
138 * a MIO enabled system. Otherwise we would have to check for every
139 * address if it is a special ZPCI_ADDR and would have to do
140 * a pfn lookup which we don't need for MIO capable devices. Currently
141 * ISM devices are the only devices without MIO support and there is no
142 * known need for accessing these from userspace.
144 if (static_branch_likely(&have_mio)) {
145 ret = __memcpy_toio_inuser((void __iomem *) mmio_addr,
152 buf = kmalloc(length, GFP_KERNEL);
159 if (copy_from_user(buf, user_buffer, length))
162 mmap_read_lock(current->mm);
164 vma = find_vma(current->mm, mmio_addr);
166 goto out_unlock_mmap;
167 if (!(vma->vm_flags & (VM_IO | VM_PFNMAP)))
168 goto out_unlock_mmap;
170 if (!(vma->vm_flags & VM_WRITE))
171 goto out_unlock_mmap;
173 ret = follow_pte(vma->vm_mm, mmio_addr, &ptep, &ptl);
175 goto out_unlock_mmap;
177 io_addr = (void __iomem *)((pte_pfn(*ptep) << PAGE_SHIFT) |
178 (mmio_addr & ~PAGE_MASK));
180 if ((unsigned long) io_addr < ZPCI_IOMAP_ADDR_BASE)
183 ret = zpci_memcpy_toio(io_addr, buf, length);
185 pte_unmap_unlock(ptep, ptl);
187 mmap_read_unlock(current->mm);
189 if (buf != local_buf)
194 static inline int __pcilg_mio_inuser(
195 void __user *dst, const void __iomem *ioaddr,
196 u64 ulen, u8 *status)
198 register u64 addr asm("2") = (u64 __force) ioaddr;
199 register u64 len asm("3") = ulen;
201 int shift = ulen * 8;
206 * read 0 < @len <= 8 bytes from the PCI memory mapped at @ioaddr (in
207 * user space) into a register using pcilg then store these bytes at
212 "0: .insn rre,0xb9d60000,%[val],%[ioaddr]\n"
217 "2: ahi %[shift],-8\n"
218 " srlg %[tmp],%[val],0(%[shift])\n"
219 "3: stc %[tmp],0(%[dst])\n"
223 EX_TABLE(0b, 4b) EX_TABLE(1b, 4b) EX_TABLE(3b, 4b)
225 [cc] "+d" (cc), [val] "=d" (val), [len] "+d" (len),
226 [dst] "+a" (dst), [cnt] "+d" (cnt), [tmp] "=d" (tmp),
232 /* did we write everything to the user space buffer? */
236 *status = len >> 24 & 0xff;
240 static inline int __memcpy_fromio_inuser(void __user *dst,
241 const void __iomem *src,
248 size = zpci_get_max_write_size((u64 __force) src,
249 (u64 __force) dst, n,
251 rc = __pcilg_mio_inuser(dst, src, size, &status);
259 zpci_err_mmio(rc, status, (__force u64) dst);
263 SYSCALL_DEFINE3(s390_pci_mmio_read, unsigned long, mmio_addr,
264 void __user *, user_buffer, size_t, length)
267 void __iomem *io_addr;
269 struct vm_area_struct *vma;
274 if (!zpci_is_enabled())
277 if (length <= 0 || PAGE_SIZE - (mmio_addr & ~PAGE_MASK) < length)
281 * We only support read access to MIO capable devices if we are on
282 * a MIO enabled system. Otherwise we would have to check for every
283 * address if it is a special ZPCI_ADDR and would have to do
284 * a pfn lookup which we don't need for MIO capable devices. Currently
285 * ISM devices are the only devices without MIO support and there is no
286 * known need for accessing these from userspace.
288 if (static_branch_likely(&have_mio)) {
289 ret = __memcpy_fromio_inuser(
290 user_buffer, (const void __iomem *)mmio_addr,
296 buf = kmalloc(length, GFP_KERNEL);
303 mmap_read_lock(current->mm);
305 vma = find_vma(current->mm, mmio_addr);
307 goto out_unlock_mmap;
308 if (!(vma->vm_flags & (VM_IO | VM_PFNMAP)))
309 goto out_unlock_mmap;
311 if (!(vma->vm_flags & VM_WRITE))
312 goto out_unlock_mmap;
314 ret = follow_pte(vma->vm_mm, mmio_addr, &ptep, &ptl);
316 goto out_unlock_mmap;
318 io_addr = (void __iomem *)((pte_pfn(*ptep) << PAGE_SHIFT) |
319 (mmio_addr & ~PAGE_MASK));
321 if ((unsigned long) io_addr < ZPCI_IOMAP_ADDR_BASE) {
325 ret = zpci_memcpy_fromio(buf, io_addr, length);
328 pte_unmap_unlock(ptep, ptl);
330 mmap_read_unlock(current->mm);
332 if (!ret && copy_to_user(user_buffer, buf, length))
335 if (buf != local_buf)