1 // SPDX-License-Identifier: GPL-2.0
3 * BPF Jit compiler for s390.
5 * Minimum build requirements:
7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
13 * Copyright IBM Corp. 2012,2015
15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
16 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
19 #define KMSG_COMPONENT "bpf_jit"
20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
22 #include <linux/netdevice.h>
23 #include <linux/filter.h>
24 #include <linux/init.h>
25 #include <linux/bpf.h>
26 #include <asm/cacheflush.h>
28 #include <asm/facility.h>
29 #include <asm/nospec-branch.h>
30 #include <asm/set_memory.h>
34 u32 seen; /* Flags to remember seen eBPF instructions */
35 u32 seen_reg[16]; /* Array to remember which registers are used */
36 u32 *addrs; /* Array with relative instruction addresses */
37 u8 *prg_buf; /* Start of program */
38 int size; /* Size of program and literal pool */
39 int size_prg; /* Size of program */
40 int prg; /* Current position in program */
41 int lit_start; /* Start of literal pool */
42 int lit; /* Current position in literal pool */
43 int base_ip; /* Base address for literal pool */
44 int ret0_ip; /* Address of return 0 */
45 int exit_ip; /* Address of exit */
46 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */
47 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */
48 int tail_call_start; /* Tail call start offset */
49 int labels[1]; /* Labels for local jumps */
52 #define BPF_SIZE_MAX 0xffff /* Max size for program (16 bit branches) */
54 #define SEEN_MEM (1 << 0) /* use mem[] for temporary storage */
55 #define SEEN_RET0 (1 << 1) /* ret0_ip points to a valid return 0 */
56 #define SEEN_LITERAL (1 << 2) /* code uses literals */
57 #define SEEN_FUNC (1 << 3) /* calls C functions */
58 #define SEEN_TAIL_CALL (1 << 4) /* code uses tail calls */
59 #define SEEN_REG_AX (1 << 5) /* code uses constant blinding */
60 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM)
65 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
66 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */
67 #define REG_L (MAX_BPF_JIT_REG + 2) /* Literal pool register */
68 #define REG_15 (MAX_BPF_JIT_REG + 3) /* Register 15 */
69 #define REG_0 REG_W0 /* Register 0 */
70 #define REG_1 REG_W1 /* Register 1 */
71 #define REG_2 BPF_REG_1 /* Register 2 */
72 #define REG_14 BPF_REG_0 /* Register 14 */
75 * Mapping of BPF registers to s390 registers
77 static const int reg2hex[] = {
80 /* Function parameters */
86 /* Call saved registers */
91 /* BPF stack pointer */
93 /* Register for blinding */
95 /* Work registers for s390x backend */
102 static inline u32 reg(u32 dst_reg, u32 src_reg)
104 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
107 static inline u32 reg_high(u32 reg)
109 return reg2hex[reg] << 4;
112 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
114 u32 r1 = reg2hex[b1];
116 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15)
117 jit->seen_reg[r1] = 1;
120 #define REG_SET_SEEN(b1) \
122 reg_set_seen(jit, b1); \
125 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
128 * EMIT macros for code generation
134 *(u16 *) (jit->prg_buf + jit->prg) = op; \
138 #define EMIT2(op, b1, b2) \
140 _EMIT2(op | reg(b1, b2)); \
148 *(u32 *) (jit->prg_buf + jit->prg) = op; \
152 #define EMIT4(op, b1, b2) \
154 _EMIT4(op | reg(b1, b2)); \
159 #define EMIT4_RRF(op, b1, b2, b3) \
161 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \
167 #define _EMIT4_DISP(op, disp) \
169 unsigned int __disp = (disp) & 0xfff; \
170 _EMIT4(op | __disp); \
173 #define EMIT4_DISP(op, b1, b2, disp) \
175 _EMIT4_DISP(op | reg_high(b1) << 16 | \
176 reg_high(b2) << 8, disp); \
181 #define EMIT4_IMM(op, b1, imm) \
183 unsigned int __imm = (imm) & 0xffff; \
184 _EMIT4(op | reg_high(b1) << 16 | __imm); \
188 #define EMIT4_PCREL(op, pcrel) \
190 long __pcrel = ((pcrel) >> 1) & 0xffff; \
191 _EMIT4(op | __pcrel); \
194 #define _EMIT6(op1, op2) \
196 if (jit->prg_buf) { \
197 *(u32 *) (jit->prg_buf + jit->prg) = op1; \
198 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
203 #define _EMIT6_DISP(op1, op2, disp) \
205 unsigned int __disp = (disp) & 0xfff; \
206 _EMIT6(op1 | __disp, op2); \
209 #define _EMIT6_DISP_LH(op1, op2, disp) \
211 u32 _disp = (u32) disp; \
212 unsigned int __disp_h = _disp & 0xff000; \
213 unsigned int __disp_l = _disp & 0x00fff; \
214 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
217 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
219 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \
220 reg_high(b3) << 8, op2, disp); \
226 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
228 int rel = (jit->labels[label] - jit->prg) >> 1; \
229 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \
235 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
237 int rel = (jit->labels[label] - jit->prg) >> 1; \
238 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \
239 (rel & 0xffff), op2 | (imm & 0xff) << 8); \
241 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \
244 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
246 /* Branch instruction needs 6 bytes */ \
247 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\
248 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \
253 #define EMIT6_PCREL_RILB(op, b, target) \
255 int rel = (target - jit->prg) / 2; \
256 _EMIT6(op | reg_high(b) << 16 | rel >> 16, rel & 0xffff); \
260 #define EMIT6_PCREL_RIL(op, target) \
262 int rel = (target - jit->prg) / 2; \
263 _EMIT6(op | rel >> 16, rel & 0xffff); \
266 #define _EMIT6_IMM(op, imm) \
268 unsigned int __imm = (imm); \
269 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \
272 #define EMIT6_IMM(op, b1, imm) \
274 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \
278 #define EMIT_CONST_U32(val) \
281 ret = jit->lit - jit->base_ip; \
282 jit->seen |= SEEN_LITERAL; \
284 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \
289 #define EMIT_CONST_U64(val) \
292 ret = jit->lit - jit->base_ip; \
293 jit->seen |= SEEN_LITERAL; \
295 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \
300 #define EMIT_ZERO(b1) \
302 if (!fp->aux->verifier_zext) { \
303 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
304 EMIT4(0xb9160000, b1, b1); \
310 * Fill whole space with illegal instructions
312 static void jit_fill_hole(void *area, unsigned int size)
314 memset(area, 0, size);
318 * Save registers from "rs" (register start) to "re" (register end) on stack
320 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
322 u32 off = STK_OFF_R6 + (rs - 6) * 8;
325 /* stg %rs,off(%r15) */
326 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
328 /* stmg %rs,%re,off(%r15) */
329 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
333 * Restore registers from "rs" (register start) to "re" (register end) on stack
335 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re, u32 stack_depth)
337 u32 off = STK_OFF_R6 + (rs - 6) * 8;
339 if (jit->seen & SEEN_STACK)
340 off += STK_OFF + stack_depth;
343 /* lg %rs,off(%r15) */
344 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
346 /* lmg %rs,%re,off(%r15) */
347 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
351 * Return first seen register (from start)
353 static int get_start(struct bpf_jit *jit, int start)
357 for (i = start; i <= 15; i++) {
358 if (jit->seen_reg[i])
365 * Return last seen register (from start) (gap >= 2)
367 static int get_end(struct bpf_jit *jit, int start)
371 for (i = start; i < 15; i++) {
372 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
375 return jit->seen_reg[15] ? 15 : 14;
379 #define REGS_RESTORE 0
381 * Save and restore clobbered registers (6-15) on stack.
382 * We save/restore registers in chunks with gap >= 2 registers.
384 static void save_restore_regs(struct bpf_jit *jit, int op, u32 stack_depth)
390 rs = get_start(jit, re);
393 re = get_end(jit, rs + 1);
395 save_regs(jit, rs, re);
397 restore_regs(jit, rs, re, stack_depth);
403 * Emit function prologue
405 * Save registers and create stack frame if necessary.
406 * See stack frame layout desription in "bpf_jit.h"!
408 static void bpf_jit_prologue(struct bpf_jit *jit, u32 stack_depth)
410 if (jit->seen & SEEN_TAIL_CALL) {
411 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
412 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
414 /* j tail_call_start: NOP if no tail calls are used */
415 EMIT4_PCREL(0xa7f40000, 6);
418 /* Tail calls have to skip above initialization */
419 jit->tail_call_start = jit->prg;
421 save_restore_regs(jit, REGS_SAVE, stack_depth);
422 /* Setup literal pool */
423 if (jit->seen & SEEN_LITERAL) {
425 EMIT2(0x0d00, REG_L, REG_0);
426 jit->base_ip = jit->prg;
428 /* Setup stack and backchain */
429 if (jit->seen & SEEN_STACK) {
430 if (jit->seen & SEEN_FUNC)
431 /* lgr %w1,%r15 (backchain) */
432 EMIT4(0xb9040000, REG_W1, REG_15);
433 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
434 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
435 /* aghi %r15,-STK_OFF */
436 EMIT4_IMM(0xa70b0000, REG_15, -(STK_OFF + stack_depth));
437 if (jit->seen & SEEN_FUNC)
438 /* stg %w1,152(%r15) (backchain) */
439 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
447 static void bpf_jit_epilogue(struct bpf_jit *jit, u32 stack_depth)
450 if (jit->seen & SEEN_RET0) {
451 jit->ret0_ip = jit->prg;
453 EMIT4_IMM(0xa7090000, BPF_REG_0, 0);
455 jit->exit_ip = jit->prg;
456 /* Load exit code: lgr %r2,%b0 */
457 EMIT4(0xb9040000, REG_2, BPF_REG_0);
458 /* Restore registers */
459 save_restore_regs(jit, REGS_RESTORE, stack_depth);
460 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) {
461 jit->r14_thunk_ip = jit->prg;
462 /* Generate __s390_indirect_jump_r14 thunk */
463 if (test_facility(35)) {
465 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
468 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14);
470 EMIT4_DISP(0x44000000, REG_0, REG_1, 0);
473 EMIT4_PCREL(0xa7f40000, 0);
478 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable &&
479 (jit->seen & SEEN_FUNC)) {
480 jit->r1_thunk_ip = jit->prg;
481 /* Generate __s390_indirect_jump_r1 thunk */
482 if (test_facility(35)) {
484 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
486 EMIT4_PCREL(0xa7f40000, 0);
490 /* ex 0,S390_lowcore.br_r1_tampoline */
491 EMIT4_DISP(0x44000000, REG_0, REG_0,
492 offsetof(struct lowcore, br_r1_trampoline));
494 EMIT4_PCREL(0xa7f40000, 0);
500 * Compile one eBPF instruction into s390x code
502 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
503 * stack space for the large switch statement.
505 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i)
507 struct bpf_insn *insn = &fp->insnsi[i];
508 int jmp_off, last, insn_count = 1;
509 u32 dst_reg = insn->dst_reg;
510 u32 src_reg = insn->src_reg;
511 u32 *addrs = jit->addrs;
516 if (dst_reg == BPF_REG_AX || src_reg == BPF_REG_AX)
517 jit->seen |= SEEN_REG_AX;
518 switch (insn->code) {
522 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
523 /* llgfr %dst,%src */
524 EMIT4(0xb9160000, dst_reg, src_reg);
525 if (insn_is_zext(&insn[1]))
528 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
530 EMIT4(0xb9040000, dst_reg, src_reg);
532 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
534 EMIT6_IMM(0xc00f0000, dst_reg, imm);
535 if (insn_is_zext(&insn[1]))
538 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
540 EMIT6_IMM(0xc0010000, dst_reg, imm);
545 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
547 /* 16 byte instruction that uses two 'struct bpf_insn' */
550 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
551 /* lg %dst,<d(imm)>(%l) */
552 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L,
553 EMIT_CONST_U64(imm64));
560 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
562 EMIT2(0x1a00, dst_reg, src_reg);
565 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
567 EMIT4(0xb9080000, dst_reg, src_reg);
569 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
573 EMIT6_IMM(0xc20b0000, dst_reg, imm);
576 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
580 EMIT6_IMM(0xc2080000, dst_reg, imm);
585 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
587 EMIT2(0x1b00, dst_reg, src_reg);
590 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
592 EMIT4(0xb9090000, dst_reg, src_reg);
594 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
598 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
601 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
605 EMIT6_IMM(0xc2080000, dst_reg, -imm);
610 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
612 EMIT4(0xb2520000, dst_reg, src_reg);
615 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
617 EMIT4(0xb90c0000, dst_reg, src_reg);
619 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
623 EMIT6_IMM(0xc2010000, dst_reg, imm);
626 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
630 EMIT6_IMM(0xc2000000, dst_reg, imm);
635 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
636 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
638 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
641 EMIT4_IMM(0xa7080000, REG_W0, 0);
643 EMIT2(0x1800, REG_W1, dst_reg);
645 EMIT4(0xb9970000, REG_W0, src_reg);
647 EMIT4(0xb9160000, dst_reg, rc_reg);
648 if (insn_is_zext(&insn[1]))
652 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
653 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
655 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
658 EMIT4_IMM(0xa7090000, REG_W0, 0);
660 EMIT4(0xb9040000, REG_W1, dst_reg);
662 EMIT4(0xb9870000, REG_W0, src_reg);
664 EMIT4(0xb9040000, dst_reg, rc_reg);
667 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
668 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
670 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
673 if (BPF_OP(insn->code) == BPF_MOD)
675 EMIT4_IMM(0xa7090000, dst_reg, 0);
679 EMIT4_IMM(0xa7080000, REG_W0, 0);
681 EMIT2(0x1800, REG_W1, dst_reg);
682 /* dl %w0,<d(imm)>(%l) */
683 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
684 EMIT_CONST_U32(imm));
686 EMIT4(0xb9160000, dst_reg, rc_reg);
687 if (insn_is_zext(&insn[1]))
691 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
692 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
694 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
697 if (BPF_OP(insn->code) == BPF_MOD)
699 EMIT4_IMM(0xa7090000, dst_reg, 0);
703 EMIT4_IMM(0xa7090000, REG_W0, 0);
705 EMIT4(0xb9040000, REG_W1, dst_reg);
706 /* dlg %w0,<d(imm)>(%l) */
707 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
708 EMIT_CONST_U64(imm));
710 EMIT4(0xb9040000, dst_reg, rc_reg);
716 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
718 EMIT2(0x1400, dst_reg, src_reg);
721 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
723 EMIT4(0xb9800000, dst_reg, src_reg);
725 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
727 EMIT6_IMM(0xc00b0000, dst_reg, imm);
730 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
731 /* ng %dst,<d(imm)>(%l) */
732 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L,
733 EMIT_CONST_U64(imm));
738 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
740 EMIT2(0x1600, dst_reg, src_reg);
743 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
745 EMIT4(0xb9810000, dst_reg, src_reg);
747 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
749 EMIT6_IMM(0xc00d0000, dst_reg, imm);
752 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
753 /* og %dst,<d(imm)>(%l) */
754 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L,
755 EMIT_CONST_U64(imm));
760 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
762 EMIT2(0x1700, dst_reg, src_reg);
765 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
767 EMIT4(0xb9820000, dst_reg, src_reg);
769 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
773 EMIT6_IMM(0xc0070000, dst_reg, imm);
776 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
777 /* xg %dst,<d(imm)>(%l) */
778 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L,
779 EMIT_CONST_U64(imm));
784 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
785 /* sll %dst,0(%src) */
786 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
789 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
790 /* sllg %dst,%dst,0(%src) */
791 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
793 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
796 /* sll %dst,imm(%r0) */
797 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
800 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
803 /* sllg %dst,%dst,imm(%r0) */
804 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
809 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
810 /* srl %dst,0(%src) */
811 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
814 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
815 /* srlg %dst,%dst,0(%src) */
816 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
818 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
821 /* srl %dst,imm(%r0) */
822 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
825 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
828 /* srlg %dst,%dst,imm(%r0) */
829 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
834 case BPF_ALU | BPF_ARSH | BPF_X: /* ((s32) dst) >>= src */
835 /* sra %dst,%dst,0(%src) */
836 EMIT4_DISP(0x8a000000, dst_reg, src_reg, 0);
839 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
840 /* srag %dst,%dst,0(%src) */
841 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
843 case BPF_ALU | BPF_ARSH | BPF_K: /* ((s32) dst >> imm */
846 /* sra %dst,imm(%r0) */
847 EMIT4_DISP(0x8a000000, dst_reg, REG_0, imm);
850 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
853 /* srag %dst,%dst,imm(%r0) */
854 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
859 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
861 EMIT2(0x1300, dst_reg, dst_reg);
864 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
866 EMIT4(0xb9030000, dst_reg, dst_reg);
871 case BPF_ALU | BPF_END | BPF_FROM_BE:
872 /* s390 is big endian, therefore only clear high order bytes */
874 case 16: /* dst = (u16) cpu_to_be16(dst) */
875 /* llghr %dst,%dst */
876 EMIT4(0xb9850000, dst_reg, dst_reg);
877 if (insn_is_zext(&insn[1]))
880 case 32: /* dst = (u32) cpu_to_be32(dst) */
881 if (!fp->aux->verifier_zext)
882 /* llgfr %dst,%dst */
883 EMIT4(0xb9160000, dst_reg, dst_reg);
885 case 64: /* dst = (u64) cpu_to_be64(dst) */
889 case BPF_ALU | BPF_END | BPF_FROM_LE:
891 case 16: /* dst = (u16) cpu_to_le16(dst) */
893 EMIT4(0xb91f0000, dst_reg, dst_reg);
894 /* srl %dst,16(%r0) */
895 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
896 /* llghr %dst,%dst */
897 EMIT4(0xb9850000, dst_reg, dst_reg);
898 if (insn_is_zext(&insn[1]))
901 case 32: /* dst = (u32) cpu_to_le32(dst) */
903 EMIT4(0xb91f0000, dst_reg, dst_reg);
904 if (!fp->aux->verifier_zext)
905 /* llgfr %dst,%dst */
906 EMIT4(0xb9160000, dst_reg, dst_reg);
908 case 64: /* dst = (u64) cpu_to_le64(dst) */
909 /* lrvgr %dst,%dst */
910 EMIT4(0xb90f0000, dst_reg, dst_reg);
917 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
918 /* stcy %src,off(%dst) */
919 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
920 jit->seen |= SEEN_MEM;
922 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
923 /* sthy %src,off(%dst) */
924 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
925 jit->seen |= SEEN_MEM;
927 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
928 /* sty %src,off(%dst) */
929 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
930 jit->seen |= SEEN_MEM;
932 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
933 /* stg %src,off(%dst) */
934 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
935 jit->seen |= SEEN_MEM;
937 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
939 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
940 /* stcy %w0,off(dst) */
941 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
942 jit->seen |= SEEN_MEM;
944 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
946 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
947 /* sthy %w0,off(dst) */
948 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
949 jit->seen |= SEEN_MEM;
951 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
953 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
954 /* sty %w0,off(%dst) */
955 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
956 jit->seen |= SEEN_MEM;
958 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
960 EMIT6_IMM(0xc0010000, REG_W0, imm);
961 /* stg %w0,off(%dst) */
962 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
963 jit->seen |= SEEN_MEM;
966 * BPF_STX XADD (atomic_add)
968 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
969 /* laal %w0,%src,off(%dst) */
970 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
972 jit->seen |= SEEN_MEM;
974 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
975 /* laalg %w0,%src,off(%dst) */
976 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
978 jit->seen |= SEEN_MEM;
983 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
984 /* llgc %dst,0(off,%src) */
985 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
986 jit->seen |= SEEN_MEM;
987 if (insn_is_zext(&insn[1]))
990 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
991 /* llgh %dst,0(off,%src) */
992 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
993 jit->seen |= SEEN_MEM;
994 if (insn_is_zext(&insn[1]))
997 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
998 /* llgf %dst,off(%src) */
999 jit->seen |= SEEN_MEM;
1000 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
1001 if (insn_is_zext(&insn[1]))
1004 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
1005 /* lg %dst,0(off,%src) */
1006 jit->seen |= SEEN_MEM;
1007 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
1012 case BPF_JMP | BPF_CALL:
1015 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5)
1017 const u64 func = (u64)__bpf_call_base + imm;
1019 REG_SET_SEEN(BPF_REG_5);
1020 jit->seen |= SEEN_FUNC;
1021 /* lg %w1,<d(imm)>(%l) */
1022 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1, REG_0, REG_L,
1023 EMIT_CONST_U64(func));
1024 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) {
1025 /* brasl %r14,__s390_indirect_jump_r1 */
1026 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip);
1029 EMIT2(0x0d00, REG_14, REG_W1);
1031 /* lgr %b0,%r2: load return value into %b0 */
1032 EMIT4(0xb9040000, BPF_REG_0, REG_2);
1035 case BPF_JMP | BPF_TAIL_CALL:
1038 * B1: pointer to ctx
1039 * B2: pointer to bpf_array
1040 * B3: index in bpf_array
1042 jit->seen |= SEEN_TAIL_CALL;
1045 * if (index >= array->map.max_entries)
1049 /* llgf %w1,map.max_entries(%b2) */
1050 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
1051 offsetof(struct bpf_array, map.max_entries));
1052 /* clrj %b3,%w1,0xa,label0: if (u32)%b3 >= (u32)%w1 goto out */
1053 EMIT6_PCREL_LABEL(0xec000000, 0x0077, BPF_REG_3,
1057 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1061 if (jit->seen & SEEN_STACK)
1062 off = STK_OFF_TCCNT + STK_OFF + fp->aux->stack_depth;
1064 off = STK_OFF_TCCNT;
1066 EMIT4_IMM(0xa7080000, REG_W0, 1);
1067 /* laal %w1,%w0,off(%r15) */
1068 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1069 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1070 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1,
1071 MAX_TAIL_CALL_CNT, 0, 0x2);
1074 * prog = array->ptrs[index];
1079 /* llgfr %r1,%b3: %r1 = (u32) index */
1080 EMIT4(0xb9160000, REG_1, BPF_REG_3);
1081 /* sllg %r1,%r1,3: %r1 *= 8 */
1082 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, REG_1, REG_0, 3);
1083 /* lg %r1,prog(%b2,%r1) */
1084 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2,
1085 REG_1, offsetof(struct bpf_array, ptrs));
1086 /* clgij %r1,0,0x8,label0 */
1087 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1, 0, 0, 0x8);
1090 * Restore registers before calling function
1092 save_restore_regs(jit, REGS_RESTORE, fp->aux->stack_depth);
1095 * goto *(prog->bpf_func + tail_call_start);
1098 /* lg %r1,bpf_func(%r1) */
1099 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1100 offsetof(struct bpf_prog, bpf_func));
1101 /* bc 0xf,tail_call_start(%r1) */
1102 _EMIT4(0x47f01000 + jit->tail_call_start);
1104 jit->labels[0] = jit->prg;
1106 case BPF_JMP | BPF_EXIT: /* return b0 */
1107 last = (i == fp->len - 1) ? 1 : 0;
1108 if (last && !(jit->seen & SEEN_RET0))
1111 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg);
1114 * Branch relative (number of skipped instructions) to offset on
1117 * Condition code to mask mapping:
1119 * CC | Description | Mask
1120 * ------------------------------
1121 * 0 | Operands equal | 8
1122 * 1 | First operand low | 4
1123 * 2 | First operand high | 2
1126 * For s390x relative branches: ip = ip + off_bytes
1127 * For BPF relative branches: insn = insn + off_insns + 1
1129 * For example for s390x with offset 0 we jump to the branch
1130 * instruction itself (loop) and for BPF with offset 0 we
1131 * branch to the instruction behind the branch.
1133 case BPF_JMP | BPF_JA: /* if (true) */
1134 mask = 0xf000; /* j */
1136 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1137 case BPF_JMP32 | BPF_JSGT | BPF_K: /* ((s32) dst > (s32) imm) */
1138 mask = 0x2000; /* jh */
1140 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */
1141 case BPF_JMP32 | BPF_JSLT | BPF_K: /* ((s32) dst < (s32) imm) */
1142 mask = 0x4000; /* jl */
1144 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1145 case BPF_JMP32 | BPF_JSGE | BPF_K: /* ((s32) dst >= (s32) imm) */
1146 mask = 0xa000; /* jhe */
1148 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */
1149 case BPF_JMP32 | BPF_JSLE | BPF_K: /* ((s32) dst <= (s32) imm) */
1150 mask = 0xc000; /* jle */
1152 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1153 case BPF_JMP32 | BPF_JGT | BPF_K: /* ((u32) dst_reg > (u32) imm) */
1154 mask = 0x2000; /* jh */
1156 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */
1157 case BPF_JMP32 | BPF_JLT | BPF_K: /* ((u32) dst_reg < (u32) imm) */
1158 mask = 0x4000; /* jl */
1160 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1161 case BPF_JMP32 | BPF_JGE | BPF_K: /* ((u32) dst_reg >= (u32) imm) */
1162 mask = 0xa000; /* jhe */
1164 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */
1165 case BPF_JMP32 | BPF_JLE | BPF_K: /* ((u32) dst_reg <= (u32) imm) */
1166 mask = 0xc000; /* jle */
1168 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1169 case BPF_JMP32 | BPF_JNE | BPF_K: /* ((u32) dst_reg != (u32) imm) */
1170 mask = 0x7000; /* jne */
1172 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1173 case BPF_JMP32 | BPF_JEQ | BPF_K: /* ((u32) dst_reg == (u32) imm) */
1174 mask = 0x8000; /* je */
1176 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1177 case BPF_JMP32 | BPF_JSET | BPF_K: /* ((u32) dst_reg & (u32) imm) */
1178 mask = 0x7000; /* jnz */
1179 if (BPF_CLASS(insn->code) == BPF_JMP32) {
1180 /* llilf %w1,imm (load zero extend imm) */
1181 EMIT6_IMM(0xc00f0000, REG_W1, imm);
1183 EMIT2(0x1400, REG_W1, dst_reg);
1185 /* lgfi %w1,imm (load sign extend imm) */
1186 EMIT6_IMM(0xc0010000, REG_W1, imm);
1188 EMIT4(0xb9800000, REG_W1, dst_reg);
1192 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1193 case BPF_JMP32 | BPF_JSGT | BPF_X: /* ((s32) dst > (s32) src) */
1194 mask = 0x2000; /* jh */
1196 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */
1197 case BPF_JMP32 | BPF_JSLT | BPF_X: /* ((s32) dst < (s32) src) */
1198 mask = 0x4000; /* jl */
1200 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1201 case BPF_JMP32 | BPF_JSGE | BPF_X: /* ((s32) dst >= (s32) src) */
1202 mask = 0xa000; /* jhe */
1204 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */
1205 case BPF_JMP32 | BPF_JSLE | BPF_X: /* ((s32) dst <= (s32) src) */
1206 mask = 0xc000; /* jle */
1208 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1209 case BPF_JMP32 | BPF_JGT | BPF_X: /* ((u32) dst > (u32) src) */
1210 mask = 0x2000; /* jh */
1212 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */
1213 case BPF_JMP32 | BPF_JLT | BPF_X: /* ((u32) dst < (u32) src) */
1214 mask = 0x4000; /* jl */
1216 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1217 case BPF_JMP32 | BPF_JGE | BPF_X: /* ((u32) dst >= (u32) src) */
1218 mask = 0xa000; /* jhe */
1220 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */
1221 case BPF_JMP32 | BPF_JLE | BPF_X: /* ((u32) dst <= (u32) src) */
1222 mask = 0xc000; /* jle */
1224 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1225 case BPF_JMP32 | BPF_JNE | BPF_X: /* ((u32) dst != (u32) src) */
1226 mask = 0x7000; /* jne */
1228 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1229 case BPF_JMP32 | BPF_JEQ | BPF_X: /* ((u32) dst == (u32) src) */
1230 mask = 0x8000; /* je */
1232 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1233 case BPF_JMP32 | BPF_JSET | BPF_X: /* ((u32) dst & (u32) src) */
1235 bool is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1237 mask = 0x7000; /* jnz */
1238 /* nrk or ngrk %w1,%dst,%src */
1239 EMIT4_RRF((is_jmp32 ? 0xb9f40000 : 0xb9e40000),
1240 REG_W1, dst_reg, src_reg);
1243 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1244 /* lgfi %w1,imm (load sign extend imm) */
1245 EMIT6_IMM(0xc0010000, REG_W1, imm);
1246 /* crj or cgrj %dst,%w1,mask,off */
1247 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0076 : 0x0064),
1248 dst_reg, REG_W1, i, off, mask);
1251 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1252 /* lgfi %w1,imm (load sign extend imm) */
1253 EMIT6_IMM(0xc0010000, REG_W1, imm);
1254 /* clrj or clgrj %dst,%w1,mask,off */
1255 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0077 : 0x0065),
1256 dst_reg, REG_W1, i, off, mask);
1259 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1260 /* crj or cgrj %dst,%src,mask,off */
1261 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0076 : 0x0064),
1262 dst_reg, src_reg, i, off, mask);
1265 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1266 /* clrj or clgrj %dst,%src,mask,off */
1267 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0077 : 0x0065),
1268 dst_reg, src_reg, i, off, mask);
1271 /* brc mask,jmp_off (branch instruction needs 4 bytes) */
1272 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4);
1273 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off);
1276 default: /* too complex, give up */
1277 pr_err("Unknown opcode %02x\n", insn->code);
1284 * Compile eBPF program into s390x code
1286 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp)
1290 jit->lit = jit->lit_start;
1293 bpf_jit_prologue(jit, fp->aux->stack_depth);
1294 for (i = 0; i < fp->len; i += insn_count) {
1295 insn_count = bpf_jit_insn(jit, fp, i);
1298 /* Next instruction address */
1299 jit->addrs[i + insn_count] = jit->prg;
1301 bpf_jit_epilogue(jit, fp->aux->stack_depth);
1303 jit->lit_start = jit->prg;
1304 jit->size = jit->lit;
1305 jit->size_prg = jit->prg;
1309 bool bpf_jit_needs_zext(void)
1315 * Compile eBPF program "fp"
1317 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
1319 struct bpf_prog *tmp, *orig_fp = fp;
1320 struct bpf_binary_header *header;
1321 bool tmp_blinded = false;
1325 if (!fp->jit_requested)
1328 tmp = bpf_jit_blind_constants(fp);
1330 * If blinding was requested and we failed during blinding,
1331 * we must fall back to the interpreter.
1340 memset(&jit, 0, sizeof(jit));
1341 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1342 if (jit.addrs == NULL) {
1347 * Three initial passes:
1348 * - 1/2: Determine clobbered registers
1349 * - 3: Calculate program size and addrs arrray
1351 for (pass = 1; pass <= 3; pass++) {
1352 if (bpf_jit_prog(&jit, fp)) {
1358 * Final pass: Allocate and generate program
1360 if (jit.size >= BPF_SIZE_MAX) {
1364 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole);
1369 if (bpf_jit_prog(&jit, fp)) {
1370 bpf_jit_binary_free(header);
1374 if (bpf_jit_enable > 1) {
1375 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1376 print_fn_code(jit.prg_buf, jit.size_prg);
1378 bpf_jit_binary_lock_ro(header);
1379 fp->bpf_func = (void *) jit.prg_buf;
1381 fp->jited_len = jit.size;
1386 bpf_jit_prog_release_other(fp, fp == orig_fp ?