1 // SPDX-License-Identifier: GPL-2.0
3 * BPF Jit compiler for s390.
5 * Minimum build requirements:
7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
13 * Copyright IBM Corp. 2012,2015
15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
16 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
19 #define KMSG_COMPONENT "bpf_jit"
20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
22 #include <linux/netdevice.h>
23 #include <linux/filter.h>
24 #include <linux/init.h>
25 #include <linux/bpf.h>
27 #include <linux/kernel.h>
28 #include <asm/cacheflush.h>
30 #include <asm/facility.h>
31 #include <asm/nospec-branch.h>
32 #include <asm/set_memory.h>
36 u32 seen; /* Flags to remember seen eBPF instructions */
37 u32 seen_reg[16]; /* Array to remember which registers are used */
38 u32 *addrs; /* Array with relative instruction addresses */
39 u8 *prg_buf; /* Start of program */
40 int size; /* Size of program and literal pool */
41 int size_prg; /* Size of program */
42 int prg; /* Current position in program */
43 int lit32_start; /* Start of 32-bit literal pool */
44 int lit32; /* Current position in 32-bit literal pool */
45 int lit64_start; /* Start of 64-bit literal pool */
46 int lit64; /* Current position in 64-bit literal pool */
47 int base_ip; /* Base address for literal pool */
48 int exit_ip; /* Address of exit */
49 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */
50 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */
51 int tail_call_start; /* Tail call start offset */
52 int excnt; /* Number of exception table entries */
55 #define SEEN_MEM BIT(0) /* use mem[] for temporary storage */
56 #define SEEN_LITERAL BIT(1) /* code uses literals */
57 #define SEEN_FUNC BIT(2) /* calls C functions */
58 #define SEEN_TAIL_CALL BIT(3) /* code uses tail calls */
59 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM)
64 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
65 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */
66 #define REG_L (MAX_BPF_JIT_REG + 2) /* Literal pool register */
67 #define REG_15 (MAX_BPF_JIT_REG + 3) /* Register 15 */
68 #define REG_0 REG_W0 /* Register 0 */
69 #define REG_1 REG_W1 /* Register 1 */
70 #define REG_2 BPF_REG_1 /* Register 2 */
71 #define REG_14 BPF_REG_0 /* Register 14 */
74 * Mapping of BPF registers to s390 registers
76 static const int reg2hex[] = {
79 /* Function parameters */
85 /* Call saved registers */
90 /* BPF stack pointer */
92 /* Register for blinding */
94 /* Work registers for s390x backend */
101 static inline u32 reg(u32 dst_reg, u32 src_reg)
103 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
106 static inline u32 reg_high(u32 reg)
108 return reg2hex[reg] << 4;
111 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
113 u32 r1 = reg2hex[b1];
115 if (r1 >= 6 && r1 <= 15 && !jit->seen_reg[r1])
116 jit->seen_reg[r1] = 1;
119 #define REG_SET_SEEN(b1) \
121 reg_set_seen(jit, b1); \
124 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
127 * EMIT macros for code generation
133 *(u16 *) (jit->prg_buf + jit->prg) = (op); \
137 #define EMIT2(op, b1, b2) \
139 _EMIT2((op) | reg(b1, b2)); \
147 *(u32 *) (jit->prg_buf + jit->prg) = (op); \
151 #define EMIT4(op, b1, b2) \
153 _EMIT4((op) | reg(b1, b2)); \
158 #define EMIT4_RRF(op, b1, b2, b3) \
160 _EMIT4((op) | reg_high(b3) << 8 | reg(b1, b2)); \
166 #define _EMIT4_DISP(op, disp) \
168 unsigned int __disp = (disp) & 0xfff; \
169 _EMIT4((op) | __disp); \
172 #define EMIT4_DISP(op, b1, b2, disp) \
174 _EMIT4_DISP((op) | reg_high(b1) << 16 | \
175 reg_high(b2) << 8, (disp)); \
180 #define EMIT4_IMM(op, b1, imm) \
182 unsigned int __imm = (imm) & 0xffff; \
183 _EMIT4((op) | reg_high(b1) << 16 | __imm); \
187 #define EMIT4_PCREL(op, pcrel) \
189 long __pcrel = ((pcrel) >> 1) & 0xffff; \
190 _EMIT4((op) | __pcrel); \
193 #define EMIT4_PCREL_RIC(op, mask, target) \
195 int __rel = ((target) - jit->prg) / 2; \
196 _EMIT4((op) | (mask) << 20 | (__rel & 0xffff)); \
199 #define _EMIT6(op1, op2) \
201 if (jit->prg_buf) { \
202 *(u32 *) (jit->prg_buf + jit->prg) = (op1); \
203 *(u16 *) (jit->prg_buf + jit->prg + 4) = (op2); \
208 #define _EMIT6_DISP(op1, op2, disp) \
210 unsigned int __disp = (disp) & 0xfff; \
211 _EMIT6((op1) | __disp, op2); \
214 #define _EMIT6_DISP_LH(op1, op2, disp) \
216 u32 _disp = (u32) (disp); \
217 unsigned int __disp_h = _disp & 0xff000; \
218 unsigned int __disp_l = _disp & 0x00fff; \
219 _EMIT6((op1) | __disp_l, (op2) | __disp_h >> 4); \
222 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
224 _EMIT6_DISP_LH((op1) | reg(b1, b2) << 16 | \
225 reg_high(b3) << 8, op2, disp); \
231 #define EMIT6_PCREL_RIEB(op1, op2, b1, b2, mask, target) \
233 unsigned int rel = (int)((target) - jit->prg) / 2; \
234 _EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), \
235 (op2) | (mask) << 12); \
240 #define EMIT6_PCREL_RIEC(op1, op2, b1, imm, mask, target) \
242 unsigned int rel = (int)((target) - jit->prg) / 2; \
243 _EMIT6((op1) | (reg_high(b1) | (mask)) << 16 | \
244 (rel & 0xffff), (op2) | ((imm) & 0xff) << 8); \
246 BUILD_BUG_ON(((unsigned long) (imm)) > 0xff); \
249 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
251 int rel = (addrs[(i) + (off) + 1] - jit->prg) / 2; \
252 _EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), (op2) | (mask));\
257 #define EMIT6_PCREL_RILB(op, b, target) \
259 unsigned int rel = (int)((target) - jit->prg) / 2; \
260 _EMIT6((op) | reg_high(b) << 16 | rel >> 16, rel & 0xffff);\
264 #define EMIT6_PCREL_RIL(op, target) \
266 unsigned int rel = (int)((target) - jit->prg) / 2; \
267 _EMIT6((op) | rel >> 16, rel & 0xffff); \
270 #define EMIT6_PCREL_RILC(op, mask, target) \
272 EMIT6_PCREL_RIL((op) | (mask) << 20, (target)); \
275 #define _EMIT6_IMM(op, imm) \
277 unsigned int __imm = (imm); \
278 _EMIT6((op) | (__imm >> 16), __imm & 0xffff); \
281 #define EMIT6_IMM(op, b1, imm) \
283 _EMIT6_IMM((op) | reg_high(b1) << 16, imm); \
287 #define _EMIT_CONST_U32(val) \
292 *(u32 *)(jit->prg_buf + jit->lit32) = (u32)(val);\
297 #define EMIT_CONST_U32(val) \
299 jit->seen |= SEEN_LITERAL; \
300 _EMIT_CONST_U32(val) - jit->base_ip; \
303 #define _EMIT_CONST_U64(val) \
308 *(u64 *)(jit->prg_buf + jit->lit64) = (u64)(val);\
313 #define EMIT_CONST_U64(val) \
315 jit->seen |= SEEN_LITERAL; \
316 _EMIT_CONST_U64(val) - jit->base_ip; \
319 #define EMIT_ZERO(b1) \
321 if (!fp->aux->verifier_zext) { \
322 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
323 EMIT4(0xb9160000, b1, b1); \
329 * Return whether this is the first pass. The first pass is special, since we
330 * don't know any sizes yet, and thus must be conservative.
332 static bool is_first_pass(struct bpf_jit *jit)
334 return jit->size == 0;
338 * Return whether this is the code generation pass. The code generation pass is
339 * special, since we should change as little as possible.
341 static bool is_codegen_pass(struct bpf_jit *jit)
347 * Return whether "rel" can be encoded as a short PC-relative offset
349 static bool is_valid_rel(int rel)
351 return rel >= -65536 && rel <= 65534;
355 * Return whether "off" can be reached using a short PC-relative offset
357 static bool can_use_rel(struct bpf_jit *jit, int off)
359 return is_valid_rel(off - jit->prg);
363 * Return whether given displacement can be encoded using
364 * Long-Displacement Facility
366 static bool is_valid_ldisp(int disp)
368 return disp >= -524288 && disp <= 524287;
372 * Return whether the next 32-bit literal pool entry can be referenced using
373 * Long-Displacement Facility
375 static bool can_use_ldisp_for_lit32(struct bpf_jit *jit)
377 return is_valid_ldisp(jit->lit32 - jit->base_ip);
381 * Return whether the next 64-bit literal pool entry can be referenced using
382 * Long-Displacement Facility
384 static bool can_use_ldisp_for_lit64(struct bpf_jit *jit)
386 return is_valid_ldisp(jit->lit64 - jit->base_ip);
390 * Fill whole space with illegal instructions
392 static void jit_fill_hole(void *area, unsigned int size)
394 memset(area, 0, size);
398 * Save registers from "rs" (register start) to "re" (register end) on stack
400 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
402 u32 off = STK_OFF_R6 + (rs - 6) * 8;
405 /* stg %rs,off(%r15) */
406 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
408 /* stmg %rs,%re,off(%r15) */
409 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
413 * Restore registers from "rs" (register start) to "re" (register end) on stack
415 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re, u32 stack_depth)
417 u32 off = STK_OFF_R6 + (rs - 6) * 8;
419 if (jit->seen & SEEN_STACK)
420 off += STK_OFF + stack_depth;
423 /* lg %rs,off(%r15) */
424 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
426 /* lmg %rs,%re,off(%r15) */
427 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
431 * Return first seen register (from start)
433 static int get_start(struct bpf_jit *jit, int start)
437 for (i = start; i <= 15; i++) {
438 if (jit->seen_reg[i])
445 * Return last seen register (from start) (gap >= 2)
447 static int get_end(struct bpf_jit *jit, int start)
451 for (i = start; i < 15; i++) {
452 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
455 return jit->seen_reg[15] ? 15 : 14;
459 #define REGS_RESTORE 0
461 * Save and restore clobbered registers (6-15) on stack.
462 * We save/restore registers in chunks with gap >= 2 registers.
464 static void save_restore_regs(struct bpf_jit *jit, int op, u32 stack_depth)
466 const int last = 15, save_restore_size = 6;
469 if (is_first_pass(jit)) {
471 * We don't know yet which registers are used. Reserve space
474 jit->prg += (last - re + 1) * save_restore_size;
479 rs = get_start(jit, re);
482 re = get_end(jit, rs + 1);
484 save_regs(jit, rs, re);
486 restore_regs(jit, rs, re, stack_depth);
488 } while (re <= last);
491 static void bpf_skip(struct bpf_jit *jit, int size)
493 if (size >= 6 && !is_valid_rel(size)) {
495 EMIT6_PCREL_RIL(0xc0f4000000, size);
497 } else if (size >= 4 && is_valid_rel(size)) {
499 EMIT4_PCREL(0xa7f40000, size);
510 * Emit function prologue
512 * Save registers and create stack frame if necessary.
513 * See stack frame layout desription in "bpf_jit.h"!
515 static void bpf_jit_prologue(struct bpf_jit *jit, u32 stack_depth)
517 if (jit->seen & SEEN_TAIL_CALL) {
518 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
519 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
522 * There are no tail calls. Insert nops in order to have
523 * tail_call_start at a predictable offset.
527 /* Tail calls have to skip above initialization */
528 jit->tail_call_start = jit->prg;
530 save_restore_regs(jit, REGS_SAVE, stack_depth);
531 /* Setup literal pool */
532 if (is_first_pass(jit) || (jit->seen & SEEN_LITERAL)) {
533 if (!is_first_pass(jit) &&
534 is_valid_ldisp(jit->size - (jit->prg + 2))) {
536 EMIT2(0x0d00, REG_L, REG_0);
537 jit->base_ip = jit->prg;
539 /* larl %l,lit32_start */
540 EMIT6_PCREL_RILB(0xc0000000, REG_L, jit->lit32_start);
541 jit->base_ip = jit->lit32_start;
544 /* Setup stack and backchain */
545 if (is_first_pass(jit) || (jit->seen & SEEN_STACK)) {
546 if (is_first_pass(jit) || (jit->seen & SEEN_FUNC))
547 /* lgr %w1,%r15 (backchain) */
548 EMIT4(0xb9040000, REG_W1, REG_15);
549 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
550 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
551 /* aghi %r15,-STK_OFF */
552 EMIT4_IMM(0xa70b0000, REG_15, -(STK_OFF + stack_depth));
553 if (is_first_pass(jit) || (jit->seen & SEEN_FUNC))
554 /* stg %w1,152(%r15) (backchain) */
555 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
563 static void bpf_jit_epilogue(struct bpf_jit *jit, u32 stack_depth)
565 jit->exit_ip = jit->prg;
566 /* Load exit code: lgr %r2,%b0 */
567 EMIT4(0xb9040000, REG_2, BPF_REG_0);
568 /* Restore registers */
569 save_restore_regs(jit, REGS_RESTORE, stack_depth);
570 if (nospec_uses_trampoline()) {
571 jit->r14_thunk_ip = jit->prg;
572 /* Generate __s390_indirect_jump_r14 thunk */
573 if (test_facility(35)) {
575 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
578 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14);
580 EMIT4_DISP(0x44000000, REG_0, REG_1, 0);
583 EMIT4_PCREL(0xa7f40000, 0);
588 if ((nospec_uses_trampoline()) &&
589 (is_first_pass(jit) || (jit->seen & SEEN_FUNC))) {
590 jit->r1_thunk_ip = jit->prg;
591 /* Generate __s390_indirect_jump_r1 thunk */
592 if (test_facility(35)) {
594 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
596 EMIT4_PCREL(0xa7f40000, 0);
600 /* ex 0,S390_lowcore.br_r1_tampoline */
601 EMIT4_DISP(0x44000000, REG_0, REG_0,
602 offsetof(struct lowcore, br_r1_trampoline));
604 EMIT4_PCREL(0xa7f40000, 0);
609 static int get_probe_mem_regno(const u8 *insn)
612 * insn must point to llgc, llgh, llgf or lg, which have destination
613 * register at the same position.
615 if (insn[0] != 0xe3) /* common llgc, llgh, llgf and lg prefix */
617 if (insn[5] != 0x90 && /* llgc */
618 insn[5] != 0x91 && /* llgh */
619 insn[5] != 0x16 && /* llgf */
620 insn[5] != 0x04) /* lg */
625 static bool ex_handler_bpf(const struct exception_table_entry *x,
626 struct pt_regs *regs)
631 regs->psw.addr = extable_fixup(x);
632 insn = (u8 *)__rewind_psw(regs->psw, regs->int_code >> 16);
633 regno = get_probe_mem_regno(insn);
634 if (WARN_ON_ONCE(regno < 0))
635 /* JIT bug - unexpected instruction. */
637 regs->gprs[regno] = 0;
641 static int bpf_jit_probe_mem(struct bpf_jit *jit, struct bpf_prog *fp,
642 int probe_prg, int nop_prg)
644 struct exception_table_entry *ex;
650 if (!fp->aux->extable)
651 /* Do nothing during early JIT passes. */
653 insn = jit->prg_buf + probe_prg;
654 if (WARN_ON_ONCE(get_probe_mem_regno(insn) < 0))
655 /* JIT bug - unexpected probe instruction. */
657 if (WARN_ON_ONCE(probe_prg + insn_length(*insn) != nop_prg))
658 /* JIT bug - gap between probe and nop instructions. */
660 for (i = 0; i < 2; i++) {
661 if (WARN_ON_ONCE(jit->excnt >= fp->aux->num_exentries))
662 /* Verifier bug - not enough entries. */
664 ex = &fp->aux->extable[jit->excnt];
665 /* Add extable entries for probe and nop instructions. */
666 prg = i == 0 ? probe_prg : nop_prg;
667 delta = jit->prg_buf + prg - (u8 *)&ex->insn;
668 if (WARN_ON_ONCE(delta < INT_MIN || delta > INT_MAX))
669 /* JIT bug - code and extable must be close. */
673 * Always land on the nop. Note that extable infrastructure
674 * ignores fixup field, it is handled by ex_handler_bpf().
676 delta = jit->prg_buf + nop_prg - (u8 *)&ex->fixup;
677 if (WARN_ON_ONCE(delta < INT_MIN || delta > INT_MAX))
678 /* JIT bug - landing pad and extable must be close. */
681 ex->handler = (u8 *)ex_handler_bpf - (u8 *)&ex->handler;
688 * Compile one eBPF instruction into s390x code
690 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
691 * stack space for the large switch statement.
693 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp,
694 int i, bool extra_pass, u32 stack_depth)
696 struct bpf_insn *insn = &fp->insnsi[i];
697 u32 dst_reg = insn->dst_reg;
698 u32 src_reg = insn->src_reg;
699 int last, insn_count = 1;
700 u32 *addrs = jit->addrs;
708 if (BPF_CLASS(insn->code) == BPF_LDX &&
709 BPF_MODE(insn->code) == BPF_PROBE_MEM)
710 probe_prg = jit->prg;
712 switch (insn->code) {
716 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
717 /* llgfr %dst,%src */
718 EMIT4(0xb9160000, dst_reg, src_reg);
719 if (insn_is_zext(&insn[1]))
722 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
724 EMIT4(0xb9040000, dst_reg, src_reg);
726 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
728 EMIT6_IMM(0xc00f0000, dst_reg, imm);
729 if (insn_is_zext(&insn[1]))
732 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
734 EMIT6_IMM(0xc0010000, dst_reg, imm);
739 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
741 /* 16 byte instruction that uses two 'struct bpf_insn' */
744 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
746 EMIT6_PCREL_RILB(0xc4080000, dst_reg, _EMIT_CONST_U64(imm64));
753 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
755 EMIT2(0x1a00, dst_reg, src_reg);
758 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
760 EMIT4(0xb9080000, dst_reg, src_reg);
762 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
765 EMIT6_IMM(0xc20b0000, dst_reg, imm);
769 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
773 EMIT6_IMM(0xc2080000, dst_reg, imm);
778 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
780 EMIT2(0x1b00, dst_reg, src_reg);
783 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
785 EMIT4(0xb9090000, dst_reg, src_reg);
787 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
790 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
794 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
797 if (imm == -0x80000000) {
798 /* algfi %dst,0x80000000 */
799 EMIT6_IMM(0xc20a0000, dst_reg, 0x80000000);
802 EMIT6_IMM(0xc2080000, dst_reg, -imm);
808 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
810 EMIT4(0xb2520000, dst_reg, src_reg);
813 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
815 EMIT4(0xb90c0000, dst_reg, src_reg);
817 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
820 EMIT6_IMM(0xc2010000, dst_reg, imm);
824 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
828 EMIT6_IMM(0xc2000000, dst_reg, imm);
833 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
834 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
836 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
839 EMIT4_IMM(0xa7080000, REG_W0, 0);
841 EMIT2(0x1800, REG_W1, dst_reg);
843 EMIT4(0xb9970000, REG_W0, src_reg);
845 EMIT4(0xb9160000, dst_reg, rc_reg);
846 if (insn_is_zext(&insn[1]))
850 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
851 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
853 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
856 EMIT4_IMM(0xa7090000, REG_W0, 0);
858 EMIT4(0xb9040000, REG_W1, dst_reg);
860 EMIT4(0xb9870000, REG_W0, src_reg);
862 EMIT4(0xb9040000, dst_reg, rc_reg);
865 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
866 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
868 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
871 if (BPF_OP(insn->code) == BPF_MOD)
873 EMIT4_IMM(0xa7090000, dst_reg, 0);
879 EMIT4_IMM(0xa7080000, REG_W0, 0);
881 EMIT2(0x1800, REG_W1, dst_reg);
882 if (!is_first_pass(jit) && can_use_ldisp_for_lit32(jit)) {
883 /* dl %w0,<d(imm)>(%l) */
884 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
885 EMIT_CONST_U32(imm));
888 EMIT6_PCREL_RILB(0xc40c0000, dst_reg,
889 _EMIT_CONST_U32(imm));
890 jit->seen |= SEEN_LITERAL;
892 EMIT4(0xb9970000, REG_W0, dst_reg);
895 EMIT4(0xb9160000, dst_reg, rc_reg);
896 if (insn_is_zext(&insn[1]))
900 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
901 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
903 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
906 if (BPF_OP(insn->code) == BPF_MOD)
908 EMIT4_IMM(0xa7090000, dst_reg, 0);
912 EMIT4_IMM(0xa7090000, REG_W0, 0);
914 EMIT4(0xb9040000, REG_W1, dst_reg);
915 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
916 /* dlg %w0,<d(imm)>(%l) */
917 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
918 EMIT_CONST_U64(imm));
921 EMIT6_PCREL_RILB(0xc4080000, dst_reg,
922 _EMIT_CONST_U64(imm));
923 jit->seen |= SEEN_LITERAL;
925 EMIT4(0xb9870000, REG_W0, dst_reg);
928 EMIT4(0xb9040000, dst_reg, rc_reg);
934 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
936 EMIT2(0x1400, dst_reg, src_reg);
939 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
941 EMIT4(0xb9800000, dst_reg, src_reg);
943 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
945 EMIT6_IMM(0xc00b0000, dst_reg, imm);
948 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
949 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
950 /* ng %dst,<d(imm)>(%l) */
951 EMIT6_DISP_LH(0xe3000000, 0x0080,
952 dst_reg, REG_0, REG_L,
953 EMIT_CONST_U64(imm));
956 EMIT6_PCREL_RILB(0xc4080000, REG_W0,
957 _EMIT_CONST_U64(imm));
958 jit->seen |= SEEN_LITERAL;
960 EMIT4(0xb9800000, dst_reg, REG_W0);
966 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
968 EMIT2(0x1600, dst_reg, src_reg);
971 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
973 EMIT4(0xb9810000, dst_reg, src_reg);
975 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
977 EMIT6_IMM(0xc00d0000, dst_reg, imm);
980 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
981 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
982 /* og %dst,<d(imm)>(%l) */
983 EMIT6_DISP_LH(0xe3000000, 0x0081,
984 dst_reg, REG_0, REG_L,
985 EMIT_CONST_U64(imm));
988 EMIT6_PCREL_RILB(0xc4080000, REG_W0,
989 _EMIT_CONST_U64(imm));
990 jit->seen |= SEEN_LITERAL;
992 EMIT4(0xb9810000, dst_reg, REG_W0);
998 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
1000 EMIT2(0x1700, dst_reg, src_reg);
1003 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
1005 EMIT4(0xb9820000, dst_reg, src_reg);
1007 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
1010 EMIT6_IMM(0xc0070000, dst_reg, imm);
1014 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
1015 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
1016 /* xg %dst,<d(imm)>(%l) */
1017 EMIT6_DISP_LH(0xe3000000, 0x0082,
1018 dst_reg, REG_0, REG_L,
1019 EMIT_CONST_U64(imm));
1022 EMIT6_PCREL_RILB(0xc4080000, REG_W0,
1023 _EMIT_CONST_U64(imm));
1024 jit->seen |= SEEN_LITERAL;
1026 EMIT4(0xb9820000, dst_reg, REG_W0);
1032 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
1033 /* sll %dst,0(%src) */
1034 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
1037 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
1038 /* sllg %dst,%dst,0(%src) */
1039 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
1041 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
1043 /* sll %dst,imm(%r0) */
1044 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
1048 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
1051 /* sllg %dst,%dst,imm(%r0) */
1052 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
1057 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
1058 /* srl %dst,0(%src) */
1059 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
1062 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
1063 /* srlg %dst,%dst,0(%src) */
1064 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
1066 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
1068 /* srl %dst,imm(%r0) */
1069 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
1073 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
1076 /* srlg %dst,%dst,imm(%r0) */
1077 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
1082 case BPF_ALU | BPF_ARSH | BPF_X: /* ((s32) dst) >>= src */
1083 /* sra %dst,%dst,0(%src) */
1084 EMIT4_DISP(0x8a000000, dst_reg, src_reg, 0);
1087 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
1088 /* srag %dst,%dst,0(%src) */
1089 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
1091 case BPF_ALU | BPF_ARSH | BPF_K: /* ((s32) dst >> imm */
1093 /* sra %dst,imm(%r0) */
1094 EMIT4_DISP(0x8a000000, dst_reg, REG_0, imm);
1098 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
1101 /* srag %dst,%dst,imm(%r0) */
1102 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
1107 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
1109 EMIT2(0x1300, dst_reg, dst_reg);
1112 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
1113 /* lcgr %dst,%dst */
1114 EMIT4(0xb9030000, dst_reg, dst_reg);
1119 case BPF_ALU | BPF_END | BPF_FROM_BE:
1120 /* s390 is big endian, therefore only clear high order bytes */
1122 case 16: /* dst = (u16) cpu_to_be16(dst) */
1123 /* llghr %dst,%dst */
1124 EMIT4(0xb9850000, dst_reg, dst_reg);
1125 if (insn_is_zext(&insn[1]))
1128 case 32: /* dst = (u32) cpu_to_be32(dst) */
1129 if (!fp->aux->verifier_zext)
1130 /* llgfr %dst,%dst */
1131 EMIT4(0xb9160000, dst_reg, dst_reg);
1133 case 64: /* dst = (u64) cpu_to_be64(dst) */
1137 case BPF_ALU | BPF_END | BPF_FROM_LE:
1139 case 16: /* dst = (u16) cpu_to_le16(dst) */
1140 /* lrvr %dst,%dst */
1141 EMIT4(0xb91f0000, dst_reg, dst_reg);
1142 /* srl %dst,16(%r0) */
1143 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
1144 /* llghr %dst,%dst */
1145 EMIT4(0xb9850000, dst_reg, dst_reg);
1146 if (insn_is_zext(&insn[1]))
1149 case 32: /* dst = (u32) cpu_to_le32(dst) */
1150 /* lrvr %dst,%dst */
1151 EMIT4(0xb91f0000, dst_reg, dst_reg);
1152 if (!fp->aux->verifier_zext)
1153 /* llgfr %dst,%dst */
1154 EMIT4(0xb9160000, dst_reg, dst_reg);
1156 case 64: /* dst = (u64) cpu_to_le64(dst) */
1157 /* lrvgr %dst,%dst */
1158 EMIT4(0xb90f0000, dst_reg, dst_reg);
1163 * BPF_NOSPEC (speculation barrier)
1165 case BPF_ST | BPF_NOSPEC:
1170 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
1171 /* stcy %src,off(%dst) */
1172 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
1173 jit->seen |= SEEN_MEM;
1175 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
1176 /* sthy %src,off(%dst) */
1177 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
1178 jit->seen |= SEEN_MEM;
1180 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
1181 /* sty %src,off(%dst) */
1182 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
1183 jit->seen |= SEEN_MEM;
1185 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
1186 /* stg %src,off(%dst) */
1187 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
1188 jit->seen |= SEEN_MEM;
1190 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
1192 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
1193 /* stcy %w0,off(dst) */
1194 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
1195 jit->seen |= SEEN_MEM;
1197 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
1199 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
1200 /* sthy %w0,off(dst) */
1201 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
1202 jit->seen |= SEEN_MEM;
1204 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
1206 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
1207 /* sty %w0,off(%dst) */
1208 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
1209 jit->seen |= SEEN_MEM;
1211 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
1213 EMIT6_IMM(0xc0010000, REG_W0, imm);
1214 /* stg %w0,off(%dst) */
1215 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
1216 jit->seen |= SEEN_MEM;
1221 case BPF_STX | BPF_ATOMIC | BPF_DW:
1222 case BPF_STX | BPF_ATOMIC | BPF_W:
1224 bool is32 = BPF_SIZE(insn->code) == BPF_W;
1226 switch (insn->imm) {
1227 /* {op32|op64} {%w0|%src},%src,off(%dst) */
1228 #define EMIT_ATOMIC(op32, op64) do { \
1229 EMIT6_DISP_LH(0xeb000000, is32 ? (op32) : (op64), \
1230 (insn->imm & BPF_FETCH) ? src_reg : REG_W0, \
1231 src_reg, dst_reg, off); \
1232 if (is32 && (insn->imm & BPF_FETCH)) \
1233 EMIT_ZERO(src_reg); \
1236 case BPF_ADD | BPF_FETCH:
1238 EMIT_ATOMIC(0x00fa, 0x00ea);
1241 case BPF_AND | BPF_FETCH:
1243 EMIT_ATOMIC(0x00f4, 0x00e4);
1246 case BPF_OR | BPF_FETCH:
1248 EMIT_ATOMIC(0x00f6, 0x00e6);
1251 case BPF_XOR | BPF_FETCH:
1253 EMIT_ATOMIC(0x00f7, 0x00e7);
1257 /* {ly|lg} %w0,off(%dst) */
1258 EMIT6_DISP_LH(0xe3000000,
1259 is32 ? 0x0058 : 0x0004, REG_W0, REG_0,
1261 /* 0: {csy|csg} %w0,%src,off(%dst) */
1262 EMIT6_DISP_LH(0xeb000000, is32 ? 0x0014 : 0x0030,
1263 REG_W0, src_reg, dst_reg, off);
1265 EMIT4_PCREL_RIC(0xa7040000, 4, jit->prg - 6);
1266 /* {llgfr|lgr} %src,%w0 */
1267 EMIT4(is32 ? 0xb9160000 : 0xb9040000, src_reg, REG_W0);
1268 if (is32 && insn_is_zext(&insn[1]))
1272 /* 0: {csy|csg} %b0,%src,off(%dst) */
1273 EMIT6_DISP_LH(0xeb000000, is32 ? 0x0014 : 0x0030,
1274 BPF_REG_0, src_reg, dst_reg, off);
1277 pr_err("Unknown atomic operation %02x\n", insn->imm);
1281 jit->seen |= SEEN_MEM;
1287 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
1288 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
1289 /* llgc %dst,0(off,%src) */
1290 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
1291 jit->seen |= SEEN_MEM;
1292 if (insn_is_zext(&insn[1]))
1295 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
1296 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
1297 /* llgh %dst,0(off,%src) */
1298 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
1299 jit->seen |= SEEN_MEM;
1300 if (insn_is_zext(&insn[1]))
1303 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
1304 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
1305 /* llgf %dst,off(%src) */
1306 jit->seen |= SEEN_MEM;
1307 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
1308 if (insn_is_zext(&insn[1]))
1311 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
1312 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
1313 /* lg %dst,0(off,%src) */
1314 jit->seen |= SEEN_MEM;
1315 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
1320 case BPF_JMP | BPF_CALL:
1323 bool func_addr_fixed;
1326 ret = bpf_jit_get_func_addr(fp, insn, extra_pass,
1327 &func, &func_addr_fixed);
1331 REG_SET_SEEN(BPF_REG_5);
1332 jit->seen |= SEEN_FUNC;
1334 EMIT6_PCREL_RILB(0xc4080000, REG_W1, _EMIT_CONST_U64(func));
1335 if (nospec_uses_trampoline()) {
1336 /* brasl %r14,__s390_indirect_jump_r1 */
1337 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip);
1340 EMIT2(0x0d00, REG_14, REG_W1);
1342 /* lgr %b0,%r2: load return value into %b0 */
1343 EMIT4(0xb9040000, BPF_REG_0, REG_2);
1346 case BPF_JMP | BPF_TAIL_CALL: {
1347 int patch_1_clrj, patch_2_clij, patch_3_brc;
1351 * B1: pointer to ctx
1352 * B2: pointer to bpf_array
1353 * B3: index in bpf_array
1355 jit->seen |= SEEN_TAIL_CALL;
1358 * if (index >= array->map.max_entries)
1362 /* llgf %w1,map.max_entries(%b2) */
1363 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
1364 offsetof(struct bpf_array, map.max_entries));
1365 /* if ((u32)%b3 >= (u32)%w1) goto out; */
1366 /* clrj %b3,%w1,0xa,out */
1367 patch_1_clrj = jit->prg;
1368 EMIT6_PCREL_RIEB(0xec000000, 0x0077, BPF_REG_3, REG_W1, 0xa,
1372 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
1376 if (jit->seen & SEEN_STACK)
1377 off = STK_OFF_TCCNT + STK_OFF + stack_depth;
1379 off = STK_OFF_TCCNT;
1381 EMIT4_IMM(0xa7080000, REG_W0, 1);
1382 /* laal %w1,%w0,off(%r15) */
1383 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1384 /* clij %w1,MAX_TAIL_CALL_CNT-1,0x2,out */
1385 patch_2_clij = jit->prg;
1386 EMIT6_PCREL_RIEC(0xec000000, 0x007f, REG_W1, MAX_TAIL_CALL_CNT - 1,
1390 * prog = array->ptrs[index];
1395 /* llgfr %r1,%b3: %r1 = (u32) index */
1396 EMIT4(0xb9160000, REG_1, BPF_REG_3);
1397 /* sllg %r1,%r1,3: %r1 *= 8 */
1398 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, REG_1, REG_0, 3);
1399 /* ltg %r1,prog(%b2,%r1) */
1400 EMIT6_DISP_LH(0xe3000000, 0x0002, REG_1, BPF_REG_2,
1401 REG_1, offsetof(struct bpf_array, ptrs));
1403 patch_3_brc = jit->prg;
1404 EMIT4_PCREL_RIC(0xa7040000, 8, jit->prg);
1407 * Restore registers before calling function
1409 save_restore_regs(jit, REGS_RESTORE, stack_depth);
1412 * goto *(prog->bpf_func + tail_call_start);
1415 /* lg %r1,bpf_func(%r1) */
1416 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1417 offsetof(struct bpf_prog, bpf_func));
1418 /* bc 0xf,tail_call_start(%r1) */
1419 _EMIT4(0x47f01000 + jit->tail_call_start);
1422 *(u16 *)(jit->prg_buf + patch_1_clrj + 2) =
1423 (jit->prg - patch_1_clrj) >> 1;
1424 *(u16 *)(jit->prg_buf + patch_2_clij + 2) =
1425 (jit->prg - patch_2_clij) >> 1;
1426 *(u16 *)(jit->prg_buf + patch_3_brc + 2) =
1427 (jit->prg - patch_3_brc) >> 1;
1431 case BPF_JMP | BPF_EXIT: /* return b0 */
1432 last = (i == fp->len - 1) ? 1 : 0;
1435 if (!is_first_pass(jit) && can_use_rel(jit, jit->exit_ip))
1436 /* brc 0xf, <exit> */
1437 EMIT4_PCREL_RIC(0xa7040000, 0xf, jit->exit_ip);
1439 /* brcl 0xf, <exit> */
1440 EMIT6_PCREL_RILC(0xc0040000, 0xf, jit->exit_ip);
1443 * Branch relative (number of skipped instructions) to offset on
1446 * Condition code to mask mapping:
1448 * CC | Description | Mask
1449 * ------------------------------
1450 * 0 | Operands equal | 8
1451 * 1 | First operand low | 4
1452 * 2 | First operand high | 2
1455 * For s390x relative branches: ip = ip + off_bytes
1456 * For BPF relative branches: insn = insn + off_insns + 1
1458 * For example for s390x with offset 0 we jump to the branch
1459 * instruction itself (loop) and for BPF with offset 0 we
1460 * branch to the instruction behind the branch.
1462 case BPF_JMP | BPF_JA: /* if (true) */
1463 mask = 0xf000; /* j */
1465 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1466 case BPF_JMP32 | BPF_JSGT | BPF_K: /* ((s32) dst > (s32) imm) */
1467 mask = 0x2000; /* jh */
1469 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */
1470 case BPF_JMP32 | BPF_JSLT | BPF_K: /* ((s32) dst < (s32) imm) */
1471 mask = 0x4000; /* jl */
1473 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1474 case BPF_JMP32 | BPF_JSGE | BPF_K: /* ((s32) dst >= (s32) imm) */
1475 mask = 0xa000; /* jhe */
1477 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */
1478 case BPF_JMP32 | BPF_JSLE | BPF_K: /* ((s32) dst <= (s32) imm) */
1479 mask = 0xc000; /* jle */
1481 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1482 case BPF_JMP32 | BPF_JGT | BPF_K: /* ((u32) dst_reg > (u32) imm) */
1483 mask = 0x2000; /* jh */
1485 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */
1486 case BPF_JMP32 | BPF_JLT | BPF_K: /* ((u32) dst_reg < (u32) imm) */
1487 mask = 0x4000; /* jl */
1489 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1490 case BPF_JMP32 | BPF_JGE | BPF_K: /* ((u32) dst_reg >= (u32) imm) */
1491 mask = 0xa000; /* jhe */
1493 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */
1494 case BPF_JMP32 | BPF_JLE | BPF_K: /* ((u32) dst_reg <= (u32) imm) */
1495 mask = 0xc000; /* jle */
1497 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1498 case BPF_JMP32 | BPF_JNE | BPF_K: /* ((u32) dst_reg != (u32) imm) */
1499 mask = 0x7000; /* jne */
1501 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1502 case BPF_JMP32 | BPF_JEQ | BPF_K: /* ((u32) dst_reg == (u32) imm) */
1503 mask = 0x8000; /* je */
1505 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1506 case BPF_JMP32 | BPF_JSET | BPF_K: /* ((u32) dst_reg & (u32) imm) */
1507 mask = 0x7000; /* jnz */
1508 if (BPF_CLASS(insn->code) == BPF_JMP32) {
1509 /* llilf %w1,imm (load zero extend imm) */
1510 EMIT6_IMM(0xc00f0000, REG_W1, imm);
1512 EMIT2(0x1400, REG_W1, dst_reg);
1514 /* lgfi %w1,imm (load sign extend imm) */
1515 EMIT6_IMM(0xc0010000, REG_W1, imm);
1517 EMIT4(0xb9800000, REG_W1, dst_reg);
1521 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1522 case BPF_JMP32 | BPF_JSGT | BPF_X: /* ((s32) dst > (s32) src) */
1523 mask = 0x2000; /* jh */
1525 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */
1526 case BPF_JMP32 | BPF_JSLT | BPF_X: /* ((s32) dst < (s32) src) */
1527 mask = 0x4000; /* jl */
1529 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1530 case BPF_JMP32 | BPF_JSGE | BPF_X: /* ((s32) dst >= (s32) src) */
1531 mask = 0xa000; /* jhe */
1533 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */
1534 case BPF_JMP32 | BPF_JSLE | BPF_X: /* ((s32) dst <= (s32) src) */
1535 mask = 0xc000; /* jle */
1537 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1538 case BPF_JMP32 | BPF_JGT | BPF_X: /* ((u32) dst > (u32) src) */
1539 mask = 0x2000; /* jh */
1541 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */
1542 case BPF_JMP32 | BPF_JLT | BPF_X: /* ((u32) dst < (u32) src) */
1543 mask = 0x4000; /* jl */
1545 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1546 case BPF_JMP32 | BPF_JGE | BPF_X: /* ((u32) dst >= (u32) src) */
1547 mask = 0xa000; /* jhe */
1549 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */
1550 case BPF_JMP32 | BPF_JLE | BPF_X: /* ((u32) dst <= (u32) src) */
1551 mask = 0xc000; /* jle */
1553 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1554 case BPF_JMP32 | BPF_JNE | BPF_X: /* ((u32) dst != (u32) src) */
1555 mask = 0x7000; /* jne */
1557 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1558 case BPF_JMP32 | BPF_JEQ | BPF_X: /* ((u32) dst == (u32) src) */
1559 mask = 0x8000; /* je */
1561 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1562 case BPF_JMP32 | BPF_JSET | BPF_X: /* ((u32) dst & (u32) src) */
1564 bool is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1566 mask = 0x7000; /* jnz */
1567 /* nrk or ngrk %w1,%dst,%src */
1568 EMIT4_RRF((is_jmp32 ? 0xb9f40000 : 0xb9e40000),
1569 REG_W1, dst_reg, src_reg);
1572 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1573 /* cfi or cgfi %dst,imm */
1574 EMIT6_IMM(is_jmp32 ? 0xc20d0000 : 0xc20c0000,
1576 if (!is_first_pass(jit) &&
1577 can_use_rel(jit, addrs[i + off + 1])) {
1579 EMIT4_PCREL_RIC(0xa7040000,
1580 mask >> 12, addrs[i + off + 1]);
1583 EMIT6_PCREL_RILC(0xc0040000,
1584 mask >> 12, addrs[i + off + 1]);
1588 /* lgfi %w1,imm (load sign extend imm) */
1590 EMIT6_IMM(0xc0010000, src_reg, imm);
1593 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1594 if (!is_first_pass(jit) &&
1595 can_use_rel(jit, addrs[i + off + 1])) {
1596 /* crj or cgrj %dst,%src,mask,off */
1597 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0076 : 0x0064),
1598 dst_reg, src_reg, i, off, mask);
1600 /* cr or cgr %dst,%src */
1602 EMIT2(0x1900, dst_reg, src_reg);
1604 EMIT4(0xb9200000, dst_reg, src_reg);
1606 EMIT6_PCREL_RILC(0xc0040000,
1607 mask >> 12, addrs[i + off + 1]);
1611 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1612 if (!is_first_pass(jit) &&
1613 can_use_rel(jit, addrs[i + off + 1])) {
1614 /* clrj or clgrj %dst,%src,mask,off */
1615 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0077 : 0x0065),
1616 dst_reg, src_reg, i, off, mask);
1618 /* clr or clgr %dst,%src */
1620 EMIT2(0x1500, dst_reg, src_reg);
1622 EMIT4(0xb9210000, dst_reg, src_reg);
1624 EMIT6_PCREL_RILC(0xc0040000,
1625 mask >> 12, addrs[i + off + 1]);
1629 if (!is_first_pass(jit) &&
1630 can_use_rel(jit, addrs[i + off + 1])) {
1632 EMIT4_PCREL_RIC(0xa7040000,
1633 mask >> 12, addrs[i + off + 1]);
1636 EMIT6_PCREL_RILC(0xc0040000,
1637 mask >> 12, addrs[i + off + 1]);
1641 default: /* too complex, give up */
1642 pr_err("Unknown opcode %02x\n", insn->code);
1646 if (probe_prg != -1) {
1648 * Handlers of certain exceptions leave psw.addr pointing to
1649 * the instruction directly after the failing one. Therefore,
1650 * create two exception table entries and also add a nop in
1651 * case two probing instructions come directly after each
1657 err = bpf_jit_probe_mem(jit, fp, probe_prg, nop_prg);
1666 * Return whether new i-th instruction address does not violate any invariant
1668 static bool bpf_is_new_addr_sane(struct bpf_jit *jit, int i)
1670 /* On the first pass anything goes */
1671 if (is_first_pass(jit))
1674 /* The codegen pass must not change anything */
1675 if (is_codegen_pass(jit))
1676 return jit->addrs[i] == jit->prg;
1678 /* Passes in between must not increase code size */
1679 return jit->addrs[i] >= jit->prg;
1683 * Update the address of i-th instruction
1685 static int bpf_set_addr(struct bpf_jit *jit, int i)
1689 if (is_codegen_pass(jit)) {
1690 delta = jit->prg - jit->addrs[i];
1692 bpf_skip(jit, -delta);
1694 if (WARN_ON_ONCE(!bpf_is_new_addr_sane(jit, i)))
1696 jit->addrs[i] = jit->prg;
1701 * Compile eBPF program into s390x code
1703 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp,
1704 bool extra_pass, u32 stack_depth)
1706 int i, insn_count, lit32_size, lit64_size;
1708 jit->lit32 = jit->lit32_start;
1709 jit->lit64 = jit->lit64_start;
1713 bpf_jit_prologue(jit, stack_depth);
1714 if (bpf_set_addr(jit, 0) < 0)
1716 for (i = 0; i < fp->len; i += insn_count) {
1717 insn_count = bpf_jit_insn(jit, fp, i, extra_pass, stack_depth);
1720 /* Next instruction address */
1721 if (bpf_set_addr(jit, i + insn_count) < 0)
1724 bpf_jit_epilogue(jit, stack_depth);
1726 lit32_size = jit->lit32 - jit->lit32_start;
1727 lit64_size = jit->lit64 - jit->lit64_start;
1728 jit->lit32_start = jit->prg;
1730 jit->lit32_start = ALIGN(jit->lit32_start, 4);
1731 jit->lit64_start = jit->lit32_start + lit32_size;
1733 jit->lit64_start = ALIGN(jit->lit64_start, 8);
1734 jit->size = jit->lit64_start + lit64_size;
1735 jit->size_prg = jit->prg;
1737 if (WARN_ON_ONCE(fp->aux->extable &&
1738 jit->excnt != fp->aux->num_exentries))
1739 /* Verifier bug - too many entries. */
1745 bool bpf_jit_needs_zext(void)
1750 struct s390_jit_data {
1751 struct bpf_binary_header *header;
1756 static struct bpf_binary_header *bpf_jit_alloc(struct bpf_jit *jit,
1757 struct bpf_prog *fp)
1759 struct bpf_binary_header *header;
1763 /* We need two entries per insn. */
1764 fp->aux->num_exentries *= 2;
1766 code_size = roundup(jit->size,
1767 __alignof__(struct exception_table_entry));
1768 extable_size = fp->aux->num_exentries *
1769 sizeof(struct exception_table_entry);
1770 header = bpf_jit_binary_alloc(code_size + extable_size, &jit->prg_buf,
1774 fp->aux->extable = (struct exception_table_entry *)
1775 (jit->prg_buf + code_size);
1780 * Compile eBPF program "fp"
1782 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
1784 u32 stack_depth = round_up(fp->aux->stack_depth, 8);
1785 struct bpf_prog *tmp, *orig_fp = fp;
1786 struct bpf_binary_header *header;
1787 struct s390_jit_data *jit_data;
1788 bool tmp_blinded = false;
1789 bool extra_pass = false;
1793 if (!fp->jit_requested)
1796 tmp = bpf_jit_blind_constants(fp);
1798 * If blinding was requested and we failed during blinding,
1799 * we must fall back to the interpreter.
1808 jit_data = fp->aux->jit_data;
1810 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
1815 fp->aux->jit_data = jit_data;
1817 if (jit_data->ctx.addrs) {
1818 jit = jit_data->ctx;
1819 header = jit_data->header;
1821 pass = jit_data->pass + 1;
1825 memset(&jit, 0, sizeof(jit));
1826 jit.addrs = kvcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1827 if (jit.addrs == NULL) {
1832 * Three initial passes:
1833 * - 1/2: Determine clobbered registers
1834 * - 3: Calculate program size and addrs arrray
1836 for (pass = 1; pass <= 3; pass++) {
1837 if (bpf_jit_prog(&jit, fp, extra_pass, stack_depth)) {
1843 * Final pass: Allocate and generate program
1845 header = bpf_jit_alloc(&jit, fp);
1851 if (bpf_jit_prog(&jit, fp, extra_pass, stack_depth)) {
1852 bpf_jit_binary_free(header);
1856 if (bpf_jit_enable > 1) {
1857 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1858 print_fn_code(jit.prg_buf, jit.size_prg);
1860 if (!fp->is_func || extra_pass) {
1861 bpf_jit_binary_lock_ro(header);
1863 jit_data->header = header;
1864 jit_data->ctx = jit;
1865 jit_data->pass = pass;
1867 fp->bpf_func = (void *) jit.prg_buf;
1869 fp->jited_len = jit.size;
1871 if (!fp->is_func || extra_pass) {
1872 bpf_prog_fill_jited_linfo(fp, jit.addrs + 1);
1876 fp->aux->jit_data = NULL;
1880 bpf_jit_prog_release_other(fp, fp == orig_fp ?