1 // SPDX-License-Identifier: GPL-2.0
3 * BPF Jit compiler for s390.
5 * Minimum build requirements:
7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
13 * Copyright IBM Corp. 2012,2015
15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
16 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
19 #define KMSG_COMPONENT "bpf_jit"
20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
22 #include <linux/netdevice.h>
23 #include <linux/filter.h>
24 #include <linux/init.h>
25 #include <linux/bpf.h>
27 #include <linux/kernel.h>
28 #include <asm/cacheflush.h>
30 #include <asm/facility.h>
31 #include <asm/nospec-branch.h>
32 #include <asm/set_memory.h>
36 u32 seen; /* Flags to remember seen eBPF instructions */
37 u32 seen_reg[16]; /* Array to remember which registers are used */
38 u32 *addrs; /* Array with relative instruction addresses */
39 u8 *prg_buf; /* Start of program */
40 int size; /* Size of program and literal pool */
41 int size_prg; /* Size of program */
42 int prg; /* Current position in program */
43 int lit32_start; /* Start of 32-bit literal pool */
44 int lit32; /* Current position in 32-bit literal pool */
45 int lit64_start; /* Start of 64-bit literal pool */
46 int lit64; /* Current position in 64-bit literal pool */
47 int base_ip; /* Base address for literal pool */
48 int exit_ip; /* Address of exit */
49 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */
50 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */
51 int tail_call_start; /* Tail call start offset */
52 int excnt; /* Number of exception table entries */
53 int labels[1]; /* Labels for local jumps */
56 #define SEEN_MEM BIT(0) /* use mem[] for temporary storage */
57 #define SEEN_LITERAL BIT(1) /* code uses literals */
58 #define SEEN_FUNC BIT(2) /* calls C functions */
59 #define SEEN_TAIL_CALL BIT(3) /* code uses tail calls */
60 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM)
65 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
66 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */
67 #define REG_L (MAX_BPF_JIT_REG + 2) /* Literal pool register */
68 #define REG_15 (MAX_BPF_JIT_REG + 3) /* Register 15 */
69 #define REG_0 REG_W0 /* Register 0 */
70 #define REG_1 REG_W1 /* Register 1 */
71 #define REG_2 BPF_REG_1 /* Register 2 */
72 #define REG_14 BPF_REG_0 /* Register 14 */
75 * Mapping of BPF registers to s390 registers
77 static const int reg2hex[] = {
80 /* Function parameters */
86 /* Call saved registers */
91 /* BPF stack pointer */
93 /* Register for blinding */
95 /* Work registers for s390x backend */
102 static inline u32 reg(u32 dst_reg, u32 src_reg)
104 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
107 static inline u32 reg_high(u32 reg)
109 return reg2hex[reg] << 4;
112 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
114 u32 r1 = reg2hex[b1];
116 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15)
117 jit->seen_reg[r1] = 1;
120 #define REG_SET_SEEN(b1) \
122 reg_set_seen(jit, b1); \
125 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
128 * EMIT macros for code generation
134 *(u16 *) (jit->prg_buf + jit->prg) = (op); \
138 #define EMIT2(op, b1, b2) \
140 _EMIT2((op) | reg(b1, b2)); \
148 *(u32 *) (jit->prg_buf + jit->prg) = (op); \
152 #define EMIT4(op, b1, b2) \
154 _EMIT4((op) | reg(b1, b2)); \
159 #define EMIT4_RRF(op, b1, b2, b3) \
161 _EMIT4((op) | reg_high(b3) << 8 | reg(b1, b2)); \
167 #define _EMIT4_DISP(op, disp) \
169 unsigned int __disp = (disp) & 0xfff; \
170 _EMIT4((op) | __disp); \
173 #define EMIT4_DISP(op, b1, b2, disp) \
175 _EMIT4_DISP((op) | reg_high(b1) << 16 | \
176 reg_high(b2) << 8, (disp)); \
181 #define EMIT4_IMM(op, b1, imm) \
183 unsigned int __imm = (imm) & 0xffff; \
184 _EMIT4((op) | reg_high(b1) << 16 | __imm); \
188 #define EMIT4_PCREL(op, pcrel) \
190 long __pcrel = ((pcrel) >> 1) & 0xffff; \
191 _EMIT4((op) | __pcrel); \
194 #define EMIT4_PCREL_RIC(op, mask, target) \
196 int __rel = ((target) - jit->prg) / 2; \
197 _EMIT4((op) | (mask) << 20 | (__rel & 0xffff)); \
200 #define _EMIT6(op1, op2) \
202 if (jit->prg_buf) { \
203 *(u32 *) (jit->prg_buf + jit->prg) = (op1); \
204 *(u16 *) (jit->prg_buf + jit->prg + 4) = (op2); \
209 #define _EMIT6_DISP(op1, op2, disp) \
211 unsigned int __disp = (disp) & 0xfff; \
212 _EMIT6((op1) | __disp, op2); \
215 #define _EMIT6_DISP_LH(op1, op2, disp) \
217 u32 _disp = (u32) (disp); \
218 unsigned int __disp_h = _disp & 0xff000; \
219 unsigned int __disp_l = _disp & 0x00fff; \
220 _EMIT6((op1) | __disp_l, (op2) | __disp_h >> 4); \
223 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
225 _EMIT6_DISP_LH((op1) | reg(b1, b2) << 16 | \
226 reg_high(b3) << 8, op2, disp); \
232 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
234 int rel = (jit->labels[label] - jit->prg) >> 1; \
235 _EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), \
236 (op2) | (mask) << 12); \
241 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
243 int rel = (jit->labels[label] - jit->prg) >> 1; \
244 _EMIT6((op1) | (reg_high(b1) | (mask)) << 16 | \
245 (rel & 0xffff), (op2) | ((imm) & 0xff) << 8); \
247 BUILD_BUG_ON(((unsigned long) (imm)) > 0xff); \
250 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
252 /* Branch instruction needs 6 bytes */ \
253 int rel = (addrs[(i) + (off) + 1] - (addrs[(i) + 1] - 6)) / 2;\
254 _EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), (op2) | (mask));\
259 #define EMIT6_PCREL_RILB(op, b, target) \
261 unsigned int rel = (int)((target) - jit->prg) / 2; \
262 _EMIT6((op) | reg_high(b) << 16 | rel >> 16, rel & 0xffff);\
266 #define EMIT6_PCREL_RIL(op, target) \
268 unsigned int rel = (int)((target) - jit->prg) / 2; \
269 _EMIT6((op) | rel >> 16, rel & 0xffff); \
272 #define EMIT6_PCREL_RILC(op, mask, target) \
274 EMIT6_PCREL_RIL((op) | (mask) << 20, (target)); \
277 #define _EMIT6_IMM(op, imm) \
279 unsigned int __imm = (imm); \
280 _EMIT6((op) | (__imm >> 16), __imm & 0xffff); \
283 #define EMIT6_IMM(op, b1, imm) \
285 _EMIT6_IMM((op) | reg_high(b1) << 16, imm); \
289 #define _EMIT_CONST_U32(val) \
294 *(u32 *)(jit->prg_buf + jit->lit32) = (u32)(val);\
299 #define EMIT_CONST_U32(val) \
301 jit->seen |= SEEN_LITERAL; \
302 _EMIT_CONST_U32(val) - jit->base_ip; \
305 #define _EMIT_CONST_U64(val) \
310 *(u64 *)(jit->prg_buf + jit->lit64) = (u64)(val);\
315 #define EMIT_CONST_U64(val) \
317 jit->seen |= SEEN_LITERAL; \
318 _EMIT_CONST_U64(val) - jit->base_ip; \
321 #define EMIT_ZERO(b1) \
323 if (!fp->aux->verifier_zext) { \
324 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
325 EMIT4(0xb9160000, b1, b1); \
331 * Return whether this is the first pass. The first pass is special, since we
332 * don't know any sizes yet, and thus must be conservative.
334 static bool is_first_pass(struct bpf_jit *jit)
336 return jit->size == 0;
340 * Return whether this is the code generation pass. The code generation pass is
341 * special, since we should change as little as possible.
343 static bool is_codegen_pass(struct bpf_jit *jit)
349 * Return whether "rel" can be encoded as a short PC-relative offset
351 static bool is_valid_rel(int rel)
353 return rel >= -65536 && rel <= 65534;
357 * Return whether "off" can be reached using a short PC-relative offset
359 static bool can_use_rel(struct bpf_jit *jit, int off)
361 return is_valid_rel(off - jit->prg);
365 * Return whether given displacement can be encoded using
366 * Long-Displacement Facility
368 static bool is_valid_ldisp(int disp)
370 return disp >= -524288 && disp <= 524287;
374 * Return whether the next 32-bit literal pool entry can be referenced using
375 * Long-Displacement Facility
377 static bool can_use_ldisp_for_lit32(struct bpf_jit *jit)
379 return is_valid_ldisp(jit->lit32 - jit->base_ip);
383 * Return whether the next 64-bit literal pool entry can be referenced using
384 * Long-Displacement Facility
386 static bool can_use_ldisp_for_lit64(struct bpf_jit *jit)
388 return is_valid_ldisp(jit->lit64 - jit->base_ip);
392 * Fill whole space with illegal instructions
394 static void jit_fill_hole(void *area, unsigned int size)
396 memset(area, 0, size);
400 * Save registers from "rs" (register start) to "re" (register end) on stack
402 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
404 u32 off = STK_OFF_R6 + (rs - 6) * 8;
407 /* stg %rs,off(%r15) */
408 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
410 /* stmg %rs,%re,off(%r15) */
411 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
415 * Restore registers from "rs" (register start) to "re" (register end) on stack
417 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re, u32 stack_depth)
419 u32 off = STK_OFF_R6 + (rs - 6) * 8;
421 if (jit->seen & SEEN_STACK)
422 off += STK_OFF + stack_depth;
425 /* lg %rs,off(%r15) */
426 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
428 /* lmg %rs,%re,off(%r15) */
429 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
433 * Return first seen register (from start)
435 static int get_start(struct bpf_jit *jit, int start)
439 for (i = start; i <= 15; i++) {
440 if (jit->seen_reg[i])
447 * Return last seen register (from start) (gap >= 2)
449 static int get_end(struct bpf_jit *jit, int start)
453 for (i = start; i < 15; i++) {
454 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
457 return jit->seen_reg[15] ? 15 : 14;
461 #define REGS_RESTORE 0
463 * Save and restore clobbered registers (6-15) on stack.
464 * We save/restore registers in chunks with gap >= 2 registers.
466 static void save_restore_regs(struct bpf_jit *jit, int op, u32 stack_depth)
468 const int last = 15, save_restore_size = 6;
471 if (is_first_pass(jit)) {
473 * We don't know yet which registers are used. Reserve space
476 jit->prg += (last - re + 1) * save_restore_size;
481 rs = get_start(jit, re);
484 re = get_end(jit, rs + 1);
486 save_regs(jit, rs, re);
488 restore_regs(jit, rs, re, stack_depth);
490 } while (re <= last);
493 static void bpf_skip(struct bpf_jit *jit, int size)
495 if (size >= 6 && !is_valid_rel(size)) {
497 EMIT6_PCREL_RIL(0xc0f4000000, size);
499 } else if (size >= 4 && is_valid_rel(size)) {
501 EMIT4_PCREL(0xa7f40000, size);
512 * Emit function prologue
514 * Save registers and create stack frame if necessary.
515 * See stack frame layout desription in "bpf_jit.h"!
517 static void bpf_jit_prologue(struct bpf_jit *jit, u32 stack_depth)
519 if (jit->seen & SEEN_TAIL_CALL) {
520 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
521 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
524 * There are no tail calls. Insert nops in order to have
525 * tail_call_start at a predictable offset.
529 /* Tail calls have to skip above initialization */
530 jit->tail_call_start = jit->prg;
532 save_restore_regs(jit, REGS_SAVE, stack_depth);
533 /* Setup literal pool */
534 if (is_first_pass(jit) || (jit->seen & SEEN_LITERAL)) {
535 if (!is_first_pass(jit) &&
536 is_valid_ldisp(jit->size - (jit->prg + 2))) {
538 EMIT2(0x0d00, REG_L, REG_0);
539 jit->base_ip = jit->prg;
541 /* larl %l,lit32_start */
542 EMIT6_PCREL_RILB(0xc0000000, REG_L, jit->lit32_start);
543 jit->base_ip = jit->lit32_start;
546 /* Setup stack and backchain */
547 if (is_first_pass(jit) || (jit->seen & SEEN_STACK)) {
548 if (is_first_pass(jit) || (jit->seen & SEEN_FUNC))
549 /* lgr %w1,%r15 (backchain) */
550 EMIT4(0xb9040000, REG_W1, REG_15);
551 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
552 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
553 /* aghi %r15,-STK_OFF */
554 EMIT4_IMM(0xa70b0000, REG_15, -(STK_OFF + stack_depth));
555 if (is_first_pass(jit) || (jit->seen & SEEN_FUNC))
556 /* stg %w1,152(%r15) (backchain) */
557 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
565 static void bpf_jit_epilogue(struct bpf_jit *jit, u32 stack_depth)
567 jit->exit_ip = jit->prg;
568 /* Load exit code: lgr %r2,%b0 */
569 EMIT4(0xb9040000, REG_2, BPF_REG_0);
570 /* Restore registers */
571 save_restore_regs(jit, REGS_RESTORE, stack_depth);
572 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) {
573 jit->r14_thunk_ip = jit->prg;
574 /* Generate __s390_indirect_jump_r14 thunk */
575 if (test_facility(35)) {
577 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
580 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14);
582 EMIT4_DISP(0x44000000, REG_0, REG_1, 0);
585 EMIT4_PCREL(0xa7f40000, 0);
590 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable &&
591 (is_first_pass(jit) || (jit->seen & SEEN_FUNC))) {
592 jit->r1_thunk_ip = jit->prg;
593 /* Generate __s390_indirect_jump_r1 thunk */
594 if (test_facility(35)) {
596 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
598 EMIT4_PCREL(0xa7f40000, 0);
602 /* ex 0,S390_lowcore.br_r1_tampoline */
603 EMIT4_DISP(0x44000000, REG_0, REG_0,
604 offsetof(struct lowcore, br_r1_trampoline));
606 EMIT4_PCREL(0xa7f40000, 0);
611 static int get_probe_mem_regno(const u8 *insn)
614 * insn must point to llgc, llgh, llgf or lg, which have destination
615 * register at the same position.
617 if (insn[0] != 0xe3) /* common llgc, llgh, llgf and lg prefix */
619 if (insn[5] != 0x90 && /* llgc */
620 insn[5] != 0x91 && /* llgh */
621 insn[5] != 0x16 && /* llgf */
622 insn[5] != 0x04) /* lg */
627 static bool ex_handler_bpf(const struct exception_table_entry *x,
628 struct pt_regs *regs)
633 regs->psw.addr = extable_fixup(x);
634 insn = (u8 *)__rewind_psw(regs->psw, regs->int_code >> 16);
635 regno = get_probe_mem_regno(insn);
636 if (WARN_ON_ONCE(regno < 0))
637 /* JIT bug - unexpected instruction. */
639 regs->gprs[regno] = 0;
643 static int bpf_jit_probe_mem(struct bpf_jit *jit, struct bpf_prog *fp,
644 int probe_prg, int nop_prg)
646 struct exception_table_entry *ex;
652 if (!fp->aux->extable)
653 /* Do nothing during early JIT passes. */
655 insn = jit->prg_buf + probe_prg;
656 if (WARN_ON_ONCE(get_probe_mem_regno(insn) < 0))
657 /* JIT bug - unexpected probe instruction. */
659 if (WARN_ON_ONCE(probe_prg + insn_length(*insn) != nop_prg))
660 /* JIT bug - gap between probe and nop instructions. */
662 for (i = 0; i < 2; i++) {
663 if (WARN_ON_ONCE(jit->excnt >= fp->aux->num_exentries))
664 /* Verifier bug - not enough entries. */
666 ex = &fp->aux->extable[jit->excnt];
667 /* Add extable entries for probe and nop instructions. */
668 prg = i == 0 ? probe_prg : nop_prg;
669 delta = jit->prg_buf + prg - (u8 *)&ex->insn;
670 if (WARN_ON_ONCE(delta < INT_MIN || delta > INT_MAX))
671 /* JIT bug - code and extable must be close. */
675 * Always land on the nop. Note that extable infrastructure
676 * ignores fixup field, it is handled by ex_handler_bpf().
678 delta = jit->prg_buf + nop_prg - (u8 *)&ex->fixup;
679 if (WARN_ON_ONCE(delta < INT_MIN || delta > INT_MAX))
680 /* JIT bug - landing pad and extable must be close. */
683 ex->handler = (u8 *)ex_handler_bpf - (u8 *)&ex->handler;
690 * Compile one eBPF instruction into s390x code
692 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
693 * stack space for the large switch statement.
695 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp,
696 int i, bool extra_pass, u32 stack_depth)
698 struct bpf_insn *insn = &fp->insnsi[i];
699 u32 dst_reg = insn->dst_reg;
700 u32 src_reg = insn->src_reg;
701 int last, insn_count = 1;
702 u32 *addrs = jit->addrs;
710 if (BPF_CLASS(insn->code) == BPF_LDX &&
711 BPF_MODE(insn->code) == BPF_PROBE_MEM)
712 probe_prg = jit->prg;
714 switch (insn->code) {
718 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
719 /* llgfr %dst,%src */
720 EMIT4(0xb9160000, dst_reg, src_reg);
721 if (insn_is_zext(&insn[1]))
724 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
726 EMIT4(0xb9040000, dst_reg, src_reg);
728 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
730 EMIT6_IMM(0xc00f0000, dst_reg, imm);
731 if (insn_is_zext(&insn[1]))
734 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
736 EMIT6_IMM(0xc0010000, dst_reg, imm);
741 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
743 /* 16 byte instruction that uses two 'struct bpf_insn' */
746 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
748 EMIT6_PCREL_RILB(0xc4080000, dst_reg, _EMIT_CONST_U64(imm64));
755 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
757 EMIT2(0x1a00, dst_reg, src_reg);
760 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
762 EMIT4(0xb9080000, dst_reg, src_reg);
764 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
768 EMIT6_IMM(0xc20b0000, dst_reg, imm);
771 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
775 EMIT6_IMM(0xc2080000, dst_reg, imm);
780 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
782 EMIT2(0x1b00, dst_reg, src_reg);
785 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
787 EMIT4(0xb9090000, dst_reg, src_reg);
789 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
793 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
796 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
800 EMIT6_IMM(0xc2080000, dst_reg, -imm);
805 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
807 EMIT4(0xb2520000, dst_reg, src_reg);
810 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
812 EMIT4(0xb90c0000, dst_reg, src_reg);
814 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
818 EMIT6_IMM(0xc2010000, dst_reg, imm);
821 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
825 EMIT6_IMM(0xc2000000, dst_reg, imm);
830 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
831 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
833 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
836 EMIT4_IMM(0xa7080000, REG_W0, 0);
838 EMIT2(0x1800, REG_W1, dst_reg);
840 EMIT4(0xb9970000, REG_W0, src_reg);
842 EMIT4(0xb9160000, dst_reg, rc_reg);
843 if (insn_is_zext(&insn[1]))
847 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
848 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
850 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
853 EMIT4_IMM(0xa7090000, REG_W0, 0);
855 EMIT4(0xb9040000, REG_W1, dst_reg);
857 EMIT4(0xb9870000, REG_W0, src_reg);
859 EMIT4(0xb9040000, dst_reg, rc_reg);
862 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
863 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
865 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
868 if (BPF_OP(insn->code) == BPF_MOD)
870 EMIT4_IMM(0xa7090000, dst_reg, 0);
874 EMIT4_IMM(0xa7080000, REG_W0, 0);
876 EMIT2(0x1800, REG_W1, dst_reg);
877 if (!is_first_pass(jit) && can_use_ldisp_for_lit32(jit)) {
878 /* dl %w0,<d(imm)>(%l) */
879 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
880 EMIT_CONST_U32(imm));
883 EMIT6_PCREL_RILB(0xc40c0000, dst_reg,
884 _EMIT_CONST_U32(imm));
885 jit->seen |= SEEN_LITERAL;
887 EMIT4(0xb9970000, REG_W0, dst_reg);
890 EMIT4(0xb9160000, dst_reg, rc_reg);
891 if (insn_is_zext(&insn[1]))
895 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
896 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
898 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
901 if (BPF_OP(insn->code) == BPF_MOD)
903 EMIT4_IMM(0xa7090000, dst_reg, 0);
907 EMIT4_IMM(0xa7090000, REG_W0, 0);
909 EMIT4(0xb9040000, REG_W1, dst_reg);
910 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
911 /* dlg %w0,<d(imm)>(%l) */
912 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
913 EMIT_CONST_U64(imm));
916 EMIT6_PCREL_RILB(0xc4080000, dst_reg,
917 _EMIT_CONST_U64(imm));
918 jit->seen |= SEEN_LITERAL;
920 EMIT4(0xb9870000, REG_W0, dst_reg);
923 EMIT4(0xb9040000, dst_reg, rc_reg);
929 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
931 EMIT2(0x1400, dst_reg, src_reg);
934 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
936 EMIT4(0xb9800000, dst_reg, src_reg);
938 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
940 EMIT6_IMM(0xc00b0000, dst_reg, imm);
943 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
944 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
945 /* ng %dst,<d(imm)>(%l) */
946 EMIT6_DISP_LH(0xe3000000, 0x0080,
947 dst_reg, REG_0, REG_L,
948 EMIT_CONST_U64(imm));
951 EMIT6_PCREL_RILB(0xc4080000, REG_W0,
952 _EMIT_CONST_U64(imm));
953 jit->seen |= SEEN_LITERAL;
955 EMIT4(0xb9800000, dst_reg, REG_W0);
961 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
963 EMIT2(0x1600, dst_reg, src_reg);
966 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
968 EMIT4(0xb9810000, dst_reg, src_reg);
970 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
972 EMIT6_IMM(0xc00d0000, dst_reg, imm);
975 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
976 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
977 /* og %dst,<d(imm)>(%l) */
978 EMIT6_DISP_LH(0xe3000000, 0x0081,
979 dst_reg, REG_0, REG_L,
980 EMIT_CONST_U64(imm));
983 EMIT6_PCREL_RILB(0xc4080000, REG_W0,
984 _EMIT_CONST_U64(imm));
985 jit->seen |= SEEN_LITERAL;
987 EMIT4(0xb9810000, dst_reg, REG_W0);
993 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
995 EMIT2(0x1700, dst_reg, src_reg);
998 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
1000 EMIT4(0xb9820000, dst_reg, src_reg);
1002 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
1006 EMIT6_IMM(0xc0070000, dst_reg, imm);
1009 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
1010 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
1011 /* xg %dst,<d(imm)>(%l) */
1012 EMIT6_DISP_LH(0xe3000000, 0x0082,
1013 dst_reg, REG_0, REG_L,
1014 EMIT_CONST_U64(imm));
1017 EMIT6_PCREL_RILB(0xc4080000, REG_W0,
1018 _EMIT_CONST_U64(imm));
1019 jit->seen |= SEEN_LITERAL;
1021 EMIT4(0xb9820000, dst_reg, REG_W0);
1027 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
1028 /* sll %dst,0(%src) */
1029 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
1032 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
1033 /* sllg %dst,%dst,0(%src) */
1034 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
1036 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
1039 /* sll %dst,imm(%r0) */
1040 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
1043 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
1046 /* sllg %dst,%dst,imm(%r0) */
1047 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
1052 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
1053 /* srl %dst,0(%src) */
1054 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
1057 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
1058 /* srlg %dst,%dst,0(%src) */
1059 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
1061 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
1064 /* srl %dst,imm(%r0) */
1065 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
1068 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
1071 /* srlg %dst,%dst,imm(%r0) */
1072 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
1077 case BPF_ALU | BPF_ARSH | BPF_X: /* ((s32) dst) >>= src */
1078 /* sra %dst,%dst,0(%src) */
1079 EMIT4_DISP(0x8a000000, dst_reg, src_reg, 0);
1082 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
1083 /* srag %dst,%dst,0(%src) */
1084 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
1086 case BPF_ALU | BPF_ARSH | BPF_K: /* ((s32) dst >> imm */
1089 /* sra %dst,imm(%r0) */
1090 EMIT4_DISP(0x8a000000, dst_reg, REG_0, imm);
1093 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
1096 /* srag %dst,%dst,imm(%r0) */
1097 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
1102 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
1104 EMIT2(0x1300, dst_reg, dst_reg);
1107 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
1108 /* lcgr %dst,%dst */
1109 EMIT4(0xb9030000, dst_reg, dst_reg);
1114 case BPF_ALU | BPF_END | BPF_FROM_BE:
1115 /* s390 is big endian, therefore only clear high order bytes */
1117 case 16: /* dst = (u16) cpu_to_be16(dst) */
1118 /* llghr %dst,%dst */
1119 EMIT4(0xb9850000, dst_reg, dst_reg);
1120 if (insn_is_zext(&insn[1]))
1123 case 32: /* dst = (u32) cpu_to_be32(dst) */
1124 if (!fp->aux->verifier_zext)
1125 /* llgfr %dst,%dst */
1126 EMIT4(0xb9160000, dst_reg, dst_reg);
1128 case 64: /* dst = (u64) cpu_to_be64(dst) */
1132 case BPF_ALU | BPF_END | BPF_FROM_LE:
1134 case 16: /* dst = (u16) cpu_to_le16(dst) */
1135 /* lrvr %dst,%dst */
1136 EMIT4(0xb91f0000, dst_reg, dst_reg);
1137 /* srl %dst,16(%r0) */
1138 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
1139 /* llghr %dst,%dst */
1140 EMIT4(0xb9850000, dst_reg, dst_reg);
1141 if (insn_is_zext(&insn[1]))
1144 case 32: /* dst = (u32) cpu_to_le32(dst) */
1145 /* lrvr %dst,%dst */
1146 EMIT4(0xb91f0000, dst_reg, dst_reg);
1147 if (!fp->aux->verifier_zext)
1148 /* llgfr %dst,%dst */
1149 EMIT4(0xb9160000, dst_reg, dst_reg);
1151 case 64: /* dst = (u64) cpu_to_le64(dst) */
1152 /* lrvgr %dst,%dst */
1153 EMIT4(0xb90f0000, dst_reg, dst_reg);
1160 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
1161 /* stcy %src,off(%dst) */
1162 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
1163 jit->seen |= SEEN_MEM;
1165 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
1166 /* sthy %src,off(%dst) */
1167 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
1168 jit->seen |= SEEN_MEM;
1170 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
1171 /* sty %src,off(%dst) */
1172 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
1173 jit->seen |= SEEN_MEM;
1175 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
1176 /* stg %src,off(%dst) */
1177 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
1178 jit->seen |= SEEN_MEM;
1180 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
1182 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
1183 /* stcy %w0,off(dst) */
1184 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
1185 jit->seen |= SEEN_MEM;
1187 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
1189 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
1190 /* sthy %w0,off(dst) */
1191 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
1192 jit->seen |= SEEN_MEM;
1194 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
1196 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
1197 /* sty %w0,off(%dst) */
1198 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
1199 jit->seen |= SEEN_MEM;
1201 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
1203 EMIT6_IMM(0xc0010000, REG_W0, imm);
1204 /* stg %w0,off(%dst) */
1205 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
1206 jit->seen |= SEEN_MEM;
1209 * BPF_STX XADD (atomic_add)
1211 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
1212 /* laal %w0,%src,off(%dst) */
1213 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
1215 jit->seen |= SEEN_MEM;
1217 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
1218 /* laalg %w0,%src,off(%dst) */
1219 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
1221 jit->seen |= SEEN_MEM;
1226 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
1227 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
1228 /* llgc %dst,0(off,%src) */
1229 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
1230 jit->seen |= SEEN_MEM;
1231 if (insn_is_zext(&insn[1]))
1234 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
1235 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
1236 /* llgh %dst,0(off,%src) */
1237 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
1238 jit->seen |= SEEN_MEM;
1239 if (insn_is_zext(&insn[1]))
1242 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
1243 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
1244 /* llgf %dst,off(%src) */
1245 jit->seen |= SEEN_MEM;
1246 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
1247 if (insn_is_zext(&insn[1]))
1250 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
1251 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
1252 /* lg %dst,0(off,%src) */
1253 jit->seen |= SEEN_MEM;
1254 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
1259 case BPF_JMP | BPF_CALL:
1262 bool func_addr_fixed;
1265 ret = bpf_jit_get_func_addr(fp, insn, extra_pass,
1266 &func, &func_addr_fixed);
1270 REG_SET_SEEN(BPF_REG_5);
1271 jit->seen |= SEEN_FUNC;
1273 EMIT6_PCREL_RILB(0xc4080000, REG_W1, _EMIT_CONST_U64(func));
1274 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) {
1275 /* brasl %r14,__s390_indirect_jump_r1 */
1276 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip);
1279 EMIT2(0x0d00, REG_14, REG_W1);
1281 /* lgr %b0,%r2: load return value into %b0 */
1282 EMIT4(0xb9040000, BPF_REG_0, REG_2);
1285 case BPF_JMP | BPF_TAIL_CALL:
1288 * B1: pointer to ctx
1289 * B2: pointer to bpf_array
1290 * B3: index in bpf_array
1292 jit->seen |= SEEN_TAIL_CALL;
1295 * if (index >= array->map.max_entries)
1299 /* llgf %w1,map.max_entries(%b2) */
1300 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
1301 offsetof(struct bpf_array, map.max_entries));
1302 /* if ((u32)%b3 >= (u32)%w1) goto out; */
1303 if (!is_first_pass(jit) && can_use_rel(jit, jit->labels[0])) {
1304 /* clrj %b3,%w1,0xa,label0 */
1305 EMIT6_PCREL_LABEL(0xec000000, 0x0077, BPF_REG_3,
1309 EMIT2(0x1500, BPF_REG_3, REG_W1);
1310 /* brcl 0xa,label0 */
1311 EMIT6_PCREL_RILC(0xc0040000, 0xa, jit->labels[0]);
1315 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1319 if (jit->seen & SEEN_STACK)
1320 off = STK_OFF_TCCNT + STK_OFF + stack_depth;
1322 off = STK_OFF_TCCNT;
1324 EMIT4_IMM(0xa7080000, REG_W0, 1);
1325 /* laal %w1,%w0,off(%r15) */
1326 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1327 if (!is_first_pass(jit) && can_use_rel(jit, jit->labels[0])) {
1328 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1329 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1,
1330 MAX_TAIL_CALL_CNT, 0, 0x2);
1332 /* clfi %w1,MAX_TAIL_CALL_CNT */
1333 EMIT6_IMM(0xc20f0000, REG_W1, MAX_TAIL_CALL_CNT);
1334 /* brcl 0x2,label0 */
1335 EMIT6_PCREL_RILC(0xc0040000, 0x2, jit->labels[0]);
1339 * prog = array->ptrs[index];
1344 /* llgfr %r1,%b3: %r1 = (u32) index */
1345 EMIT4(0xb9160000, REG_1, BPF_REG_3);
1346 /* sllg %r1,%r1,3: %r1 *= 8 */
1347 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, REG_1, REG_0, 3);
1348 /* ltg %r1,prog(%b2,%r1) */
1349 EMIT6_DISP_LH(0xe3000000, 0x0002, REG_1, BPF_REG_2,
1350 REG_1, offsetof(struct bpf_array, ptrs));
1351 if (!is_first_pass(jit) && can_use_rel(jit, jit->labels[0])) {
1352 /* brc 0x8,label0 */
1353 EMIT4_PCREL_RIC(0xa7040000, 0x8, jit->labels[0]);
1355 /* brcl 0x8,label0 */
1356 EMIT6_PCREL_RILC(0xc0040000, 0x8, jit->labels[0]);
1360 * Restore registers before calling function
1362 save_restore_regs(jit, REGS_RESTORE, stack_depth);
1365 * goto *(prog->bpf_func + tail_call_start);
1368 /* lg %r1,bpf_func(%r1) */
1369 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1370 offsetof(struct bpf_prog, bpf_func));
1371 /* bc 0xf,tail_call_start(%r1) */
1372 _EMIT4(0x47f01000 + jit->tail_call_start);
1374 jit->labels[0] = jit->prg;
1376 case BPF_JMP | BPF_EXIT: /* return b0 */
1377 last = (i == fp->len - 1) ? 1 : 0;
1380 if (!is_first_pass(jit) && can_use_rel(jit, jit->exit_ip))
1381 /* brc 0xf, <exit> */
1382 EMIT4_PCREL_RIC(0xa7040000, 0xf, jit->exit_ip);
1384 /* brcl 0xf, <exit> */
1385 EMIT6_PCREL_RILC(0xc0040000, 0xf, jit->exit_ip);
1388 * Branch relative (number of skipped instructions) to offset on
1391 * Condition code to mask mapping:
1393 * CC | Description | Mask
1394 * ------------------------------
1395 * 0 | Operands equal | 8
1396 * 1 | First operand low | 4
1397 * 2 | First operand high | 2
1400 * For s390x relative branches: ip = ip + off_bytes
1401 * For BPF relative branches: insn = insn + off_insns + 1
1403 * For example for s390x with offset 0 we jump to the branch
1404 * instruction itself (loop) and for BPF with offset 0 we
1405 * branch to the instruction behind the branch.
1407 case BPF_JMP | BPF_JA: /* if (true) */
1408 mask = 0xf000; /* j */
1410 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1411 case BPF_JMP32 | BPF_JSGT | BPF_K: /* ((s32) dst > (s32) imm) */
1412 mask = 0x2000; /* jh */
1414 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */
1415 case BPF_JMP32 | BPF_JSLT | BPF_K: /* ((s32) dst < (s32) imm) */
1416 mask = 0x4000; /* jl */
1418 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1419 case BPF_JMP32 | BPF_JSGE | BPF_K: /* ((s32) dst >= (s32) imm) */
1420 mask = 0xa000; /* jhe */
1422 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */
1423 case BPF_JMP32 | BPF_JSLE | BPF_K: /* ((s32) dst <= (s32) imm) */
1424 mask = 0xc000; /* jle */
1426 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1427 case BPF_JMP32 | BPF_JGT | BPF_K: /* ((u32) dst_reg > (u32) imm) */
1428 mask = 0x2000; /* jh */
1430 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */
1431 case BPF_JMP32 | BPF_JLT | BPF_K: /* ((u32) dst_reg < (u32) imm) */
1432 mask = 0x4000; /* jl */
1434 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1435 case BPF_JMP32 | BPF_JGE | BPF_K: /* ((u32) dst_reg >= (u32) imm) */
1436 mask = 0xa000; /* jhe */
1438 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */
1439 case BPF_JMP32 | BPF_JLE | BPF_K: /* ((u32) dst_reg <= (u32) imm) */
1440 mask = 0xc000; /* jle */
1442 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1443 case BPF_JMP32 | BPF_JNE | BPF_K: /* ((u32) dst_reg != (u32) imm) */
1444 mask = 0x7000; /* jne */
1446 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1447 case BPF_JMP32 | BPF_JEQ | BPF_K: /* ((u32) dst_reg == (u32) imm) */
1448 mask = 0x8000; /* je */
1450 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1451 case BPF_JMP32 | BPF_JSET | BPF_K: /* ((u32) dst_reg & (u32) imm) */
1452 mask = 0x7000; /* jnz */
1453 if (BPF_CLASS(insn->code) == BPF_JMP32) {
1454 /* llilf %w1,imm (load zero extend imm) */
1455 EMIT6_IMM(0xc00f0000, REG_W1, imm);
1457 EMIT2(0x1400, REG_W1, dst_reg);
1459 /* lgfi %w1,imm (load sign extend imm) */
1460 EMIT6_IMM(0xc0010000, REG_W1, imm);
1462 EMIT4(0xb9800000, REG_W1, dst_reg);
1466 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1467 case BPF_JMP32 | BPF_JSGT | BPF_X: /* ((s32) dst > (s32) src) */
1468 mask = 0x2000; /* jh */
1470 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */
1471 case BPF_JMP32 | BPF_JSLT | BPF_X: /* ((s32) dst < (s32) src) */
1472 mask = 0x4000; /* jl */
1474 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1475 case BPF_JMP32 | BPF_JSGE | BPF_X: /* ((s32) dst >= (s32) src) */
1476 mask = 0xa000; /* jhe */
1478 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */
1479 case BPF_JMP32 | BPF_JSLE | BPF_X: /* ((s32) dst <= (s32) src) */
1480 mask = 0xc000; /* jle */
1482 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1483 case BPF_JMP32 | BPF_JGT | BPF_X: /* ((u32) dst > (u32) src) */
1484 mask = 0x2000; /* jh */
1486 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */
1487 case BPF_JMP32 | BPF_JLT | BPF_X: /* ((u32) dst < (u32) src) */
1488 mask = 0x4000; /* jl */
1490 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1491 case BPF_JMP32 | BPF_JGE | BPF_X: /* ((u32) dst >= (u32) src) */
1492 mask = 0xa000; /* jhe */
1494 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */
1495 case BPF_JMP32 | BPF_JLE | BPF_X: /* ((u32) dst <= (u32) src) */
1496 mask = 0xc000; /* jle */
1498 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1499 case BPF_JMP32 | BPF_JNE | BPF_X: /* ((u32) dst != (u32) src) */
1500 mask = 0x7000; /* jne */
1502 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1503 case BPF_JMP32 | BPF_JEQ | BPF_X: /* ((u32) dst == (u32) src) */
1504 mask = 0x8000; /* je */
1506 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1507 case BPF_JMP32 | BPF_JSET | BPF_X: /* ((u32) dst & (u32) src) */
1509 bool is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1511 mask = 0x7000; /* jnz */
1512 /* nrk or ngrk %w1,%dst,%src */
1513 EMIT4_RRF((is_jmp32 ? 0xb9f40000 : 0xb9e40000),
1514 REG_W1, dst_reg, src_reg);
1517 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1518 /* cfi or cgfi %dst,imm */
1519 EMIT6_IMM(is_jmp32 ? 0xc20d0000 : 0xc20c0000,
1521 if (!is_first_pass(jit) &&
1522 can_use_rel(jit, addrs[i + off + 1])) {
1524 EMIT4_PCREL_RIC(0xa7040000,
1525 mask >> 12, addrs[i + off + 1]);
1528 EMIT6_PCREL_RILC(0xc0040000,
1529 mask >> 12, addrs[i + off + 1]);
1533 /* lgfi %w1,imm (load sign extend imm) */
1535 EMIT6_IMM(0xc0010000, src_reg, imm);
1538 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1539 if (!is_first_pass(jit) &&
1540 can_use_rel(jit, addrs[i + off + 1])) {
1541 /* crj or cgrj %dst,%src,mask,off */
1542 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0076 : 0x0064),
1543 dst_reg, src_reg, i, off, mask);
1545 /* cr or cgr %dst,%src */
1547 EMIT2(0x1900, dst_reg, src_reg);
1549 EMIT4(0xb9200000, dst_reg, src_reg);
1551 EMIT6_PCREL_RILC(0xc0040000,
1552 mask >> 12, addrs[i + off + 1]);
1556 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1557 if (!is_first_pass(jit) &&
1558 can_use_rel(jit, addrs[i + off + 1])) {
1559 /* clrj or clgrj %dst,%src,mask,off */
1560 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0077 : 0x0065),
1561 dst_reg, src_reg, i, off, mask);
1563 /* clr or clgr %dst,%src */
1565 EMIT2(0x1500, dst_reg, src_reg);
1567 EMIT4(0xb9210000, dst_reg, src_reg);
1569 EMIT6_PCREL_RILC(0xc0040000,
1570 mask >> 12, addrs[i + off + 1]);
1574 if (!is_first_pass(jit) &&
1575 can_use_rel(jit, addrs[i + off + 1])) {
1577 EMIT4_PCREL_RIC(0xa7040000,
1578 mask >> 12, addrs[i + off + 1]);
1581 EMIT6_PCREL_RILC(0xc0040000,
1582 mask >> 12, addrs[i + off + 1]);
1586 default: /* too complex, give up */
1587 pr_err("Unknown opcode %02x\n", insn->code);
1591 if (probe_prg != -1) {
1593 * Handlers of certain exceptions leave psw.addr pointing to
1594 * the instruction directly after the failing one. Therefore,
1595 * create two exception table entries and also add a nop in
1596 * case two probing instructions come directly after each
1602 err = bpf_jit_probe_mem(jit, fp, probe_prg, nop_prg);
1611 * Return whether new i-th instruction address does not violate any invariant
1613 static bool bpf_is_new_addr_sane(struct bpf_jit *jit, int i)
1615 /* On the first pass anything goes */
1616 if (is_first_pass(jit))
1619 /* The codegen pass must not change anything */
1620 if (is_codegen_pass(jit))
1621 return jit->addrs[i] == jit->prg;
1623 /* Passes in between must not increase code size */
1624 return jit->addrs[i] >= jit->prg;
1628 * Update the address of i-th instruction
1630 static int bpf_set_addr(struct bpf_jit *jit, int i)
1634 if (is_codegen_pass(jit)) {
1635 delta = jit->prg - jit->addrs[i];
1637 bpf_skip(jit, -delta);
1639 if (WARN_ON_ONCE(!bpf_is_new_addr_sane(jit, i)))
1641 jit->addrs[i] = jit->prg;
1646 * Compile eBPF program into s390x code
1648 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp,
1649 bool extra_pass, u32 stack_depth)
1651 int i, insn_count, lit32_size, lit64_size;
1653 jit->lit32 = jit->lit32_start;
1654 jit->lit64 = jit->lit64_start;
1658 bpf_jit_prologue(jit, stack_depth);
1659 if (bpf_set_addr(jit, 0) < 0)
1661 for (i = 0; i < fp->len; i += insn_count) {
1662 insn_count = bpf_jit_insn(jit, fp, i, extra_pass, stack_depth);
1665 /* Next instruction address */
1666 if (bpf_set_addr(jit, i + insn_count) < 0)
1669 bpf_jit_epilogue(jit, stack_depth);
1671 lit32_size = jit->lit32 - jit->lit32_start;
1672 lit64_size = jit->lit64 - jit->lit64_start;
1673 jit->lit32_start = jit->prg;
1675 jit->lit32_start = ALIGN(jit->lit32_start, 4);
1676 jit->lit64_start = jit->lit32_start + lit32_size;
1678 jit->lit64_start = ALIGN(jit->lit64_start, 8);
1679 jit->size = jit->lit64_start + lit64_size;
1680 jit->size_prg = jit->prg;
1682 if (WARN_ON_ONCE(fp->aux->extable &&
1683 jit->excnt != fp->aux->num_exentries))
1684 /* Verifier bug - too many entries. */
1690 bool bpf_jit_needs_zext(void)
1695 struct s390_jit_data {
1696 struct bpf_binary_header *header;
1701 static struct bpf_binary_header *bpf_jit_alloc(struct bpf_jit *jit,
1702 struct bpf_prog *fp)
1704 struct bpf_binary_header *header;
1708 /* We need two entries per insn. */
1709 fp->aux->num_exentries *= 2;
1711 code_size = roundup(jit->size,
1712 __alignof__(struct exception_table_entry));
1713 extable_size = fp->aux->num_exentries *
1714 sizeof(struct exception_table_entry);
1715 header = bpf_jit_binary_alloc(code_size + extable_size, &jit->prg_buf,
1719 fp->aux->extable = (struct exception_table_entry *)
1720 (jit->prg_buf + code_size);
1725 * Compile eBPF program "fp"
1727 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
1729 u32 stack_depth = round_up(fp->aux->stack_depth, 8);
1730 struct bpf_prog *tmp, *orig_fp = fp;
1731 struct bpf_binary_header *header;
1732 struct s390_jit_data *jit_data;
1733 bool tmp_blinded = false;
1734 bool extra_pass = false;
1738 if (!fp->jit_requested)
1741 tmp = bpf_jit_blind_constants(fp);
1743 * If blinding was requested and we failed during blinding,
1744 * we must fall back to the interpreter.
1753 jit_data = fp->aux->jit_data;
1755 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
1760 fp->aux->jit_data = jit_data;
1762 if (jit_data->ctx.addrs) {
1763 jit = jit_data->ctx;
1764 header = jit_data->header;
1766 pass = jit_data->pass + 1;
1770 memset(&jit, 0, sizeof(jit));
1771 jit.addrs = kvcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1772 if (jit.addrs == NULL) {
1777 * Three initial passes:
1778 * - 1/2: Determine clobbered registers
1779 * - 3: Calculate program size and addrs arrray
1781 for (pass = 1; pass <= 3; pass++) {
1782 if (bpf_jit_prog(&jit, fp, extra_pass, stack_depth)) {
1788 * Final pass: Allocate and generate program
1790 header = bpf_jit_alloc(&jit, fp);
1796 if (bpf_jit_prog(&jit, fp, extra_pass, stack_depth)) {
1797 bpf_jit_binary_free(header);
1801 if (bpf_jit_enable > 1) {
1802 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1803 print_fn_code(jit.prg_buf, jit.size_prg);
1805 if (!fp->is_func || extra_pass) {
1806 bpf_jit_binary_lock_ro(header);
1808 jit_data->header = header;
1809 jit_data->ctx = jit;
1810 jit_data->pass = pass;
1812 fp->bpf_func = (void *) jit.prg_buf;
1814 fp->jited_len = jit.size;
1816 if (!fp->is_func || extra_pass) {
1817 bpf_prog_fill_jited_linfo(fp, jit.addrs + 1);
1821 fp->aux->jit_data = NULL;
1825 bpf_jit_prog_release_other(fp, fp == orig_fp ?