1 // SPDX-License-Identifier: GPL-2.0
3 * BPF Jit compiler for s390.
5 * Minimum build requirements:
7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
13 * Copyright IBM Corp. 2012,2015
15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
16 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
19 #define KMSG_COMPONENT "bpf_jit"
20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
22 #include <linux/netdevice.h>
23 #include <linux/filter.h>
24 #include <linux/init.h>
25 #include <linux/bpf.h>
27 #include <linux/kernel.h>
28 #include <asm/cacheflush.h>
30 #include <asm/facility.h>
31 #include <asm/nospec-branch.h>
32 #include <asm/set_memory.h>
36 u32 seen; /* Flags to remember seen eBPF instructions */
37 u32 seen_reg[16]; /* Array to remember which registers are used */
38 u32 *addrs; /* Array with relative instruction addresses */
39 u8 *prg_buf; /* Start of program */
40 int size; /* Size of program and literal pool */
41 int size_prg; /* Size of program */
42 int prg; /* Current position in program */
43 int lit32_start; /* Start of 32-bit literal pool */
44 int lit32; /* Current position in 32-bit literal pool */
45 int lit64_start; /* Start of 64-bit literal pool */
46 int lit64; /* Current position in 64-bit literal pool */
47 int base_ip; /* Base address for literal pool */
48 int exit_ip; /* Address of exit */
49 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */
50 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */
51 int tail_call_start; /* Tail call start offset */
52 int excnt; /* Number of exception table entries */
53 int labels[1]; /* Labels for local jumps */
56 #define SEEN_MEM BIT(0) /* use mem[] for temporary storage */
57 #define SEEN_LITERAL BIT(1) /* code uses literals */
58 #define SEEN_FUNC BIT(2) /* calls C functions */
59 #define SEEN_TAIL_CALL BIT(3) /* code uses tail calls */
60 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM)
65 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
66 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */
67 #define REG_L (MAX_BPF_JIT_REG + 2) /* Literal pool register */
68 #define REG_15 (MAX_BPF_JIT_REG + 3) /* Register 15 */
69 #define REG_0 REG_W0 /* Register 0 */
70 #define REG_1 REG_W1 /* Register 1 */
71 #define REG_2 BPF_REG_1 /* Register 2 */
72 #define REG_14 BPF_REG_0 /* Register 14 */
75 * Mapping of BPF registers to s390 registers
77 static const int reg2hex[] = {
80 /* Function parameters */
86 /* Call saved registers */
91 /* BPF stack pointer */
93 /* Register for blinding */
95 /* Work registers for s390x backend */
102 static inline u32 reg(u32 dst_reg, u32 src_reg)
104 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
107 static inline u32 reg_high(u32 reg)
109 return reg2hex[reg] << 4;
112 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
114 u32 r1 = reg2hex[b1];
116 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15)
117 jit->seen_reg[r1] = 1;
120 #define REG_SET_SEEN(b1) \
122 reg_set_seen(jit, b1); \
125 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
128 * EMIT macros for code generation
134 *(u16 *) (jit->prg_buf + jit->prg) = (op); \
138 #define EMIT2(op, b1, b2) \
140 _EMIT2((op) | reg(b1, b2)); \
148 *(u32 *) (jit->prg_buf + jit->prg) = (op); \
152 #define EMIT4(op, b1, b2) \
154 _EMIT4((op) | reg(b1, b2)); \
159 #define EMIT4_RRF(op, b1, b2, b3) \
161 _EMIT4((op) | reg_high(b3) << 8 | reg(b1, b2)); \
167 #define _EMIT4_DISP(op, disp) \
169 unsigned int __disp = (disp) & 0xfff; \
170 _EMIT4((op) | __disp); \
173 #define EMIT4_DISP(op, b1, b2, disp) \
175 _EMIT4_DISP((op) | reg_high(b1) << 16 | \
176 reg_high(b2) << 8, (disp)); \
181 #define EMIT4_IMM(op, b1, imm) \
183 unsigned int __imm = (imm) & 0xffff; \
184 _EMIT4((op) | reg_high(b1) << 16 | __imm); \
188 #define EMIT4_PCREL(op, pcrel) \
190 long __pcrel = ((pcrel) >> 1) & 0xffff; \
191 _EMIT4((op) | __pcrel); \
194 #define EMIT4_PCREL_RIC(op, mask, target) \
196 int __rel = ((target) - jit->prg) / 2; \
197 _EMIT4((op) | (mask) << 20 | (__rel & 0xffff)); \
200 #define _EMIT6(op1, op2) \
202 if (jit->prg_buf) { \
203 *(u32 *) (jit->prg_buf + jit->prg) = (op1); \
204 *(u16 *) (jit->prg_buf + jit->prg + 4) = (op2); \
209 #define _EMIT6_DISP(op1, op2, disp) \
211 unsigned int __disp = (disp) & 0xfff; \
212 _EMIT6((op1) | __disp, op2); \
215 #define _EMIT6_DISP_LH(op1, op2, disp) \
217 u32 _disp = (u32) (disp); \
218 unsigned int __disp_h = _disp & 0xff000; \
219 unsigned int __disp_l = _disp & 0x00fff; \
220 _EMIT6((op1) | __disp_l, (op2) | __disp_h >> 4); \
223 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
225 _EMIT6_DISP_LH((op1) | reg(b1, b2) << 16 | \
226 reg_high(b3) << 8, op2, disp); \
232 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
234 int rel = (jit->labels[label] - jit->prg) >> 1; \
235 _EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), \
236 (op2) | (mask) << 12); \
241 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
243 int rel = (jit->labels[label] - jit->prg) >> 1; \
244 _EMIT6((op1) | (reg_high(b1) | (mask)) << 16 | \
245 (rel & 0xffff), (op2) | ((imm) & 0xff) << 8); \
247 BUILD_BUG_ON(((unsigned long) (imm)) > 0xff); \
250 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
252 /* Branch instruction needs 6 bytes */ \
253 int rel = (addrs[(i) + (off) + 1] - (addrs[(i) + 1] - 6)) / 2;\
254 _EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), (op2) | (mask));\
259 #define EMIT6_PCREL_RILB(op, b, target) \
261 unsigned int rel = (int)((target) - jit->prg) / 2; \
262 _EMIT6((op) | reg_high(b) << 16 | rel >> 16, rel & 0xffff);\
266 #define EMIT6_PCREL_RIL(op, target) \
268 unsigned int rel = (int)((target) - jit->prg) / 2; \
269 _EMIT6((op) | rel >> 16, rel & 0xffff); \
272 #define EMIT6_PCREL_RILC(op, mask, target) \
274 EMIT6_PCREL_RIL((op) | (mask) << 20, (target)); \
277 #define _EMIT6_IMM(op, imm) \
279 unsigned int __imm = (imm); \
280 _EMIT6((op) | (__imm >> 16), __imm & 0xffff); \
283 #define EMIT6_IMM(op, b1, imm) \
285 _EMIT6_IMM((op) | reg_high(b1) << 16, imm); \
289 #define _EMIT_CONST_U32(val) \
294 *(u32 *)(jit->prg_buf + jit->lit32) = (u32)(val);\
299 #define EMIT_CONST_U32(val) \
301 jit->seen |= SEEN_LITERAL; \
302 _EMIT_CONST_U32(val) - jit->base_ip; \
305 #define _EMIT_CONST_U64(val) \
310 *(u64 *)(jit->prg_buf + jit->lit64) = (u64)(val);\
315 #define EMIT_CONST_U64(val) \
317 jit->seen |= SEEN_LITERAL; \
318 _EMIT_CONST_U64(val) - jit->base_ip; \
321 #define EMIT_ZERO(b1) \
323 if (!fp->aux->verifier_zext) { \
324 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
325 EMIT4(0xb9160000, b1, b1); \
331 * Return whether this is the first pass. The first pass is special, since we
332 * don't know any sizes yet, and thus must be conservative.
334 static bool is_first_pass(struct bpf_jit *jit)
336 return jit->size == 0;
340 * Return whether this is the code generation pass. The code generation pass is
341 * special, since we should change as little as possible.
343 static bool is_codegen_pass(struct bpf_jit *jit)
349 * Return whether "rel" can be encoded as a short PC-relative offset
351 static bool is_valid_rel(int rel)
353 return rel >= -65536 && rel <= 65534;
357 * Return whether "off" can be reached using a short PC-relative offset
359 static bool can_use_rel(struct bpf_jit *jit, int off)
361 return is_valid_rel(off - jit->prg);
365 * Return whether given displacement can be encoded using
366 * Long-Displacement Facility
368 static bool is_valid_ldisp(int disp)
370 return disp >= -524288 && disp <= 524287;
374 * Return whether the next 32-bit literal pool entry can be referenced using
375 * Long-Displacement Facility
377 static bool can_use_ldisp_for_lit32(struct bpf_jit *jit)
379 return is_valid_ldisp(jit->lit32 - jit->base_ip);
383 * Return whether the next 64-bit literal pool entry can be referenced using
384 * Long-Displacement Facility
386 static bool can_use_ldisp_for_lit64(struct bpf_jit *jit)
388 return is_valid_ldisp(jit->lit64 - jit->base_ip);
392 * Fill whole space with illegal instructions
394 static void jit_fill_hole(void *area, unsigned int size)
396 memset(area, 0, size);
400 * Save registers from "rs" (register start) to "re" (register end) on stack
402 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
404 u32 off = STK_OFF_R6 + (rs - 6) * 8;
407 /* stg %rs,off(%r15) */
408 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
410 /* stmg %rs,%re,off(%r15) */
411 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
415 * Restore registers from "rs" (register start) to "re" (register end) on stack
417 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re, u32 stack_depth)
419 u32 off = STK_OFF_R6 + (rs - 6) * 8;
421 if (jit->seen & SEEN_STACK)
422 off += STK_OFF + stack_depth;
425 /* lg %rs,off(%r15) */
426 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
428 /* lmg %rs,%re,off(%r15) */
429 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
433 * Return first seen register (from start)
435 static int get_start(struct bpf_jit *jit, int start)
439 for (i = start; i <= 15; i++) {
440 if (jit->seen_reg[i])
447 * Return last seen register (from start) (gap >= 2)
449 static int get_end(struct bpf_jit *jit, int start)
453 for (i = start; i < 15; i++) {
454 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
457 return jit->seen_reg[15] ? 15 : 14;
461 #define REGS_RESTORE 0
463 * Save and restore clobbered registers (6-15) on stack.
464 * We save/restore registers in chunks with gap >= 2 registers.
466 static void save_restore_regs(struct bpf_jit *jit, int op, u32 stack_depth)
468 const int last = 15, save_restore_size = 6;
471 if (is_first_pass(jit)) {
473 * We don't know yet which registers are used. Reserve space
476 jit->prg += (last - re + 1) * save_restore_size;
481 rs = get_start(jit, re);
484 re = get_end(jit, rs + 1);
486 save_regs(jit, rs, re);
488 restore_regs(jit, rs, re, stack_depth);
490 } while (re <= last);
494 * Emit function prologue
496 * Save registers and create stack frame if necessary.
497 * See stack frame layout desription in "bpf_jit.h"!
499 static void bpf_jit_prologue(struct bpf_jit *jit, u32 stack_depth)
501 if (jit->seen & SEEN_TAIL_CALL) {
502 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
503 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
505 /* j tail_call_start: NOP if no tail calls are used */
506 EMIT4_PCREL(0xa7f40000, 6);
508 EMIT2(0x0700, 0, REG_0);
510 /* Tail calls have to skip above initialization */
511 jit->tail_call_start = jit->prg;
513 save_restore_regs(jit, REGS_SAVE, stack_depth);
514 /* Setup literal pool */
515 if (is_first_pass(jit) || (jit->seen & SEEN_LITERAL)) {
516 if (!is_first_pass(jit) &&
517 is_valid_ldisp(jit->size - (jit->prg + 2))) {
519 EMIT2(0x0d00, REG_L, REG_0);
520 jit->base_ip = jit->prg;
522 /* larl %l,lit32_start */
523 EMIT6_PCREL_RILB(0xc0000000, REG_L, jit->lit32_start);
524 jit->base_ip = jit->lit32_start;
527 /* Setup stack and backchain */
528 if (is_first_pass(jit) || (jit->seen & SEEN_STACK)) {
529 if (is_first_pass(jit) || (jit->seen & SEEN_FUNC))
530 /* lgr %w1,%r15 (backchain) */
531 EMIT4(0xb9040000, REG_W1, REG_15);
532 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
533 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
534 /* aghi %r15,-STK_OFF */
535 EMIT4_IMM(0xa70b0000, REG_15, -(STK_OFF + stack_depth));
536 if (is_first_pass(jit) || (jit->seen & SEEN_FUNC))
537 /* stg %w1,152(%r15) (backchain) */
538 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
546 static void bpf_jit_epilogue(struct bpf_jit *jit, u32 stack_depth)
548 jit->exit_ip = jit->prg;
549 /* Load exit code: lgr %r2,%b0 */
550 EMIT4(0xb9040000, REG_2, BPF_REG_0);
551 /* Restore registers */
552 save_restore_regs(jit, REGS_RESTORE, stack_depth);
553 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) {
554 jit->r14_thunk_ip = jit->prg;
555 /* Generate __s390_indirect_jump_r14 thunk */
556 if (test_facility(35)) {
558 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
561 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14);
563 EMIT4_DISP(0x44000000, REG_0, REG_1, 0);
566 EMIT4_PCREL(0xa7f40000, 0);
571 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable &&
572 (is_first_pass(jit) || (jit->seen & SEEN_FUNC))) {
573 jit->r1_thunk_ip = jit->prg;
574 /* Generate __s390_indirect_jump_r1 thunk */
575 if (test_facility(35)) {
577 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
579 EMIT4_PCREL(0xa7f40000, 0);
583 /* ex 0,S390_lowcore.br_r1_tampoline */
584 EMIT4_DISP(0x44000000, REG_0, REG_0,
585 offsetof(struct lowcore, br_r1_trampoline));
587 EMIT4_PCREL(0xa7f40000, 0);
592 static int get_probe_mem_regno(const u8 *insn)
595 * insn must point to llgc, llgh, llgf or lg, which have destination
596 * register at the same position.
598 if (insn[0] != 0xe3) /* common llgc, llgh, llgf and lg prefix */
600 if (insn[5] != 0x90 && /* llgc */
601 insn[5] != 0x91 && /* llgh */
602 insn[5] != 0x16 && /* llgf */
603 insn[5] != 0x04) /* lg */
608 static bool ex_handler_bpf(const struct exception_table_entry *x,
609 struct pt_regs *regs)
614 regs->psw.addr = extable_fixup(x);
615 insn = (u8 *)__rewind_psw(regs->psw, regs->int_code >> 16);
616 regno = get_probe_mem_regno(insn);
617 if (WARN_ON_ONCE(regno < 0))
618 /* JIT bug - unexpected instruction. */
620 regs->gprs[regno] = 0;
624 static int bpf_jit_probe_mem(struct bpf_jit *jit, struct bpf_prog *fp,
625 int probe_prg, int nop_prg)
627 struct exception_table_entry *ex;
633 if (!fp->aux->extable)
634 /* Do nothing during early JIT passes. */
636 insn = jit->prg_buf + probe_prg;
637 if (WARN_ON_ONCE(get_probe_mem_regno(insn) < 0))
638 /* JIT bug - unexpected probe instruction. */
640 if (WARN_ON_ONCE(probe_prg + insn_length(*insn) != nop_prg))
641 /* JIT bug - gap between probe and nop instructions. */
643 for (i = 0; i < 2; i++) {
644 if (WARN_ON_ONCE(jit->excnt >= fp->aux->num_exentries))
645 /* Verifier bug - not enough entries. */
647 ex = &fp->aux->extable[jit->excnt];
648 /* Add extable entries for probe and nop instructions. */
649 prg = i == 0 ? probe_prg : nop_prg;
650 delta = jit->prg_buf + prg - (u8 *)&ex->insn;
651 if (WARN_ON_ONCE(delta < INT_MIN || delta > INT_MAX))
652 /* JIT bug - code and extable must be close. */
656 * Always land on the nop. Note that extable infrastructure
657 * ignores fixup field, it is handled by ex_handler_bpf().
659 delta = jit->prg_buf + nop_prg - (u8 *)&ex->fixup;
660 if (WARN_ON_ONCE(delta < INT_MIN || delta > INT_MAX))
661 /* JIT bug - landing pad and extable must be close. */
664 ex->handler = (u8 *)ex_handler_bpf - (u8 *)&ex->handler;
671 * Compile one eBPF instruction into s390x code
673 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
674 * stack space for the large switch statement.
676 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp,
677 int i, bool extra_pass, u32 stack_depth)
679 struct bpf_insn *insn = &fp->insnsi[i];
680 u32 dst_reg = insn->dst_reg;
681 u32 src_reg = insn->src_reg;
682 int last, insn_count = 1;
683 u32 *addrs = jit->addrs;
691 if (BPF_CLASS(insn->code) == BPF_LDX &&
692 BPF_MODE(insn->code) == BPF_PROBE_MEM)
693 probe_prg = jit->prg;
695 switch (insn->code) {
699 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
700 /* llgfr %dst,%src */
701 EMIT4(0xb9160000, dst_reg, src_reg);
702 if (insn_is_zext(&insn[1]))
705 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
707 EMIT4(0xb9040000, dst_reg, src_reg);
709 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
711 EMIT6_IMM(0xc00f0000, dst_reg, imm);
712 if (insn_is_zext(&insn[1]))
715 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
717 EMIT6_IMM(0xc0010000, dst_reg, imm);
722 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
724 /* 16 byte instruction that uses two 'struct bpf_insn' */
727 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
729 EMIT6_PCREL_RILB(0xc4080000, dst_reg, _EMIT_CONST_U64(imm64));
736 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
738 EMIT2(0x1a00, dst_reg, src_reg);
741 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
743 EMIT4(0xb9080000, dst_reg, src_reg);
745 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
749 EMIT6_IMM(0xc20b0000, dst_reg, imm);
752 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
756 EMIT6_IMM(0xc2080000, dst_reg, imm);
761 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
763 EMIT2(0x1b00, dst_reg, src_reg);
766 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
768 EMIT4(0xb9090000, dst_reg, src_reg);
770 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
774 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
777 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
781 EMIT6_IMM(0xc2080000, dst_reg, -imm);
786 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
788 EMIT4(0xb2520000, dst_reg, src_reg);
791 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
793 EMIT4(0xb90c0000, dst_reg, src_reg);
795 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
799 EMIT6_IMM(0xc2010000, dst_reg, imm);
802 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
806 EMIT6_IMM(0xc2000000, dst_reg, imm);
811 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
812 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
814 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
817 EMIT4_IMM(0xa7080000, REG_W0, 0);
819 EMIT2(0x1800, REG_W1, dst_reg);
821 EMIT4(0xb9970000, REG_W0, src_reg);
823 EMIT4(0xb9160000, dst_reg, rc_reg);
824 if (insn_is_zext(&insn[1]))
828 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
829 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
831 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
834 EMIT4_IMM(0xa7090000, REG_W0, 0);
836 EMIT4(0xb9040000, REG_W1, dst_reg);
838 EMIT4(0xb9870000, REG_W0, src_reg);
840 EMIT4(0xb9040000, dst_reg, rc_reg);
843 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
844 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
846 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
849 if (BPF_OP(insn->code) == BPF_MOD)
851 EMIT4_IMM(0xa7090000, dst_reg, 0);
855 EMIT4_IMM(0xa7080000, REG_W0, 0);
857 EMIT2(0x1800, REG_W1, dst_reg);
858 if (!is_first_pass(jit) && can_use_ldisp_for_lit32(jit)) {
859 /* dl %w0,<d(imm)>(%l) */
860 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
861 EMIT_CONST_U32(imm));
864 EMIT6_PCREL_RILB(0xc40c0000, dst_reg,
865 _EMIT_CONST_U32(imm));
866 jit->seen |= SEEN_LITERAL;
868 EMIT4(0xb9970000, REG_W0, dst_reg);
871 EMIT4(0xb9160000, dst_reg, rc_reg);
872 if (insn_is_zext(&insn[1]))
876 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
877 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
879 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
882 if (BPF_OP(insn->code) == BPF_MOD)
884 EMIT4_IMM(0xa7090000, dst_reg, 0);
888 EMIT4_IMM(0xa7090000, REG_W0, 0);
890 EMIT4(0xb9040000, REG_W1, dst_reg);
891 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
892 /* dlg %w0,<d(imm)>(%l) */
893 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
894 EMIT_CONST_U64(imm));
897 EMIT6_PCREL_RILB(0xc4080000, dst_reg,
898 _EMIT_CONST_U64(imm));
899 jit->seen |= SEEN_LITERAL;
901 EMIT4(0xb9870000, REG_W0, dst_reg);
904 EMIT4(0xb9040000, dst_reg, rc_reg);
910 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
912 EMIT2(0x1400, dst_reg, src_reg);
915 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
917 EMIT4(0xb9800000, dst_reg, src_reg);
919 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
921 EMIT6_IMM(0xc00b0000, dst_reg, imm);
924 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
925 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
926 /* ng %dst,<d(imm)>(%l) */
927 EMIT6_DISP_LH(0xe3000000, 0x0080,
928 dst_reg, REG_0, REG_L,
929 EMIT_CONST_U64(imm));
932 EMIT6_PCREL_RILB(0xc4080000, REG_W0,
933 _EMIT_CONST_U64(imm));
934 jit->seen |= SEEN_LITERAL;
936 EMIT4(0xb9800000, dst_reg, REG_W0);
942 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
944 EMIT2(0x1600, dst_reg, src_reg);
947 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
949 EMIT4(0xb9810000, dst_reg, src_reg);
951 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
953 EMIT6_IMM(0xc00d0000, dst_reg, imm);
956 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
957 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
958 /* og %dst,<d(imm)>(%l) */
959 EMIT6_DISP_LH(0xe3000000, 0x0081,
960 dst_reg, REG_0, REG_L,
961 EMIT_CONST_U64(imm));
964 EMIT6_PCREL_RILB(0xc4080000, REG_W0,
965 _EMIT_CONST_U64(imm));
966 jit->seen |= SEEN_LITERAL;
968 EMIT4(0xb9810000, dst_reg, REG_W0);
974 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
976 EMIT2(0x1700, dst_reg, src_reg);
979 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
981 EMIT4(0xb9820000, dst_reg, src_reg);
983 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
987 EMIT6_IMM(0xc0070000, dst_reg, imm);
990 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
991 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
992 /* xg %dst,<d(imm)>(%l) */
993 EMIT6_DISP_LH(0xe3000000, 0x0082,
994 dst_reg, REG_0, REG_L,
995 EMIT_CONST_U64(imm));
998 EMIT6_PCREL_RILB(0xc4080000, REG_W0,
999 _EMIT_CONST_U64(imm));
1000 jit->seen |= SEEN_LITERAL;
1002 EMIT4(0xb9820000, dst_reg, REG_W0);
1008 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
1009 /* sll %dst,0(%src) */
1010 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
1013 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
1014 /* sllg %dst,%dst,0(%src) */
1015 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
1017 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
1020 /* sll %dst,imm(%r0) */
1021 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
1024 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
1027 /* sllg %dst,%dst,imm(%r0) */
1028 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
1033 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
1034 /* srl %dst,0(%src) */
1035 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
1038 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
1039 /* srlg %dst,%dst,0(%src) */
1040 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
1042 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
1045 /* srl %dst,imm(%r0) */
1046 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
1049 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
1052 /* srlg %dst,%dst,imm(%r0) */
1053 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
1058 case BPF_ALU | BPF_ARSH | BPF_X: /* ((s32) dst) >>= src */
1059 /* sra %dst,%dst,0(%src) */
1060 EMIT4_DISP(0x8a000000, dst_reg, src_reg, 0);
1063 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
1064 /* srag %dst,%dst,0(%src) */
1065 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
1067 case BPF_ALU | BPF_ARSH | BPF_K: /* ((s32) dst >> imm */
1070 /* sra %dst,imm(%r0) */
1071 EMIT4_DISP(0x8a000000, dst_reg, REG_0, imm);
1074 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
1077 /* srag %dst,%dst,imm(%r0) */
1078 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
1083 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
1085 EMIT2(0x1300, dst_reg, dst_reg);
1088 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
1089 /* lcgr %dst,%dst */
1090 EMIT4(0xb9030000, dst_reg, dst_reg);
1095 case BPF_ALU | BPF_END | BPF_FROM_BE:
1096 /* s390 is big endian, therefore only clear high order bytes */
1098 case 16: /* dst = (u16) cpu_to_be16(dst) */
1099 /* llghr %dst,%dst */
1100 EMIT4(0xb9850000, dst_reg, dst_reg);
1101 if (insn_is_zext(&insn[1]))
1104 case 32: /* dst = (u32) cpu_to_be32(dst) */
1105 if (!fp->aux->verifier_zext)
1106 /* llgfr %dst,%dst */
1107 EMIT4(0xb9160000, dst_reg, dst_reg);
1109 case 64: /* dst = (u64) cpu_to_be64(dst) */
1113 case BPF_ALU | BPF_END | BPF_FROM_LE:
1115 case 16: /* dst = (u16) cpu_to_le16(dst) */
1116 /* lrvr %dst,%dst */
1117 EMIT4(0xb91f0000, dst_reg, dst_reg);
1118 /* srl %dst,16(%r0) */
1119 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
1120 /* llghr %dst,%dst */
1121 EMIT4(0xb9850000, dst_reg, dst_reg);
1122 if (insn_is_zext(&insn[1]))
1125 case 32: /* dst = (u32) cpu_to_le32(dst) */
1126 /* lrvr %dst,%dst */
1127 EMIT4(0xb91f0000, dst_reg, dst_reg);
1128 if (!fp->aux->verifier_zext)
1129 /* llgfr %dst,%dst */
1130 EMIT4(0xb9160000, dst_reg, dst_reg);
1132 case 64: /* dst = (u64) cpu_to_le64(dst) */
1133 /* lrvgr %dst,%dst */
1134 EMIT4(0xb90f0000, dst_reg, dst_reg);
1141 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
1142 /* stcy %src,off(%dst) */
1143 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
1144 jit->seen |= SEEN_MEM;
1146 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
1147 /* sthy %src,off(%dst) */
1148 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
1149 jit->seen |= SEEN_MEM;
1151 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
1152 /* sty %src,off(%dst) */
1153 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
1154 jit->seen |= SEEN_MEM;
1156 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
1157 /* stg %src,off(%dst) */
1158 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
1159 jit->seen |= SEEN_MEM;
1161 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
1163 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
1164 /* stcy %w0,off(dst) */
1165 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
1166 jit->seen |= SEEN_MEM;
1168 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
1170 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
1171 /* sthy %w0,off(dst) */
1172 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
1173 jit->seen |= SEEN_MEM;
1175 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
1177 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
1178 /* sty %w0,off(%dst) */
1179 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
1180 jit->seen |= SEEN_MEM;
1182 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
1184 EMIT6_IMM(0xc0010000, REG_W0, imm);
1185 /* stg %w0,off(%dst) */
1186 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
1187 jit->seen |= SEEN_MEM;
1190 * BPF_STX XADD (atomic_add)
1192 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
1193 /* laal %w0,%src,off(%dst) */
1194 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
1196 jit->seen |= SEEN_MEM;
1198 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
1199 /* laalg %w0,%src,off(%dst) */
1200 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
1202 jit->seen |= SEEN_MEM;
1207 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
1208 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
1209 /* llgc %dst,0(off,%src) */
1210 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
1211 jit->seen |= SEEN_MEM;
1212 if (insn_is_zext(&insn[1]))
1215 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
1216 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
1217 /* llgh %dst,0(off,%src) */
1218 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
1219 jit->seen |= SEEN_MEM;
1220 if (insn_is_zext(&insn[1]))
1223 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
1224 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
1225 /* llgf %dst,off(%src) */
1226 jit->seen |= SEEN_MEM;
1227 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
1228 if (insn_is_zext(&insn[1]))
1231 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
1232 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
1233 /* lg %dst,0(off,%src) */
1234 jit->seen |= SEEN_MEM;
1235 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
1240 case BPF_JMP | BPF_CALL:
1243 bool func_addr_fixed;
1246 ret = bpf_jit_get_func_addr(fp, insn, extra_pass,
1247 &func, &func_addr_fixed);
1251 REG_SET_SEEN(BPF_REG_5);
1252 jit->seen |= SEEN_FUNC;
1254 EMIT6_PCREL_RILB(0xc4080000, REG_W1, _EMIT_CONST_U64(func));
1255 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) {
1256 /* brasl %r14,__s390_indirect_jump_r1 */
1257 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip);
1260 EMIT2(0x0d00, REG_14, REG_W1);
1262 /* lgr %b0,%r2: load return value into %b0 */
1263 EMIT4(0xb9040000, BPF_REG_0, REG_2);
1266 case BPF_JMP | BPF_TAIL_CALL:
1269 * B1: pointer to ctx
1270 * B2: pointer to bpf_array
1271 * B3: index in bpf_array
1273 jit->seen |= SEEN_TAIL_CALL;
1276 * if (index >= array->map.max_entries)
1280 /* llgf %w1,map.max_entries(%b2) */
1281 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
1282 offsetof(struct bpf_array, map.max_entries));
1283 /* if ((u32)%b3 >= (u32)%w1) goto out; */
1284 if (!is_first_pass(jit) && can_use_rel(jit, jit->labels[0])) {
1285 /* clrj %b3,%w1,0xa,label0 */
1286 EMIT6_PCREL_LABEL(0xec000000, 0x0077, BPF_REG_3,
1290 EMIT2(0x1500, BPF_REG_3, REG_W1);
1291 /* brcl 0xa,label0 */
1292 EMIT6_PCREL_RILC(0xc0040000, 0xa, jit->labels[0]);
1296 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1300 if (jit->seen & SEEN_STACK)
1301 off = STK_OFF_TCCNT + STK_OFF + stack_depth;
1303 off = STK_OFF_TCCNT;
1305 EMIT4_IMM(0xa7080000, REG_W0, 1);
1306 /* laal %w1,%w0,off(%r15) */
1307 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1308 if (!is_first_pass(jit) && can_use_rel(jit, jit->labels[0])) {
1309 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1310 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1,
1311 MAX_TAIL_CALL_CNT, 0, 0x2);
1313 /* clfi %w1,MAX_TAIL_CALL_CNT */
1314 EMIT6_IMM(0xc20f0000, REG_W1, MAX_TAIL_CALL_CNT);
1315 /* brcl 0x2,label0 */
1316 EMIT6_PCREL_RILC(0xc0040000, 0x2, jit->labels[0]);
1320 * prog = array->ptrs[index];
1325 /* llgfr %r1,%b3: %r1 = (u32) index */
1326 EMIT4(0xb9160000, REG_1, BPF_REG_3);
1327 /* sllg %r1,%r1,3: %r1 *= 8 */
1328 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, REG_1, REG_0, 3);
1329 /* ltg %r1,prog(%b2,%r1) */
1330 EMIT6_DISP_LH(0xe3000000, 0x0002, REG_1, BPF_REG_2,
1331 REG_1, offsetof(struct bpf_array, ptrs));
1332 if (!is_first_pass(jit) && can_use_rel(jit, jit->labels[0])) {
1333 /* brc 0x8,label0 */
1334 EMIT4_PCREL_RIC(0xa7040000, 0x8, jit->labels[0]);
1336 /* brcl 0x8,label0 */
1337 EMIT6_PCREL_RILC(0xc0040000, 0x8, jit->labels[0]);
1341 * Restore registers before calling function
1343 save_restore_regs(jit, REGS_RESTORE, stack_depth);
1346 * goto *(prog->bpf_func + tail_call_start);
1349 /* lg %r1,bpf_func(%r1) */
1350 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1351 offsetof(struct bpf_prog, bpf_func));
1352 /* bc 0xf,tail_call_start(%r1) */
1353 _EMIT4(0x47f01000 + jit->tail_call_start);
1355 jit->labels[0] = jit->prg;
1357 case BPF_JMP | BPF_EXIT: /* return b0 */
1358 last = (i == fp->len - 1) ? 1 : 0;
1362 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg);
1365 * Branch relative (number of skipped instructions) to offset on
1368 * Condition code to mask mapping:
1370 * CC | Description | Mask
1371 * ------------------------------
1372 * 0 | Operands equal | 8
1373 * 1 | First operand low | 4
1374 * 2 | First operand high | 2
1377 * For s390x relative branches: ip = ip + off_bytes
1378 * For BPF relative branches: insn = insn + off_insns + 1
1380 * For example for s390x with offset 0 we jump to the branch
1381 * instruction itself (loop) and for BPF with offset 0 we
1382 * branch to the instruction behind the branch.
1384 case BPF_JMP | BPF_JA: /* if (true) */
1385 mask = 0xf000; /* j */
1387 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1388 case BPF_JMP32 | BPF_JSGT | BPF_K: /* ((s32) dst > (s32) imm) */
1389 mask = 0x2000; /* jh */
1391 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */
1392 case BPF_JMP32 | BPF_JSLT | BPF_K: /* ((s32) dst < (s32) imm) */
1393 mask = 0x4000; /* jl */
1395 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1396 case BPF_JMP32 | BPF_JSGE | BPF_K: /* ((s32) dst >= (s32) imm) */
1397 mask = 0xa000; /* jhe */
1399 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */
1400 case BPF_JMP32 | BPF_JSLE | BPF_K: /* ((s32) dst <= (s32) imm) */
1401 mask = 0xc000; /* jle */
1403 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1404 case BPF_JMP32 | BPF_JGT | BPF_K: /* ((u32) dst_reg > (u32) imm) */
1405 mask = 0x2000; /* jh */
1407 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */
1408 case BPF_JMP32 | BPF_JLT | BPF_K: /* ((u32) dst_reg < (u32) imm) */
1409 mask = 0x4000; /* jl */
1411 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1412 case BPF_JMP32 | BPF_JGE | BPF_K: /* ((u32) dst_reg >= (u32) imm) */
1413 mask = 0xa000; /* jhe */
1415 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */
1416 case BPF_JMP32 | BPF_JLE | BPF_K: /* ((u32) dst_reg <= (u32) imm) */
1417 mask = 0xc000; /* jle */
1419 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1420 case BPF_JMP32 | BPF_JNE | BPF_K: /* ((u32) dst_reg != (u32) imm) */
1421 mask = 0x7000; /* jne */
1423 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1424 case BPF_JMP32 | BPF_JEQ | BPF_K: /* ((u32) dst_reg == (u32) imm) */
1425 mask = 0x8000; /* je */
1427 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1428 case BPF_JMP32 | BPF_JSET | BPF_K: /* ((u32) dst_reg & (u32) imm) */
1429 mask = 0x7000; /* jnz */
1430 if (BPF_CLASS(insn->code) == BPF_JMP32) {
1431 /* llilf %w1,imm (load zero extend imm) */
1432 EMIT6_IMM(0xc00f0000, REG_W1, imm);
1434 EMIT2(0x1400, REG_W1, dst_reg);
1436 /* lgfi %w1,imm (load sign extend imm) */
1437 EMIT6_IMM(0xc0010000, REG_W1, imm);
1439 EMIT4(0xb9800000, REG_W1, dst_reg);
1443 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1444 case BPF_JMP32 | BPF_JSGT | BPF_X: /* ((s32) dst > (s32) src) */
1445 mask = 0x2000; /* jh */
1447 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */
1448 case BPF_JMP32 | BPF_JSLT | BPF_X: /* ((s32) dst < (s32) src) */
1449 mask = 0x4000; /* jl */
1451 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1452 case BPF_JMP32 | BPF_JSGE | BPF_X: /* ((s32) dst >= (s32) src) */
1453 mask = 0xa000; /* jhe */
1455 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */
1456 case BPF_JMP32 | BPF_JSLE | BPF_X: /* ((s32) dst <= (s32) src) */
1457 mask = 0xc000; /* jle */
1459 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1460 case BPF_JMP32 | BPF_JGT | BPF_X: /* ((u32) dst > (u32) src) */
1461 mask = 0x2000; /* jh */
1463 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */
1464 case BPF_JMP32 | BPF_JLT | BPF_X: /* ((u32) dst < (u32) src) */
1465 mask = 0x4000; /* jl */
1467 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1468 case BPF_JMP32 | BPF_JGE | BPF_X: /* ((u32) dst >= (u32) src) */
1469 mask = 0xa000; /* jhe */
1471 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */
1472 case BPF_JMP32 | BPF_JLE | BPF_X: /* ((u32) dst <= (u32) src) */
1473 mask = 0xc000; /* jle */
1475 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1476 case BPF_JMP32 | BPF_JNE | BPF_X: /* ((u32) dst != (u32) src) */
1477 mask = 0x7000; /* jne */
1479 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1480 case BPF_JMP32 | BPF_JEQ | BPF_X: /* ((u32) dst == (u32) src) */
1481 mask = 0x8000; /* je */
1483 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1484 case BPF_JMP32 | BPF_JSET | BPF_X: /* ((u32) dst & (u32) src) */
1486 bool is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1488 mask = 0x7000; /* jnz */
1489 /* nrk or ngrk %w1,%dst,%src */
1490 EMIT4_RRF((is_jmp32 ? 0xb9f40000 : 0xb9e40000),
1491 REG_W1, dst_reg, src_reg);
1494 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1495 /* cfi or cgfi %dst,imm */
1496 EMIT6_IMM(is_jmp32 ? 0xc20d0000 : 0xc20c0000,
1498 if (!is_first_pass(jit) &&
1499 can_use_rel(jit, addrs[i + off + 1])) {
1501 EMIT4_PCREL_RIC(0xa7040000,
1502 mask >> 12, addrs[i + off + 1]);
1505 EMIT6_PCREL_RILC(0xc0040000,
1506 mask >> 12, addrs[i + off + 1]);
1510 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1511 /* clfi or clgfi %dst,imm */
1512 EMIT6_IMM(is_jmp32 ? 0xc20f0000 : 0xc20e0000,
1514 if (!is_first_pass(jit) &&
1515 can_use_rel(jit, addrs[i + off + 1])) {
1517 EMIT4_PCREL_RIC(0xa7040000,
1518 mask >> 12, addrs[i + off + 1]);
1521 EMIT6_PCREL_RILC(0xc0040000,
1522 mask >> 12, addrs[i + off + 1]);
1526 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1527 if (!is_first_pass(jit) &&
1528 can_use_rel(jit, addrs[i + off + 1])) {
1529 /* crj or cgrj %dst,%src,mask,off */
1530 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0076 : 0x0064),
1531 dst_reg, src_reg, i, off, mask);
1533 /* cr or cgr %dst,%src */
1535 EMIT2(0x1900, dst_reg, src_reg);
1537 EMIT4(0xb9200000, dst_reg, src_reg);
1539 EMIT6_PCREL_RILC(0xc0040000,
1540 mask >> 12, addrs[i + off + 1]);
1544 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1545 if (!is_first_pass(jit) &&
1546 can_use_rel(jit, addrs[i + off + 1])) {
1547 /* clrj or clgrj %dst,%src,mask,off */
1548 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0077 : 0x0065),
1549 dst_reg, src_reg, i, off, mask);
1551 /* clr or clgr %dst,%src */
1553 EMIT2(0x1500, dst_reg, src_reg);
1555 EMIT4(0xb9210000, dst_reg, src_reg);
1557 EMIT6_PCREL_RILC(0xc0040000,
1558 mask >> 12, addrs[i + off + 1]);
1562 if (!is_first_pass(jit) &&
1563 can_use_rel(jit, addrs[i + off + 1])) {
1565 EMIT4_PCREL_RIC(0xa7040000,
1566 mask >> 12, addrs[i + off + 1]);
1569 EMIT6_PCREL_RILC(0xc0040000,
1570 mask >> 12, addrs[i + off + 1]);
1574 default: /* too complex, give up */
1575 pr_err("Unknown opcode %02x\n", insn->code);
1579 if (probe_prg != -1) {
1581 * Handlers of certain exceptions leave psw.addr pointing to
1582 * the instruction directly after the failing one. Therefore,
1583 * create two exception table entries and also add a nop in
1584 * case two probing instructions come directly after each
1590 err = bpf_jit_probe_mem(jit, fp, probe_prg, nop_prg);
1599 * Return whether new i-th instruction address does not violate any invariant
1601 static bool bpf_is_new_addr_sane(struct bpf_jit *jit, int i)
1603 /* On the first pass anything goes */
1604 if (is_first_pass(jit))
1607 /* The codegen pass must not change anything */
1608 if (is_codegen_pass(jit))
1609 return jit->addrs[i] == jit->prg;
1611 /* Passes in between must not increase code size */
1612 return jit->addrs[i] >= jit->prg;
1616 * Update the address of i-th instruction
1618 static int bpf_set_addr(struct bpf_jit *jit, int i)
1620 if (!bpf_is_new_addr_sane(jit, i))
1622 jit->addrs[i] = jit->prg;
1627 * Compile eBPF program into s390x code
1629 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp,
1630 bool extra_pass, u32 stack_depth)
1632 int i, insn_count, lit32_size, lit64_size;
1634 jit->lit32 = jit->lit32_start;
1635 jit->lit64 = jit->lit64_start;
1639 bpf_jit_prologue(jit, stack_depth);
1640 if (bpf_set_addr(jit, 0) < 0)
1642 for (i = 0; i < fp->len; i += insn_count) {
1643 insn_count = bpf_jit_insn(jit, fp, i, extra_pass, stack_depth);
1646 /* Next instruction address */
1647 if (bpf_set_addr(jit, i + insn_count) < 0)
1650 bpf_jit_epilogue(jit, stack_depth);
1652 lit32_size = jit->lit32 - jit->lit32_start;
1653 lit64_size = jit->lit64 - jit->lit64_start;
1654 jit->lit32_start = jit->prg;
1656 jit->lit32_start = ALIGN(jit->lit32_start, 4);
1657 jit->lit64_start = jit->lit32_start + lit32_size;
1659 jit->lit64_start = ALIGN(jit->lit64_start, 8);
1660 jit->size = jit->lit64_start + lit64_size;
1661 jit->size_prg = jit->prg;
1663 if (WARN_ON_ONCE(fp->aux->extable &&
1664 jit->excnt != fp->aux->num_exentries))
1665 /* Verifier bug - too many entries. */
1671 bool bpf_jit_needs_zext(void)
1676 struct s390_jit_data {
1677 struct bpf_binary_header *header;
1682 static struct bpf_binary_header *bpf_jit_alloc(struct bpf_jit *jit,
1683 struct bpf_prog *fp)
1685 struct bpf_binary_header *header;
1689 /* We need two entries per insn. */
1690 fp->aux->num_exentries *= 2;
1692 code_size = roundup(jit->size,
1693 __alignof__(struct exception_table_entry));
1694 extable_size = fp->aux->num_exentries *
1695 sizeof(struct exception_table_entry);
1696 header = bpf_jit_binary_alloc(code_size + extable_size, &jit->prg_buf,
1700 fp->aux->extable = (struct exception_table_entry *)
1701 (jit->prg_buf + code_size);
1706 * Compile eBPF program "fp"
1708 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
1710 u32 stack_depth = round_up(fp->aux->stack_depth, 8);
1711 struct bpf_prog *tmp, *orig_fp = fp;
1712 struct bpf_binary_header *header;
1713 struct s390_jit_data *jit_data;
1714 bool tmp_blinded = false;
1715 bool extra_pass = false;
1719 if (!fp->jit_requested)
1722 tmp = bpf_jit_blind_constants(fp);
1724 * If blinding was requested and we failed during blinding,
1725 * we must fall back to the interpreter.
1734 jit_data = fp->aux->jit_data;
1736 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
1741 fp->aux->jit_data = jit_data;
1743 if (jit_data->ctx.addrs) {
1744 jit = jit_data->ctx;
1745 header = jit_data->header;
1747 pass = jit_data->pass + 1;
1751 memset(&jit, 0, sizeof(jit));
1752 jit.addrs = kvcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1753 if (jit.addrs == NULL) {
1758 * Three initial passes:
1759 * - 1/2: Determine clobbered registers
1760 * - 3: Calculate program size and addrs arrray
1762 for (pass = 1; pass <= 3; pass++) {
1763 if (bpf_jit_prog(&jit, fp, extra_pass, stack_depth)) {
1769 * Final pass: Allocate and generate program
1771 header = bpf_jit_alloc(&jit, fp);
1777 if (bpf_jit_prog(&jit, fp, extra_pass, stack_depth)) {
1778 bpf_jit_binary_free(header);
1782 if (bpf_jit_enable > 1) {
1783 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1784 print_fn_code(jit.prg_buf, jit.size_prg);
1786 if (!fp->is_func || extra_pass) {
1787 bpf_jit_binary_lock_ro(header);
1789 jit_data->header = header;
1790 jit_data->ctx = jit;
1791 jit_data->pass = pass;
1793 fp->bpf_func = (void *) jit.prg_buf;
1795 fp->jited_len = jit.size;
1797 if (!fp->is_func || extra_pass) {
1798 bpf_prog_fill_jited_linfo(fp, jit.addrs + 1);
1802 fp->aux->jit_data = NULL;
1806 bpf_jit_prog_release_other(fp, fp == orig_fp ?