1 /* SPDX-License-Identifier: GPL-2.0 */
3 * S390 low-level entry points.
5 * Copyright IBM Corp. 1999, 2012
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
11 #include <linux/init.h>
12 #include <linux/linkage.h>
13 #include <asm/alternative-asm.h>
14 #include <asm/processor.h>
15 #include <asm/cache.h>
16 #include <asm/dwarf.h>
17 #include <asm/errno.h>
18 #include <asm/ptrace.h>
19 #include <asm/thread_info.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/unistd.h>
25 #include <asm/vx-insn.h>
26 #include <asm/setup.h>
28 #include <asm/export.h>
29 #include <asm/nospec-insn.h>
32 __PT_R1 = __PT_GPRS + 8
33 __PT_R2 = __PT_GPRS + 16
34 __PT_R3 = __PT_GPRS + 24
35 __PT_R4 = __PT_GPRS + 32
36 __PT_R5 = __PT_GPRS + 40
37 __PT_R6 = __PT_GPRS + 48
38 __PT_R7 = __PT_GPRS + 56
39 __PT_R8 = __PT_GPRS + 64
40 __PT_R9 = __PT_GPRS + 72
41 __PT_R10 = __PT_GPRS + 80
42 __PT_R11 = __PT_GPRS + 88
43 __PT_R12 = __PT_GPRS + 96
44 __PT_R13 = __PT_GPRS + 104
45 __PT_R14 = __PT_GPRS + 112
46 __PT_R15 = __PT_GPRS + 120
48 STACK_SHIFT = PAGE_SHIFT + THREAD_SIZE_ORDER
49 STACK_SIZE = 1 << STACK_SHIFT
50 STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
52 _LPP_OFFSET = __LC_LPP
55 ALTERNATIVE "", ".insn s,0xb2010000,\address", 193
59 ALTERNATIVE "", ".insn s,0xb2000000,\address", 193
62 .macro LPSWEY address,lpswe
63 ALTERNATIVE "b \lpswe", ".insn siy,0xeb0000000071,\address,0", 193
67 ALTERNATIVE "", __stringify(mvc __PT_LAST_BREAK(8,\reg),__LC_LAST_BREAK), 193
70 .macro CHECK_STACK savearea
71 #ifdef CONFIG_CHECK_STACK
72 tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
78 .macro CHECK_VMAP_STACK savearea,oklabel
79 #ifdef CONFIG_VMAP_STACK
81 nill %r14,0x10000 - STACK_SIZE
83 clg %r14,__LC_KERNEL_STACK
85 clg %r14,__LC_ASYNC_STACK
87 clg %r14,__LC_MCCK_STACK
89 clg %r14,__LC_NODAT_STACK
91 clg %r14,__LC_RESTART_STACK
101 ALTERNATIVE ".insn s,0xb2050000,\savearea", \
102 ".insn s,0xb27c0000,\savearea", 25
106 * The TSTMSK macro generates a test-under-mask instruction by
107 * calculating the memory offset for the specified mask value.
108 * Mask value can be any constant. The macro shifts the mask
109 * value to calculate the memory offset for the test-under-mask
112 .macro TSTMSK addr, mask, size=8, bytepos=0
113 .if (\bytepos < \size) && (\mask >> 8)
115 .error "Mask exceeds byte boundary"
117 TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)"
121 .error "Mask must not be zero"
123 off = \size - \bytepos - 1
128 ALTERNATIVE "", ".long 0xb2e8c000", 82
132 ALTERNATIVE "", ".long 0xb2e8d000", 82
135 .macro BPENTER tif_ptr,tif_mask
136 ALTERNATIVE "TSTMSK \tif_ptr,\tif_mask; jz .+8; .long 0xb2e8d000", \
140 .macro BPEXIT tif_ptr,tif_mask
141 TSTMSK \tif_ptr,\tif_mask
142 ALTERNATIVE "jz .+8; .long 0xb2e8c000", \
143 "jnz .+8; .long 0xb2e8d000", 82
147 * The CHKSTG macro jumps to the provided label in case the
148 * machine check interruption code reports one of unrecoverable
150 * - Storage error uncorrected
151 * - Storage key error uncorrected
152 * - Storage degradation with Failing-storage-address validity
154 .macro CHKSTG errlabel
155 TSTMSK __LC_MCCK_CODE,(MCCK_CODE_STG_ERROR|MCCK_CODE_STG_KEY_ERROR)
157 TSTMSK __LC_MCCK_CODE,MCCK_CODE_STG_DEGRAD
159 TSTMSK __LC_MCCK_CODE,MCCK_CODE_STG_FAIL_ADDR
164 #if IS_ENABLED(CONFIG_KVM)
166 * The OUTSIDE macro jumps to the provided label in case the value
167 * in the provided register is outside of the provided range. The
168 * macro is useful for checking whether a PSW stored in a register
169 * pair points inside or outside of a block of instructions.
170 * @reg: register to check
171 * @start: start of the range
172 * @end: end of the range
173 * @outside_label: jump here if @reg is outside of [@start..@end)
175 .macro OUTSIDE reg,start,end,outside_label
179 lghi %r13,\end - \start
185 lg %r9,__SF_SIE_CONTROL(%r15) # get control block pointer
186 ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE
187 lctlg %c1,%c1,__LC_KERNEL_ASCE # load primary asce
188 larl %r9,sie_exit # skip forward to sie_exit
193 GEN_BR_THUNK %r14,%r13
195 .section .kprobes.text, "ax"
198 * This nop exists only in order to avoid that __bpon starts at
199 * the beginning of the kprobes text section. In that case we would
200 * have several symbols at the same address. E.g. objdump would take
201 * an arbitrary symbol name when disassembling this code.
202 * With the added nop in between the __bpon symbol is unique
214 * Scheduler resume function, called by switch_to
215 * gpr2 = (task_struct *) prev
216 * gpr3 = (task_struct *) next
221 stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task
222 lghi %r4,__TASK_stack
223 lghi %r1,__TASK_thread
225 stg %r15,__THREAD_ksp(%r1,%r2) # store kernel stack of prev
226 lg %r15,0(%r4,%r3) # start of kernel stack of next
227 agr %r15,%r5 # end of kernel stack of next
228 stg %r3,__LC_CURRENT # store task struct of next
229 stg %r15,__LC_KERNEL_STACK # store end of kernel stack
230 lg %r15,__THREAD_ksp(%r1,%r3) # load kernel stack of next
232 mvc __LC_CURRENT_PID(4,%r0),0(%r3) # store pid of next
233 lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
234 ALTERNATIVE "", ".insn s,0xb2800000,_LPP_OFFSET", 40
238 #if IS_ENABLED(CONFIG_KVM)
240 * sie64a calling convention:
241 * %r2 pointer to sie control block
242 * %r3 guest register save area
245 stmg %r6,%r14,__SF_GPRS(%r15) # save kernel registers
247 stg %r2,__SF_SIE_CONTROL(%r15) # save control block pointer
248 stg %r3,__SF_SIE_SAVEAREA(%r15) # save guest register save area
249 xc __SF_SIE_REASON(8,%r15),__SF_SIE_REASON(%r15) # reason code = 0
250 mvc __SF_SIE_FLAGS(8,%r15),__TI_flags(%r12) # copy thread flags
251 lmg %r0,%r13,0(%r3) # load guest gprs 0-13
252 lg %r14,__LC_GMAP # get gmap pointer
255 lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce
257 lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer
258 oi __SIE_PROG0C+3(%r14),1 # we are going into SIE now
259 tm __SIE_PROG20+3(%r14),3 # last exit...
261 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
262 jo .Lsie_skip # exit if fp/vx regs changed
263 BPEXIT __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
267 BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
269 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
270 lctlg %c1,%c1,__LC_KERNEL_ASCE # load primary asce
272 # some program checks are suppressing. C code (e.g. do_protection_exception)
273 # will rewind the PSW by the ILC, which is often 4 bytes in case of SIE. There
274 # are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable.
275 # Other instructions between sie64a and .Lsie_done should not cause program
276 # interrupts. So lets use 3 nops as a landing pad for all possible rewinds.
285 lg %r14,__SF_SIE_SAVEAREA(%r15) # load guest register save area
286 stmg %r0,%r13,0(%r14) # save guest gprs 0-13
287 xgr %r0,%r0 # clear guest registers to
288 xgr %r1,%r1 # prevent speculative use
292 lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers
293 lg %r2,__SF_SIE_REASON(%r15) # return exit reason code
297 stg %r14,__SF_SIE_REASON(%r15) # set exit reason code
300 EX_TABLE(.Lrewind_pad6,.Lsie_fault)
301 EX_TABLE(.Lrewind_pad4,.Lsie_fault)
302 EX_TABLE(.Lrewind_pad2,.Lsie_fault)
303 EX_TABLE(sie_exit,.Lsie_fault)
305 EXPORT_SYMBOL(sie64a)
306 EXPORT_SYMBOL(sie_exit)
310 * SVC interrupt handler routine. System calls are synchronous events and
311 * are entered with interrupts disabled.
315 stpt __LC_SYS_ENTER_TIMER
316 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
320 STBEAR __LC_LAST_BREAK
321 lctlg %c1,%c1,__LC_KERNEL_ASCE
323 lg %r15,__LC_KERNEL_STACK
324 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
325 stmg %r0,%r7,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
326 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
327 # clear user controlled register to prevent speculative use
338 la %r2,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs
339 mvc __PT_R8(64,%r2),__LC_SAVE_AREA_SYNC
342 brasl %r14,__do_syscall
343 lctlg %c1,%c1,__LC_USER_ASCE
344 mvc __LC_RETURN_PSW(16),STACK_FRAME_OVERHEAD+__PT_PSW(%r15)
345 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
346 LBEAR STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15)
347 lmg %r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
349 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE
353 # a new process exits the kernel with ret_from_fork
357 brasl %r14,__ret_from_fork
358 lctlg %c1,%c1,__LC_USER_ASCE
359 mvc __LC_RETURN_PSW(16),STACK_FRAME_OVERHEAD+__PT_PSW(%r15)
360 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
361 LBEAR STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15)
362 lmg %r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
364 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE
365 ENDPROC(ret_from_fork)
368 * Program check handler routine
371 ENTRY(pgm_check_handler)
372 stpt __LC_SYS_ENTER_TIMER
374 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
377 lmg %r8,%r9,__LC_PGM_OLD_PSW
378 tmhh %r8,0x0001 # coming from user space?
380 lctlg %c1,%c1,__LC_KERNEL_ASCE
381 j 3f # -> fault in user space
383 #if IS_ENABLED(CONFIG_KVM)
384 # cleanup critical section for program checks in sie64a
385 OUTSIDE %r9,.Lsie_gmap,.Lsie_done,1f
387 lghi %r10,_PIF_GUEST_FAULT
389 1: tmhh %r8,0x4000 # PER bit set in old PSW ?
390 jnz 2f # -> enabled, can't be a double fault
391 tm __LC_PGM_ILC+3,0x80 # check for per exception
392 jnz .Lpgm_svcper # -> single stepped svc
393 2: CHECK_STACK __LC_SAVE_AREA_SYNC
394 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
395 # CHECK_VMAP_STACK branches to stack_overflow or 4f
396 CHECK_VMAP_STACK __LC_SAVE_AREA_SYNC,4f
397 3: BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
398 lg %r15,__LC_KERNEL_STACK
399 4: la %r11,STACK_FRAME_OVERHEAD(%r15)
400 stg %r10,__PT_FLAGS(%r11)
401 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
402 stmg %r0,%r7,__PT_R0(%r11)
403 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
404 mvc __PT_LAST_BREAK(8,%r11),__LC_PGM_LAST_BREAK
405 stmg %r8,%r9,__PT_PSW(%r11)
407 # clear user controlled registers to prevent speculative use
416 brasl %r14,__do_pgm_check
417 tmhh %r8,0x0001 # returning to user space?
418 jno .Lpgm_exit_kernel
419 lctlg %c1,%c1,__LC_USER_ASCE
420 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
423 mvc __LC_RETURN_PSW(16),STACK_FRAME_OVERHEAD+__PT_PSW(%r15)
424 LBEAR STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15)
425 lmg %r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
426 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE
429 # single stepped system call
432 mvc __LC_RETURN_PSW(8),__LC_SVC_NEW_PSW
434 stg %r14,__LC_RETURN_PSW+8
436 LBEAR __LC_PGM_LAST_BREAK
437 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE # branch to .Lsysc_per
438 ENDPROC(pgm_check_handler)
441 * Interrupt handler macro used for external and IO interrupts.
443 .macro INT_HANDLER name,lc_old_psw,handler
446 stpt __LC_SYS_ENTER_TIMER
447 STBEAR __LC_LAST_BREAK
449 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
451 lmg %r8,%r9,\lc_old_psw
452 tmhh %r8,0x0001 # interrupting from user ?
454 #if IS_ENABLED(CONFIG_KVM)
455 OUTSIDE %r9,.Lsie_gmap,.Lsie_done,0f
456 BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
459 0: CHECK_STACK __LC_SAVE_AREA_ASYNC
460 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
462 1: BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
463 lctlg %c1,%c1,__LC_KERNEL_ASCE
464 lg %r15,__LC_KERNEL_STACK
465 2: xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
466 la %r11,STACK_FRAME_OVERHEAD(%r15)
467 stmg %r0,%r7,__PT_R0(%r11)
468 # clear user controlled registers to prevent speculative use
477 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
478 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
480 stmg %r8,%r9,__PT_PSW(%r11)
481 tm %r8,0x0001 # coming from user space?
483 lctlg %c1,%c1,__LC_KERNEL_ASCE
484 1: lgr %r2,%r11 # pass pointer to pt_regs
486 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
487 tmhh %r8,0x0001 # returning to user ?
489 lctlg %c1,%c1,__LC_USER_ASCE
490 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
492 2: LBEAR __PT_LAST_BREAK(%r11)
493 lmg %r0,%r15,__PT_R0(%r11)
494 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE
498 INT_HANDLER ext_int_handler,__LC_EXT_OLD_PSW,do_ext_irq
499 INT_HANDLER io_int_handler,__LC_IO_OLD_PSW,do_io_irq
505 stg %r14,(__SF_GPRS+8*8)(%r15)
506 stg %r3,__SF_EMPTY(%r15)
507 larl %r1,psw_idle_exit
508 stg %r1,__SF_EMPTY+8(%r15)
509 larl %r1,smp_cpu_mtid
513 .insn rsy,0xeb0000000017,%r1,5,__MT_CYCLES_ENTER(%r2)
515 oi __LC_CPU_FLAGS+7,_CIF_ENABLED_WAIT
517 STCK __CLOCK_IDLE_ENTER(%r2)
518 stpt __TIMER_IDLE_ENTER(%r2)
519 lpswe __SF_EMPTY(%r15)
526 * Machine check handler routines
528 ENTRY(mcck_int_handler)
531 la %r1,4095 # validate r1
532 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # validate cpu timer
533 LBEAR __LC_LAST_BREAK_SAVE_AREA-4095(%r1) # validate bear
534 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# validate gprs
536 lmg %r8,%r9,__LC_MCK_OLD_PSW
537 TSTMSK __LC_MCCK_CODE,MCCK_CODE_SYSTEM_DAMAGE
538 jo .Lmcck_panic # yes -> rest of mcck code invalid
539 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CR_VALID
540 jno .Lmcck_panic # control registers invalid -> panic
542 lctlg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r14) # validate ctl regs
544 lghi %r14,__LC_CPU_TIMER_SAVE_AREA
545 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
546 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID
548 la %r14,__LC_SYS_ENTER_TIMER
549 clc 0(8,%r14),__LC_EXIT_TIMER
551 la %r14,__LC_EXIT_TIMER
552 1: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
554 la %r14,__LC_LAST_UPDATE_TIMER
556 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
557 3: TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_MWP_VALID
559 tmhh %r8,0x0001 # interrupting from user ?
561 TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_IA_VALID
563 #if IS_ENABLED(CONFIG_KVM)
564 OUTSIDE %r9,.Lsie_gmap,.Lsie_done,6f
565 OUTSIDE %r9,.Lsie_entry,.Lsie_skip,4f
566 oi __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST
568 4: CHKSTG .Lmcck_panic
569 5: larl %r14,.Lstosm_tmp
570 stosm 0(%r14),0x04 # turn dat on, keep irqs off
571 BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
575 6: CHKSTG .Lmcck_panic
576 larl %r14,.Lstosm_tmp
577 stosm 0(%r14),0x04 # turn dat on, keep irqs off
578 tmhh %r8,0x0001 # interrupting from user ?
580 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
582 lg %r15,__LC_MCCK_STACK
583 la %r11,STACK_FRAME_OVERHEAD(%r15)
584 stctg %c1,%c1,__PT_CR1(%r11)
585 lctlg %c1,%c1,__LC_KERNEL_ASCE
586 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
587 lghi %r14,__LC_GPREGS_SAVE_AREA+64
588 stmg %r0,%r7,__PT_R0(%r11)
589 # clear user controlled registers to prevent speculative use
598 mvc __PT_R8(64,%r11),0(%r14)
599 stmg %r8,%r9,__PT_PSW(%r11)
600 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
601 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
602 lgr %r2,%r11 # pass pointer to pt_regs
603 brasl %r14,s390_do_machine_check
606 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
607 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
608 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
609 la %r11,STACK_FRAME_OVERHEAD(%r1)
611 brasl %r14,s390_handle_mcck
613 lctlg %c1,%c1,__PT_CR1(%r11)
614 lmg %r0,%r10,__PT_R0(%r11)
615 mvc __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
616 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
618 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
620 0: ALTERNATIVE "", __stringify(lghi %r12,__LC_LAST_BREAK_SAVE_AREA),193
622 lmg %r11,%r15,__PT_R11(%r11)
623 LPSWEY __LC_RETURN_MCCK_PSW,__LC_RETURN_MCCK_LPSWE
627 * Iterate over all possible CPU addresses in the range 0..0xffff
628 * and stop each CPU using signal processor. Use compare and swap
629 * to allow just one CPU-stopper and prevent concurrent CPUs from
630 * stopping each other while leaving the others running.
635 cs %r5,%r6,0(%r7) # single CPU-stopper only
638 stap 0(%r7) # this CPU address
642 sll %r0,16 # CPU counter
643 lhi %r3,0 # next CPU address
646 1: sigp %r1,%r3,SIGP_STOP # stop next CPU
650 3: sigp %r1,%r4,SIGP_STOP # stop this CPU
653 ENDPROC(mcck_int_handler)
655 ENTRY(restart_int_handler)
656 ALTERNATIVE "", ".insn s,0xb2800000,_LPP_OFFSET", 40
657 stg %r15,__LC_SAVE_AREA_RESTART
658 TSTMSK __LC_RESTART_FLAGS,RESTART_FLAG_CTLREGS,4
661 lctlg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r15)
662 0: larl %r15,.Lstosm_tmp
663 stosm 0(%r15),0x04 # turn dat on, keep irqs off
664 lg %r15,__LC_RESTART_STACK
665 xc STACK_FRAME_OVERHEAD(__PT_SIZE,%r15),STACK_FRAME_OVERHEAD(%r15)
666 stmg %r0,%r14,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
667 mvc STACK_FRAME_OVERHEAD+__PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
668 mvc STACK_FRAME_OVERHEAD+__PT_PSW(16,%r15),__LC_RST_OLD_PSW
669 xc 0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
670 lg %r1,__LC_RESTART_FN # load fn, parm & source cpu
671 lg %r2,__LC_RESTART_DATA
672 lgf %r3,__LC_RESTART_SOURCE
673 ltgr %r3,%r3 # test source cpu address
674 jm 1f # negative -> skip source stop
675 0: sigp %r4,%r3,SIGP_SENSE # sigp sense to source cpu
676 brc 10,0b # wait for status stored
677 1: basr %r14,%r1 # call function
678 stap __SF_EMPTY(%r15) # store cpu address
679 llgh %r3,__SF_EMPTY(%r15)
680 2: sigp %r4,%r3,SIGP_STOP # sigp stop to current cpu
683 ENDPROC(restart_int_handler)
685 .section .kprobes.text, "ax"
687 #if defined(CONFIG_CHECK_STACK) || defined(CONFIG_VMAP_STACK)
689 * The synchronous or the asynchronous stack overflowed. We are dead.
690 * No need to properly save the registers, we are going to panic anyway.
691 * Setup a pt_regs so that show_trace can provide a good call trace.
693 ENTRY(stack_overflow)
694 lg %r15,__LC_NODAT_STACK # change to panic stack
695 la %r11,STACK_FRAME_OVERHEAD(%r15)
696 stmg %r0,%r7,__PT_R0(%r11)
697 stmg %r8,%r9,__PT_PSW(%r11)
698 mvc __PT_R8(64,%r11),0(%r14)
699 stg %r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
700 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
701 lgr %r2,%r11 # pass pointer to pt_regs
702 jg kernel_stack_overflow
703 ENDPROC(stack_overflow)
711 .section .rodata, "a"
712 #define SYSCALL(esame,emu) .quad __s390x_ ## esame
713 .globl sys_call_table
715 #include "asm/syscall_table.h"
720 #define SYSCALL(esame,emu) .quad __s390_ ## emu
721 .globl sys_call_table_emu
723 #include "asm/syscall_table.h"