1 /* SPDX-License-Identifier: GPL-2.0 */
3 * S390 low-level entry points.
5 * Copyright IBM Corp. 1999, 2012
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/alternative-asm.h>
15 #include <asm/processor.h>
16 #include <asm/cache.h>
17 #include <asm/ctl_reg.h>
18 #include <asm/dwarf.h>
19 #include <asm/errno.h>
20 #include <asm/ptrace.h>
21 #include <asm/thread_info.h>
22 #include <asm/asm-offsets.h>
23 #include <asm/unistd.h>
27 #include <asm/vx-insn.h>
28 #include <asm/setup.h>
30 #include <asm/export.h>
31 #include <asm/nospec-insn.h>
34 __PT_R1 = __PT_GPRS + 8
35 __PT_R2 = __PT_GPRS + 16
36 __PT_R3 = __PT_GPRS + 24
37 __PT_R4 = __PT_GPRS + 32
38 __PT_R5 = __PT_GPRS + 40
39 __PT_R6 = __PT_GPRS + 48
40 __PT_R7 = __PT_GPRS + 56
41 __PT_R8 = __PT_GPRS + 64
42 __PT_R9 = __PT_GPRS + 72
43 __PT_R10 = __PT_GPRS + 80
44 __PT_R11 = __PT_GPRS + 88
45 __PT_R12 = __PT_GPRS + 96
46 __PT_R13 = __PT_GPRS + 104
47 __PT_R14 = __PT_GPRS + 112
48 __PT_R15 = __PT_GPRS + 120
50 STACK_SHIFT = PAGE_SHIFT + THREAD_SIZE_ORDER
51 STACK_SIZE = 1 << STACK_SHIFT
52 STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
54 _TIF_WORK = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
55 _TIF_UPROBE | _TIF_GUARDED_STORAGE | _TIF_PATCH_PENDING)
56 _TIF_TRACE = (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
57 _TIF_SYSCALL_TRACEPOINT)
58 _CIF_WORK = (_CIF_MCCK_PENDING | _CIF_ASCE_PRIMARY | \
59 _CIF_ASCE_SECONDARY | _CIF_FPU)
60 _PIF_WORK = (_PIF_PER_TRAP | _PIF_SYSCALL_RESTART)
62 _LPP_OFFSET = __LC_LPP
64 #define BASED(name) name-cleanup_critical(%r13)
67 #ifdef CONFIG_TRACE_IRQFLAGS
69 brasl %r14,trace_hardirqs_on_caller
74 #ifdef CONFIG_TRACE_IRQFLAGS
76 brasl %r14,trace_hardirqs_off_caller
80 .macro LOCKDEP_SYS_EXIT
82 tm __PT_PSW+1(%r11),0x01 # returning to user ?
84 brasl %r14,lockdep_sys_exit
88 .macro CHECK_STACK stacksize,savearea
89 #ifdef CONFIG_CHECK_STACK
90 tml %r15,\stacksize - CONFIG_STACK_GUARD
96 .macro SWITCH_ASYNC savearea,timer
97 tmhh %r8,0x0001 # interrupting from user ?
100 slg %r14,BASED(.Lcritical_start)
101 clg %r14,BASED(.Lcritical_length)
103 lghi %r11,\savearea # inside critical section, do cleanup
104 brasl %r14,cleanup_critical
105 tmhh %r8,0x0001 # retest problem state after cleanup
107 0: lg %r14,__LC_ASYNC_STACK # are we already on the async stack?
109 srag %r14,%r14,STACK_SHIFT
111 CHECK_STACK 1<<STACK_SHIFT,\savearea
112 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
114 1: UPDATE_VTIME %r14,%r15,\timer
115 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
116 2: lg %r15,__LC_ASYNC_STACK # load async stack
117 3: la %r11,STACK_FRAME_OVERHEAD(%r15)
120 .macro UPDATE_VTIME w1,w2,enter_timer
121 lg \w1,__LC_EXIT_TIMER
122 lg \w2,__LC_LAST_UPDATE_TIMER
124 slg \w2,__LC_EXIT_TIMER
125 alg \w1,__LC_USER_TIMER
126 alg \w2,__LC_SYSTEM_TIMER
127 stg \w1,__LC_USER_TIMER
128 stg \w2,__LC_SYSTEM_TIMER
129 mvc __LC_LAST_UPDATE_TIMER(8),\enter_timer
133 stg %r8,__LC_RETURN_PSW
134 ni __LC_RETURN_PSW,0xbf
139 #ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES
140 .insn s,0xb27c0000,\savearea # store clock fast
142 .insn s,0xb2050000,\savearea # store clock
147 * The TSTMSK macro generates a test-under-mask instruction by
148 * calculating the memory offset for the specified mask value.
149 * Mask value can be any constant. The macro shifts the mask
150 * value to calculate the memory offset for the test-under-mask
153 .macro TSTMSK addr, mask, size=8, bytepos=0
154 .if (\bytepos < \size) && (\mask >> 8)
156 .error "Mask exceeds byte boundary"
158 TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)"
162 .error "Mask must not be zero"
164 off = \size - \bytepos - 1
169 ALTERNATIVE "", ".long 0xb2e8c000", 82
173 ALTERNATIVE "", ".long 0xb2e8d000", 82
176 .macro BPENTER tif_ptr,tif_mask
177 ALTERNATIVE "TSTMSK \tif_ptr,\tif_mask; jz .+8; .long 0xb2e8d000", \
181 .macro BPEXIT tif_ptr,tif_mask
182 TSTMSK \tif_ptr,\tif_mask
183 ALTERNATIVE "jz .+8; .long 0xb2e8c000", \
184 "jnz .+8; .long 0xb2e8d000", 82
189 GEN_BR_THUNK %r14,%r11
191 .section .kprobes.text, "ax"
194 * This nop exists only in order to avoid that __switch_to starts at
195 * the beginning of the kprobes text section. In that case we would
196 * have several symbols at the same address. E.g. objdump would take
197 * an arbitrary symbol name when disassembling this code.
198 * With the added nop in between the __switch_to symbol is unique
209 * Scheduler resume function, called by switch_to
210 * gpr2 = (task_struct *) prev
211 * gpr3 = (task_struct *) next
216 stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task
217 lghi %r4,__TASK_stack
218 lghi %r1,__TASK_thread
219 lg %r5,0(%r4,%r3) # start of kernel stack of next
220 stg %r15,__THREAD_ksp(%r1,%r2) # store kernel stack of prev
222 aghi %r15,STACK_INIT # end of kernel stack of next
223 stg %r3,__LC_CURRENT # store task struct of next
224 stg %r15,__LC_KERNEL_STACK # store end of kernel stack
225 lg %r15,__THREAD_ksp(%r1,%r3) # load kernel stack of next
227 mvc __LC_CURRENT_PID(4,%r0),0(%r3) # store pid of next
228 lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
229 ALTERNATIVE "", ".insn s,0xb2800000,_LPP_OFFSET", 40
234 #if IS_ENABLED(CONFIG_KVM)
236 * sie64a calling convention:
237 * %r2 pointer to sie control block
238 * %r3 guest register save area
241 stmg %r6,%r14,__SF_GPRS(%r15) # save kernel registers
243 stg %r2,__SF_SIE_CONTROL(%r15) # save control block pointer
244 stg %r3,__SF_SIE_SAVEAREA(%r15) # save guest register save area
245 xc __SF_SIE_REASON(8,%r15),__SF_SIE_REASON(%r15) # reason code = 0
246 mvc __SF_SIE_FLAGS(8,%r15),__TI_flags(%r12) # copy thread flags
247 TSTMSK __LC_CPU_FLAGS,_CIF_FPU # load guest fp/vx registers ?
248 jno .Lsie_load_guest_gprs
249 brasl %r14,load_fpu_regs # load guest fp/vx regs
250 .Lsie_load_guest_gprs:
251 lmg %r0,%r13,0(%r3) # load guest gprs 0-13
252 lg %r14,__LC_GMAP # get gmap pointer
255 lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce
257 lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer
258 oi __SIE_PROG0C+3(%r14),1 # we are going into SIE now
259 tm __SIE_PROG20+3(%r14),3 # last exit...
261 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
262 jo .Lsie_skip # exit if fp/vx regs changed
263 BPEXIT __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
268 BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
270 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
271 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
273 # some program checks are suppressing. C code (e.g. do_protection_exception)
274 # will rewind the PSW by the ILC, which is often 4 bytes in case of SIE. There
275 # are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable.
276 # Other instructions between sie64a and .Lsie_done should not cause program
277 # interrupts. So lets use 3 nops as a landing pad for all possible rewinds.
278 # See also .Lcleanup_sie
287 lg %r14,__SF_SIE_SAVEAREA(%r15) # load guest register save area
288 stmg %r0,%r13,0(%r14) # save guest gprs 0-13
289 xgr %r0,%r0 # clear guest registers to
290 xgr %r1,%r1 # prevent speculative use
295 lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers
296 lg %r2,__SF_SIE_REASON(%r15) # return exit reason code
300 stg %r14,__SF_SIE_REASON(%r15) # set exit reason code
303 EX_TABLE(.Lrewind_pad6,.Lsie_fault)
304 EX_TABLE(.Lrewind_pad4,.Lsie_fault)
305 EX_TABLE(.Lrewind_pad2,.Lsie_fault)
306 EX_TABLE(sie_exit,.Lsie_fault)
307 EXPORT_SYMBOL(sie64a)
308 EXPORT_SYMBOL(sie_exit)
312 * SVC interrupt handler routine. System calls are synchronous events and
313 * are executed with interrupts enabled.
317 stpt __LC_SYNC_ENTER_TIMER
319 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
322 lghi %r13,__TASK_thread
323 lghi %r14,_PIF_SYSCALL
325 lg %r15,__LC_KERNEL_STACK
326 la %r11,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs
328 UPDATE_VTIME %r8,%r9,__LC_SYNC_ENTER_TIMER
329 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
330 stmg %r0,%r7,__PT_R0(%r11)
331 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
332 mvc __PT_PSW(16,%r11),__LC_SVC_OLD_PSW
333 mvc __PT_INT_CODE(4,%r11),__LC_SVC_ILC
334 stg %r14,__PT_FLAGS(%r11)
336 # clear user controlled register to prevent speculative use
338 # load address of system call table
339 lg %r10,__THREAD_sysc_table(%r13,%r12)
340 llgh %r8,__PT_INT_CODE+2(%r11)
341 slag %r8,%r8,2 # shift and test for svc 0
343 # svc 0: system call number in %r1
344 llgfr %r1,%r1 # clear high word in r1
347 sth %r1,__PT_INT_CODE+2(%r11)
350 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
351 stg %r2,__PT_ORIG_GPR2(%r11)
352 stg %r7,STACK_FRAME_OVERHEAD(%r15)
353 lgf %r9,0(%r8,%r10) # get system call add.
354 TSTMSK __TI_flags(%r12),_TIF_TRACE
356 BASR_EX %r14,%r9 # call sys_xxxx
357 stg %r2,__PT_R2(%r11) # store return value
362 TSTMSK __PT_FLAGS(%r11),_PIF_WORK
364 TSTMSK __TI_flags(%r12),_TIF_WORK
365 jnz .Lsysc_work # check for work
366 TSTMSK __LC_CPU_FLAGS,_CIF_WORK
368 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
370 lg %r14,__LC_VDSO_PER_CPU
371 lmg %r0,%r10,__PT_R0(%r11)
372 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
375 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
376 lmg %r11,%r15,__PT_R11(%r11)
377 lpswe __LC_RETURN_PSW
381 # One of the work bits is on. Find out which one.
384 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
385 jo .Lsysc_mcck_pending
386 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
388 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL_RESTART
389 jo .Lsysc_syscall_restart
390 #ifdef CONFIG_UPROBES
391 TSTMSK __TI_flags(%r12),_TIF_UPROBE
392 jo .Lsysc_uprobe_notify
394 TSTMSK __TI_flags(%r12),_TIF_GUARDED_STORAGE
395 jo .Lsysc_guarded_storage
396 TSTMSK __PT_FLAGS(%r11),_PIF_PER_TRAP
398 #ifdef CONFIG_LIVEPATCH
399 TSTMSK __TI_flags(%r12),_TIF_PATCH_PENDING
400 jo .Lsysc_patch_pending # handle live patching just before
401 # signals and possible syscall restart
403 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL_RESTART
404 jo .Lsysc_syscall_restart
405 TSTMSK __TI_flags(%r12),_TIF_SIGPENDING
407 TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME
408 jo .Lsysc_notify_resume
409 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
411 TSTMSK __LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
413 j .Lsysc_return # beware of critical section cleanup
416 # _TIF_NEED_RESCHED is set, call schedule
419 larl %r14,.Lsysc_return
423 # _CIF_MCCK_PENDING is set, call handler
426 larl %r14,.Lsysc_return
427 jg s390_handle_mcck # TIF bit will be cleared by handler
430 # _CIF_ASCE_PRIMARY and/or _CIF_ASCE_SECONDARY set, load user space asce
433 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_SECONDARY
434 lctlg %c7,%c7,__LC_VDSO_ASCE # load secondary asce
435 TSTMSK __LC_CPU_FLAGS,_CIF_ASCE_PRIMARY
437 #ifndef CONFIG_HAVE_MARCH_Z10_FEATURES
438 tm __LC_STFLE_FAC_LIST+3,0x10 # has MVCOS ?
439 jnz .Lsysc_set_fs_fixup
440 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
441 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
445 larl %r14,.Lsysc_return
449 # CIF_FPU is set, restore floating-point controls and floating-point registers.
452 larl %r14,.Lsysc_return
456 # _TIF_SIGPENDING is set, call do_signal
459 lgr %r2,%r11 # pass pointer to pt_regs
461 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL
464 lghi %r13,__TASK_thread
465 lmg %r2,%r7,__PT_R2(%r11) # load svc arguments
466 lghi %r1,0 # svc 0 returns -ENOSYS
470 # _TIF_NOTIFY_RESUME is set, call do_notify_resume
472 .Lsysc_notify_resume:
473 lgr %r2,%r11 # pass pointer to pt_regs
474 larl %r14,.Lsysc_return
478 # _TIF_UPROBE is set, call uprobe_notify_resume
480 #ifdef CONFIG_UPROBES
481 .Lsysc_uprobe_notify:
482 lgr %r2,%r11 # pass pointer to pt_regs
483 larl %r14,.Lsysc_return
484 jg uprobe_notify_resume
488 # _TIF_GUARDED_STORAGE is set, call guarded_storage_load
490 .Lsysc_guarded_storage:
491 lgr %r2,%r11 # pass pointer to pt_regs
492 larl %r14,.Lsysc_return
495 # _TIF_PATCH_PENDING is set, call klp_update_patch_state
497 #ifdef CONFIG_LIVEPATCH
498 .Lsysc_patch_pending:
499 lg %r2,__LC_CURRENT # pass pointer to task struct
500 larl %r14,.Lsysc_return
501 jg klp_update_patch_state
505 # _PIF_PER_TRAP is set, call do_per_trap
508 ni __PT_FLAGS+7(%r11),255-_PIF_PER_TRAP
509 lgr %r2,%r11 # pass pointer to pt_regs
510 larl %r14,.Lsysc_return
514 # _PIF_SYSCALL_RESTART is set, repeat the current system call
516 .Lsysc_syscall_restart:
517 ni __PT_FLAGS+7(%r11),255-_PIF_SYSCALL_RESTART
518 lmg %r1,%r7,__PT_R1(%r11) # load svc arguments
519 lg %r2,__PT_ORIG_GPR2(%r11)
523 # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
524 # and after the system call
527 lgr %r2,%r11 # pass pointer to pt_regs
529 llgh %r0,__PT_INT_CODE+2(%r11)
530 stg %r0,__PT_R2(%r11)
531 brasl %r14,do_syscall_trace_enter
538 lmg %r3,%r7,__PT_R3(%r11)
539 stg %r7,STACK_FRAME_OVERHEAD(%r15)
540 lg %r2,__PT_ORIG_GPR2(%r11)
541 BASR_EX %r14,%r9 # call sys_xxx
542 stg %r2,__PT_R2(%r11) # store return value
544 TSTMSK __TI_flags(%r12),_TIF_TRACE
546 lgr %r2,%r11 # pass pointer to pt_regs
547 larl %r14,.Lsysc_return
548 jg do_syscall_trace_exit
551 # a new process exits the kernel with ret_from_fork
554 la %r11,STACK_FRAME_OVERHEAD(%r15)
556 brasl %r14,schedule_tail
558 ssm __LC_SVC_NEW_PSW # reenable interrupts
559 tm __PT_PSW+1(%r11),0x01 # forking a kernel thread ?
561 # it's a kernel thread
562 lmg %r9,%r10,__PT_R9(%r11) # load gprs
563 ENTRY(kernel_thread_starter)
569 * Program check handler routine
572 ENTRY(pgm_check_handler)
573 stpt __LC_SYNC_ENTER_TIMER
575 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
576 lg %r10,__LC_LAST_BREAK
579 larl %r13,cleanup_critical
580 lmg %r8,%r9,__LC_PGM_OLD_PSW
581 tmhh %r8,0x0001 # test problem state bit
582 jnz 2f # -> fault in user space
583 #if IS_ENABLED(CONFIG_KVM)
584 # cleanup critical section for program checks in sie64a
586 slg %r14,BASED(.Lsie_critical_start)
587 clg %r14,BASED(.Lsie_critical_length)
589 lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer
590 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
591 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
592 larl %r9,sie_exit # skip forward to sie_exit
593 lghi %r11,_PIF_GUEST_FAULT
595 0: tmhh %r8,0x4000 # PER bit set in old PSW ?
596 jnz 1f # -> enabled, can't be a double fault
597 tm __LC_PGM_ILC+3,0x80 # check for per exception
598 jnz .Lpgm_svcper # -> single stepped svc
599 1: CHECK_STACK STACK_SIZE,__LC_SAVE_AREA_SYNC
600 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
602 2: UPDATE_VTIME %r14,%r15,__LC_SYNC_ENTER_TIMER
603 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
604 lg %r15,__LC_KERNEL_STACK
606 aghi %r14,__TASK_thread # pointer to thread_struct
607 lghi %r13,__LC_PGM_TDB
608 tm __LC_PGM_ILC+2,0x02 # check for transaction abort
610 mvc __THREAD_trap_tdb(256,%r14),0(%r13)
611 3: stg %r10,__THREAD_last_break(%r14)
613 la %r11,STACK_FRAME_OVERHEAD(%r15)
614 stmg %r0,%r7,__PT_R0(%r11)
615 # clear user controlled registers to prevent speculative use
624 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
625 stmg %r8,%r9,__PT_PSW(%r11)
626 mvc __PT_INT_CODE(4,%r11),__LC_PGM_ILC
627 mvc __PT_INT_PARM_LONG(8,%r11),__LC_TRANS_EXC_CODE
628 stg %r13,__PT_FLAGS(%r11)
629 stg %r10,__PT_ARGS(%r11)
630 tm __LC_PGM_ILC+3,0x80 # check for per exception
632 tmhh %r8,0x0001 # kernel per event ?
634 oi __PT_FLAGS+7(%r11),_PIF_PER_TRAP
635 mvc __THREAD_per_address(8,%r14),__LC_PER_ADDRESS
636 mvc __THREAD_per_cause(2,%r14),__LC_PER_CODE
637 mvc __THREAD_per_paid(1,%r14),__LC_PER_ACCESS_ID
639 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
640 larl %r1,pgm_check_table
641 llgh %r10,__PT_INT_CODE+2(%r11)
645 lgf %r9,0(%r10,%r1) # load address of handler routine
646 lgr %r2,%r11 # pass pointer to pt_regs
647 BASR_EX %r14,%r9 # branch to interrupt-handler
650 tm __PT_PSW+1(%r11),0x01 # returning to user ?
652 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL
657 # PER event in supervisor state, must be kprobes
661 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
662 lgr %r2,%r11 # pass pointer to pt_regs
663 brasl %r14,do_per_trap
667 # single stepped system call
670 mvc __LC_RETURN_PSW(8),__LC_SVC_NEW_PSW
671 lghi %r13,__TASK_thread
673 stg %r14,__LC_RETURN_PSW+8
674 lghi %r14,_PIF_SYSCALL | _PIF_PER_TRAP
675 lpswe __LC_RETURN_PSW # branch to .Lsysc_per and enable irqs
678 * IO interrupt handler routine
680 ENTRY(io_int_handler)
682 stpt __LC_ASYNC_ENTER_TIMER
684 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
686 larl %r13,cleanup_critical
687 lmg %r8,%r9,__LC_IO_OLD_PSW
688 SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
689 stmg %r0,%r7,__PT_R0(%r11)
690 # clear user controlled registers to prevent speculative use
700 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
701 stmg %r8,%r9,__PT_PSW(%r11)
702 mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
703 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
704 TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ
707 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
709 lgr %r2,%r11 # pass pointer to pt_regs
710 lghi %r3,IO_INTERRUPT
711 tm __PT_INT_CODE+8(%r11),0x80 # adapter interrupt ?
713 lghi %r3,THIN_INTERRUPT
716 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPAR
720 mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
726 TSTMSK __TI_flags(%r12),_TIF_WORK
727 jnz .Lio_work # there is work to do (signals etc.)
728 TSTMSK __LC_CPU_FLAGS,_CIF_WORK
731 lg %r14,__LC_VDSO_PER_CPU
732 lmg %r0,%r10,__PT_R0(%r11)
733 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
734 tm __PT_PSW+1(%r11),0x01 # returning to user ?
736 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
739 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
741 lmg %r11,%r15,__PT_R11(%r11)
742 lpswe __LC_RETURN_PSW
746 # There is work todo, find out in which context we have been interrupted:
747 # 1) if we return to user space we can do all _TIF_WORK work
748 # 2) if we return to kernel code and kvm is enabled check if we need to
749 # modify the psw to leave SIE
750 # 3) if we return to kernel code and preemptive scheduling is enabled check
751 # the preemption counter and if it is zero call preempt_schedule_irq
752 # Before any work can be done, a switch to the kernel stack is required.
755 tm __PT_PSW+1(%r11),0x01 # returning to user ?
756 jo .Lio_work_user # yes -> do resched & signal
757 #ifdef CONFIG_PREEMPT
758 # check for preemptive scheduling
759 icm %r0,15,__LC_PREEMPT_COUNT
760 jnz .Lio_restore # preemption is disabled
761 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
763 # switch to kernel stack
764 lg %r1,__PT_R15(%r11)
765 aghi %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
766 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
767 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
768 la %r11,STACK_FRAME_OVERHEAD(%r1)
770 # TRACE_IRQS_ON already done at .Lio_return, call
771 # TRACE_IRQS_OFF to keep things symmetrical
773 brasl %r14,preempt_schedule_irq
780 # Need to do work before returning to userspace, switch to kernel stack
783 lg %r1,__LC_KERNEL_STACK
784 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
785 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
786 la %r11,STACK_FRAME_OVERHEAD(%r1)
790 # One of the work bits is on. Find out which one.
793 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
795 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
797 #ifdef CONFIG_LIVEPATCH
798 TSTMSK __TI_flags(%r12),_TIF_PATCH_PENDING
799 jo .Lio_patch_pending
801 TSTMSK __TI_flags(%r12),_TIF_SIGPENDING
803 TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME
804 jo .Lio_notify_resume
805 TSTMSK __TI_flags(%r12),_TIF_GUARDED_STORAGE
806 jo .Lio_guarded_storage
807 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
809 TSTMSK __LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
811 j .Lio_return # beware of critical section cleanup
814 # _CIF_MCCK_PENDING is set, call handler
817 # TRACE_IRQS_ON already done at .Lio_return
818 brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler
823 # _CIF_ASCE_PRIMARY and/or CIF_ASCE_SECONDARY set, load user space asce
826 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_SECONDARY
827 lctlg %c7,%c7,__LC_VDSO_ASCE # load secondary asce
828 TSTMSK __LC_CPU_FLAGS,_CIF_ASCE_PRIMARY
830 #ifndef CONFIG_HAVE_MARCH_Z10_FEATURES
831 tm __LC_STFLE_FAC_LIST+3,0x10 # has MVCOS ?
832 jnz .Lio_set_fs_fixup
833 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
834 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
838 larl %r14,.Lio_return
842 # CIF_FPU is set, restore floating-point controls and floating-point registers.
845 larl %r14,.Lio_return
849 # _TIF_GUARDED_STORAGE is set, call guarded_storage_load
851 .Lio_guarded_storage:
852 # TRACE_IRQS_ON already done at .Lio_return
853 ssm __LC_SVC_NEW_PSW # reenable interrupts
854 lgr %r2,%r11 # pass pointer to pt_regs
855 brasl %r14,gs_load_bc_cb
856 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
861 # _TIF_NEED_RESCHED is set, call schedule
864 # TRACE_IRQS_ON already done at .Lio_return
865 ssm __LC_SVC_NEW_PSW # reenable interrupts
866 brasl %r14,schedule # call scheduler
867 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
872 # _TIF_PATCH_PENDING is set, call klp_update_patch_state
874 #ifdef CONFIG_LIVEPATCH
876 lg %r2,__LC_CURRENT # pass pointer to task struct
877 larl %r14,.Lio_return
878 jg klp_update_patch_state
882 # _TIF_SIGPENDING or is set, call do_signal
885 # TRACE_IRQS_ON already done at .Lio_return
886 ssm __LC_SVC_NEW_PSW # reenable interrupts
887 lgr %r2,%r11 # pass pointer to pt_regs
889 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
894 # _TIF_NOTIFY_RESUME or is set, call do_notify_resume
897 # TRACE_IRQS_ON already done at .Lio_return
898 ssm __LC_SVC_NEW_PSW # reenable interrupts
899 lgr %r2,%r11 # pass pointer to pt_regs
900 brasl %r14,do_notify_resume
901 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
906 * External interrupt handler routine
908 ENTRY(ext_int_handler)
910 stpt __LC_ASYNC_ENTER_TIMER
912 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
914 larl %r13,cleanup_critical
915 lmg %r8,%r9,__LC_EXT_OLD_PSW
916 SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
917 stmg %r0,%r7,__PT_R0(%r11)
918 # clear user controlled registers to prevent speculative use
928 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
929 stmg %r8,%r9,__PT_PSW(%r11)
930 lghi %r1,__LC_EXT_PARAMS2
931 mvc __PT_INT_CODE(4,%r11),__LC_EXT_CPU_ADDR
932 mvc __PT_INT_PARM(4,%r11),__LC_EXT_PARAMS
933 mvc __PT_INT_PARM_LONG(8,%r11),0(%r1)
934 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
935 TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ
938 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
939 lgr %r2,%r11 # pass pointer to pt_regs
940 lghi %r3,EXT_INTERRUPT
945 * Load idle PSW. The second "half" of this function is in .Lcleanup_idle.
948 stg %r3,__SF_EMPTY(%r15)
949 larl %r1,.Lpsw_idle_lpsw+4
950 stg %r1,__SF_EMPTY+8(%r15)
952 larl %r1,smp_cpu_mtid
956 .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+16(%r15)
959 oi __LC_CPU_FLAGS+7,_CIF_ENABLED_WAIT
961 STCK __CLOCK_IDLE_ENTER(%r2)
962 stpt __TIMER_IDLE_ENTER(%r2)
964 lpswe __SF_EMPTY(%r15)
969 * Store floating-point controls and floating-point or vector register
970 * depending whether the vector facility is available. A critical section
971 * cleanup assures that the registers are stored even if interrupted for
972 * some other work. The CIF_FPU flag is set to trigger a lazy restore
973 * of the register contents at return from io or a system call.
977 aghi %r2,__TASK_thread
978 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
979 jo .Lsave_fpu_regs_exit
980 stfpc __THREAD_FPU_fpc(%r2)
981 lg %r3,__THREAD_FPU_regs(%r2)
982 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
983 jz .Lsave_fpu_regs_fp # no -> store FP regs
984 VSTM %v0,%v15,0,%r3 # vstm 0,15,0(3)
985 VSTM %v16,%v31,256,%r3 # vstm 16,31,256(3)
986 j .Lsave_fpu_regs_done # -> set CIF_FPU flag
1004 .Lsave_fpu_regs_done:
1005 oi __LC_CPU_FLAGS+7,_CIF_FPU
1006 .Lsave_fpu_regs_exit:
1008 .Lsave_fpu_regs_end:
1009 EXPORT_SYMBOL(save_fpu_regs)
1012 * Load floating-point controls and floating-point or vector registers.
1013 * A critical section cleanup assures that the register contents are
1014 * loaded even if interrupted for some other work.
1016 * There are special calling conventions to fit into sysc and io return work:
1017 * %r15: <kernel stack>
1018 * The function requires:
1023 aghi %r4,__TASK_thread
1024 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
1025 jno .Lload_fpu_regs_exit
1026 lfpc __THREAD_FPU_fpc(%r4)
1027 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1028 lg %r4,__THREAD_FPU_regs(%r4) # %r4 <- reg save area
1029 jz .Lload_fpu_regs_fp # -> no VX, load FP regs
1031 VLM %v16,%v31,256,%r4
1032 j .Lload_fpu_regs_done
1050 .Lload_fpu_regs_done:
1051 ni __LC_CPU_FLAGS+7,255-_CIF_FPU
1052 .Lload_fpu_regs_exit:
1054 .Lload_fpu_regs_end:
1059 * Machine check handler routines
1061 ENTRY(mcck_int_handler)
1062 STCK __LC_MCCK_CLOCK
1064 la %r1,4095 # validate r1
1065 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # validate cpu timer
1066 sckc __LC_CLOCK_COMPARATOR # validate comparator
1067 lam %a0,%a15,__LC_AREGS_SAVE_AREA-4095(%r1) # validate acrs
1068 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# validate gprs
1069 lg %r12,__LC_CURRENT
1070 larl %r13,cleanup_critical
1071 lmg %r8,%r9,__LC_MCK_OLD_PSW
1072 TSTMSK __LC_MCCK_CODE,MCCK_CODE_SYSTEM_DAMAGE
1073 jo .Lmcck_panic # yes -> rest of mcck code invalid
1074 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CR_VALID
1075 jno .Lmcck_panic # control registers invalid -> panic
1077 lctlg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r14) # validate ctl regs
1079 lg %r11,__LC_MCESAD-4095(%r14) # extended machine check save area
1080 nill %r11,0xfc00 # MCESA_ORIGIN_MASK
1081 TSTMSK __LC_CREGS_SAVE_AREA+16-4095(%r14),CR2_GUARDED_STORAGE
1083 TSTMSK __LC_MCCK_CODE,MCCK_CODE_GS_VALID
1085 .insn rxy,0xe3000000004d,0,__MCESA_GS_SAVE_AREA(%r11) # LGSC
1086 0: l %r14,__LC_FP_CREG_SAVE_AREA-4095(%r14)
1087 TSTMSK __LC_MCCK_CODE,MCCK_CODE_FC_VALID
1091 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1093 lghi %r14,__LC_FPREGS_SAVE_AREA
1111 0: VLM %v0,%v15,0,%r11
1112 VLM %v16,%v31,256,%r11
1113 1: lghi %r14,__LC_CPU_TIMER_SAVE_AREA
1114 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
1115 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID
1117 la %r14,__LC_SYNC_ENTER_TIMER
1118 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
1120 la %r14,__LC_ASYNC_ENTER_TIMER
1121 0: clc 0(8,%r14),__LC_EXIT_TIMER
1123 la %r14,__LC_EXIT_TIMER
1124 1: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
1126 la %r14,__LC_LAST_UPDATE_TIMER
1128 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
1129 3: TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_MWP_VALID
1131 tmhh %r8,0x0001 # interrupting from user ?
1133 TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_IA_VALID
1135 4: SWITCH_ASYNC __LC_GPREGS_SAVE_AREA+64,__LC_MCCK_ENTER_TIMER
1137 lghi %r14,__LC_GPREGS_SAVE_AREA+64
1138 stmg %r0,%r7,__PT_R0(%r11)
1139 # clear user controlled registers to prevent speculative use
1149 mvc __PT_R8(64,%r11),0(%r14)
1150 stmg %r8,%r9,__PT_PSW(%r11)
1151 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
1152 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1153 lgr %r2,%r11 # pass pointer to pt_regs
1154 brasl %r14,s390_do_machine_check
1155 tm __PT_PSW+1(%r11),0x01 # returning to user ?
1157 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
1158 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
1159 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
1160 la %r11,STACK_FRAME_OVERHEAD(%r1)
1162 ssm __LC_PGM_NEW_PSW # turn dat on, keep irqs off
1163 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
1166 brasl %r14,s390_handle_mcck
1169 lg %r14,__LC_VDSO_PER_CPU
1170 lmg %r0,%r10,__PT_R0(%r11)
1171 mvc __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
1172 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
1174 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
1175 stpt __LC_EXIT_TIMER
1176 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
1177 0: lmg %r11,%r15,__PT_R11(%r11)
1178 lpswe __LC_RETURN_MCCK_PSW
1181 lg %r15,__LC_PANIC_STACK
1182 la %r11,STACK_FRAME_OVERHEAD(%r15)
1186 # PSW restart interrupt handler
1188 ENTRY(restart_int_handler)
1189 ALTERNATIVE "", ".insn s,0xb2800000,_LPP_OFFSET", 40
1190 stg %r15,__LC_SAVE_AREA_RESTART
1191 lg %r15,__LC_RESTART_STACK
1192 aghi %r15,-__PT_SIZE # create pt_regs on stack
1193 xc 0(__PT_SIZE,%r15),0(%r15)
1194 stmg %r0,%r14,__PT_R0(%r15)
1195 mvc __PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
1196 mvc __PT_PSW(16,%r15),__LC_RST_OLD_PSW # store restart old psw
1197 aghi %r15,-STACK_FRAME_OVERHEAD # create stack frame on stack
1198 xc 0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
1199 lg %r1,__LC_RESTART_FN # load fn, parm & source cpu
1200 lg %r2,__LC_RESTART_DATA
1201 lg %r3,__LC_RESTART_SOURCE
1202 ltgr %r3,%r3 # test source cpu address
1203 jm 1f # negative -> skip source stop
1204 0: sigp %r4,%r3,SIGP_SENSE # sigp sense to source cpu
1205 brc 10,0b # wait for status stored
1206 1: basr %r14,%r1 # call function
1207 stap __SF_EMPTY(%r15) # store cpu address
1208 llgh %r3,__SF_EMPTY(%r15)
1209 2: sigp %r4,%r3,SIGP_STOP # sigp stop to current cpu
1213 .section .kprobes.text, "ax"
1215 #ifdef CONFIG_CHECK_STACK
1217 * The synchronous or the asynchronous stack overflowed. We are dead.
1218 * No need to properly save the registers, we are going to panic anyway.
1219 * Setup a pt_regs so that show_trace can provide a good call trace.
1222 lg %r15,__LC_PANIC_STACK # change to panic stack
1223 la %r11,STACK_FRAME_OVERHEAD(%r15)
1224 stmg %r0,%r7,__PT_R0(%r11)
1225 stmg %r8,%r9,__PT_PSW(%r11)
1226 mvc __PT_R8(64,%r11),0(%r14)
1227 stg %r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
1228 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1229 lgr %r2,%r11 # pass pointer to pt_regs
1230 jg kernel_stack_overflow
1234 #if IS_ENABLED(CONFIG_KVM)
1235 clg %r9,BASED(.Lcleanup_table_sie) # .Lsie_gmap
1237 clg %r9,BASED(.Lcleanup_table_sie+8)# .Lsie_done
1240 clg %r9,BASED(.Lcleanup_table) # system_call
1242 clg %r9,BASED(.Lcleanup_table+8) # .Lsysc_do_svc
1243 jl .Lcleanup_system_call
1244 clg %r9,BASED(.Lcleanup_table+16) # .Lsysc_tif
1246 clg %r9,BASED(.Lcleanup_table+24) # .Lsysc_restore
1247 jl .Lcleanup_sysc_tif
1248 clg %r9,BASED(.Lcleanup_table+32) # .Lsysc_done
1249 jl .Lcleanup_sysc_restore
1250 clg %r9,BASED(.Lcleanup_table+40) # .Lio_tif
1252 clg %r9,BASED(.Lcleanup_table+48) # .Lio_restore
1254 clg %r9,BASED(.Lcleanup_table+56) # .Lio_done
1255 jl .Lcleanup_io_restore
1256 clg %r9,BASED(.Lcleanup_table+64) # psw_idle
1258 clg %r9,BASED(.Lcleanup_table+72) # .Lpsw_idle_end
1260 clg %r9,BASED(.Lcleanup_table+80) # save_fpu_regs
1262 clg %r9,BASED(.Lcleanup_table+88) # .Lsave_fpu_regs_end
1263 jl .Lcleanup_save_fpu_regs
1264 clg %r9,BASED(.Lcleanup_table+96) # load_fpu_regs
1266 clg %r9,BASED(.Lcleanup_table+104) # .Lload_fpu_regs_end
1267 jl .Lcleanup_load_fpu_regs
1275 .quad .Lsysc_restore
1281 .quad .Lpsw_idle_end
1283 .quad .Lsave_fpu_regs_end
1285 .quad .Lload_fpu_regs_end
1287 #if IS_ENABLED(CONFIG_KVM)
1288 .Lcleanup_table_sie:
1293 cghi %r11,__LC_SAVE_AREA_ASYNC #Is this in normal interrupt?
1295 slg %r9,BASED(.Lsie_crit_mcck_start)
1296 clg %r9,BASED(.Lsie_crit_mcck_length)
1298 oi __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST
1299 1: BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
1300 lg %r9,__SF_SIE_CONTROL(%r15) # get control block pointer
1301 ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE
1302 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
1303 larl %r9,sie_exit # skip forward to sie_exit
1307 .Lcleanup_system_call:
1308 # check if stpt has been executed
1309 clg %r9,BASED(.Lcleanup_system_call_insn)
1311 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
1312 cghi %r11,__LC_SAVE_AREA_ASYNC
1314 mvc __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
1315 0: # check if stmg has been executed
1316 clg %r9,BASED(.Lcleanup_system_call_insn+8)
1318 mvc __LC_SAVE_AREA_SYNC(64),0(%r11)
1319 0: # check if base register setup + TIF bit load has been done
1320 clg %r9,BASED(.Lcleanup_system_call_insn+16)
1322 # set up saved register r12 task struct pointer
1324 # set up saved register r13 __TASK_thread offset
1325 mvc 40(8,%r11),BASED(.Lcleanup_system_call_const)
1326 0: # check if the user time update has been done
1327 clg %r9,BASED(.Lcleanup_system_call_insn+24)
1329 lg %r15,__LC_EXIT_TIMER
1330 slg %r15,__LC_SYNC_ENTER_TIMER
1331 alg %r15,__LC_USER_TIMER
1332 stg %r15,__LC_USER_TIMER
1333 0: # check if the system time update has been done
1334 clg %r9,BASED(.Lcleanup_system_call_insn+32)
1336 lg %r15,__LC_LAST_UPDATE_TIMER
1337 slg %r15,__LC_EXIT_TIMER
1338 alg %r15,__LC_SYSTEM_TIMER
1339 stg %r15,__LC_SYSTEM_TIMER
1340 0: # update accounting time stamp
1341 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
1342 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
1343 # set up saved register r11
1344 lg %r15,__LC_KERNEL_STACK
1345 la %r9,STACK_FRAME_OVERHEAD(%r15)
1346 stg %r9,24(%r11) # r11 pt_regs pointer
1348 mvc __PT_R8(64,%r9),__LC_SAVE_AREA_SYNC
1349 stmg %r0,%r7,__PT_R0(%r9)
1350 mvc __PT_PSW(16,%r9),__LC_SVC_OLD_PSW
1351 mvc __PT_INT_CODE(4,%r9),__LC_SVC_ILC
1352 xc __PT_FLAGS(8,%r9),__PT_FLAGS(%r9)
1353 mvi __PT_FLAGS+7(%r9),_PIF_SYSCALL
1354 # setup saved register r15
1355 stg %r15,56(%r11) # r15 stack pointer
1356 # set new psw address and exit
1357 larl %r9,.Lsysc_do_svc
1359 .Lcleanup_system_call_insn:
1363 .quad .Lsysc_vtime+36
1364 .quad .Lsysc_vtime+42
1365 .Lcleanup_system_call_const:
1372 .Lcleanup_sysc_restore:
1373 # check if stpt has been executed
1374 clg %r9,BASED(.Lcleanup_sysc_restore_insn)
1376 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
1377 cghi %r11,__LC_SAVE_AREA_ASYNC
1379 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
1380 0: clg %r9,BASED(.Lcleanup_sysc_restore_insn+8)
1382 lg %r9,24(%r11) # get saved pointer to pt_regs
1383 mvc __LC_RETURN_PSW(16),__PT_PSW(%r9)
1384 mvc 0(64,%r11),__PT_R8(%r9)
1385 lmg %r0,%r7,__PT_R0(%r9)
1386 1: lmg %r8,%r9,__LC_RETURN_PSW
1388 .Lcleanup_sysc_restore_insn:
1389 .quad .Lsysc_exit_timer
1390 .quad .Lsysc_done - 4
1396 .Lcleanup_io_restore:
1397 # check if stpt has been executed
1398 clg %r9,BASED(.Lcleanup_io_restore_insn)
1400 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
1401 0: clg %r9,BASED(.Lcleanup_io_restore_insn+8)
1403 lg %r9,24(%r11) # get saved r11 pointer to pt_regs
1404 mvc __LC_RETURN_PSW(16),__PT_PSW(%r9)
1405 mvc 0(64,%r11),__PT_R8(%r9)
1406 lmg %r0,%r7,__PT_R0(%r9)
1407 1: lmg %r8,%r9,__LC_RETURN_PSW
1409 .Lcleanup_io_restore_insn:
1410 .quad .Lio_exit_timer
1414 ni __LC_CPU_FLAGS+7,255-_CIF_ENABLED_WAIT
1415 # copy interrupt clock & cpu timer
1416 mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_INT_CLOCK
1417 mvc __TIMER_IDLE_EXIT(8,%r2),__LC_ASYNC_ENTER_TIMER
1418 cghi %r11,__LC_SAVE_AREA_ASYNC
1420 mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
1421 mvc __TIMER_IDLE_EXIT(8,%r2),__LC_MCCK_ENTER_TIMER
1422 0: # check if stck & stpt have been executed
1423 clg %r9,BASED(.Lcleanup_idle_insn)
1425 mvc __CLOCK_IDLE_ENTER(8,%r2),__CLOCK_IDLE_EXIT(%r2)
1426 mvc __TIMER_IDLE_ENTER(8,%r2),__TIMER_IDLE_EXIT(%r2)
1427 1: # calculate idle cycles
1429 clg %r9,BASED(.Lcleanup_idle_insn)
1431 larl %r1,smp_cpu_mtid
1435 .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+80(%r15)
1437 ag %r3,__LC_PERCPU_OFFSET
1438 la %r4,__SF_EMPTY+16(%r15)
1447 3: # account system time going idle
1448 lg %r9,__LC_STEAL_TIMER
1449 alg %r9,__CLOCK_IDLE_ENTER(%r2)
1450 slg %r9,__LC_LAST_UPDATE_CLOCK
1451 stg %r9,__LC_STEAL_TIMER
1452 mvc __LC_LAST_UPDATE_CLOCK(8),__CLOCK_IDLE_EXIT(%r2)
1453 lg %r9,__LC_SYSTEM_TIMER
1454 alg %r9,__LC_LAST_UPDATE_TIMER
1455 slg %r9,__TIMER_IDLE_ENTER(%r2)
1456 stg %r9,__LC_SYSTEM_TIMER
1457 mvc __LC_LAST_UPDATE_TIMER(8),__TIMER_IDLE_EXIT(%r2)
1458 # prepare return psw
1459 nihh %r8,0xfcfd # clear irq & wait state bits
1460 lg %r9,48(%r11) # return from psw_idle
1462 .Lcleanup_idle_insn:
1463 .quad .Lpsw_idle_lpsw
1465 .Lcleanup_save_fpu_regs:
1466 larl %r9,save_fpu_regs
1469 .Lcleanup_load_fpu_regs:
1470 larl %r9,load_fpu_regs
1478 .quad .L__critical_start
1480 .quad .L__critical_end - .L__critical_start
1481 #if IS_ENABLED(CONFIG_KVM)
1482 .Lsie_critical_start:
1484 .Lsie_critical_length:
1485 .quad .Lsie_done - .Lsie_gmap
1486 .Lsie_crit_mcck_start:
1488 .Lsie_crit_mcck_length:
1489 .quad .Lsie_skip - .Lsie_entry
1491 .section .rodata, "a"
1492 #define SYSCALL(esame,emu) .long esame
1493 .globl sys_call_table
1495 #include "asm/syscall_table.h"
1498 #ifdef CONFIG_COMPAT
1500 #define SYSCALL(esame,emu) .long emu
1501 .globl sys_call_table_emu
1503 #include "asm/syscall_table.h"