1 /* SPDX-License-Identifier: GPL-2.0 */
3 * S390 low-level entry points.
5 * Copyright IBM Corp. 1999, 2012
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
11 #include <linux/init.h>
12 #include <linux/linkage.h>
13 #include <asm/asm-extable.h>
14 #include <asm/alternative-asm.h>
15 #include <asm/processor.h>
16 #include <asm/cache.h>
17 #include <asm/dwarf.h>
18 #include <asm/errno.h>
19 #include <asm/ptrace.h>
20 #include <asm/thread_info.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/unistd.h>
26 #include <asm/vx-insn.h>
27 #include <asm/setup.h>
29 #include <asm/export.h>
30 #include <asm/nospec-insn.h>
33 __PT_R1 = __PT_GPRS + 8
34 __PT_R2 = __PT_GPRS + 16
35 __PT_R3 = __PT_GPRS + 24
36 __PT_R4 = __PT_GPRS + 32
37 __PT_R5 = __PT_GPRS + 40
38 __PT_R6 = __PT_GPRS + 48
39 __PT_R7 = __PT_GPRS + 56
40 __PT_R8 = __PT_GPRS + 64
41 __PT_R9 = __PT_GPRS + 72
42 __PT_R10 = __PT_GPRS + 80
43 __PT_R11 = __PT_GPRS + 88
44 __PT_R12 = __PT_GPRS + 96
45 __PT_R13 = __PT_GPRS + 104
46 __PT_R14 = __PT_GPRS + 112
47 __PT_R15 = __PT_GPRS + 120
49 STACK_SHIFT = PAGE_SHIFT + THREAD_SIZE_ORDER
50 STACK_SIZE = 1 << STACK_SHIFT
51 STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
53 _LPP_OFFSET = __LC_LPP
56 ALTERNATIVE "nop", ".insn s,0xb2010000,\address", 193
60 ALTERNATIVE "nop", ".insn s,0xb2000000,\address", 193
63 .macro LPSWEY address,lpswe
64 ALTERNATIVE "b \lpswe; nopr", ".insn siy,0xeb0000000071,\address,0", 193
68 ALTERNATIVE "brcl 0,0", __stringify(mvc __PT_LAST_BREAK(8,\reg),__LC_LAST_BREAK), 193
71 .macro CHECK_STACK savearea
72 #ifdef CONFIG_CHECK_STACK
73 tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
79 .macro CHECK_VMAP_STACK savearea,oklabel
80 #ifdef CONFIG_VMAP_STACK
82 nill %r14,0x10000 - STACK_SIZE
84 clg %r14,__LC_KERNEL_STACK
86 clg %r14,__LC_ASYNC_STACK
88 clg %r14,__LC_MCCK_STACK
90 clg %r14,__LC_NODAT_STACK
92 clg %r14,__LC_RESTART_STACK
102 * The TSTMSK macro generates a test-under-mask instruction by
103 * calculating the memory offset for the specified mask value.
104 * Mask value can be any constant. The macro shifts the mask
105 * value to calculate the memory offset for the test-under-mask
108 .macro TSTMSK addr, mask, size=8, bytepos=0
109 .if (\bytepos < \size) && (\mask >> 8)
111 .error "Mask exceeds byte boundary"
113 TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)"
117 .error "Mask must not be zero"
119 off = \size - \bytepos - 1
124 ALTERNATIVE "nop", ".insn rrf,0xb2e80000,0,0,12,0", 82
128 ALTERNATIVE "nop", ".insn rrf,0xb2e80000,0,0,13,0", 82
131 .macro BPENTER tif_ptr,tif_mask
132 ALTERNATIVE "TSTMSK \tif_ptr,\tif_mask; jz .+8; .insn rrf,0xb2e80000,0,0,13,0", \
133 "j .+12; nop; nop", 82
136 .macro BPEXIT tif_ptr,tif_mask
137 TSTMSK \tif_ptr,\tif_mask
138 ALTERNATIVE "jz .+8; .insn rrf,0xb2e80000,0,0,12,0", \
139 "jnz .+8; .insn rrf,0xb2e80000,0,0,13,0", 82
143 * The CHKSTG macro jumps to the provided label in case the
144 * machine check interruption code reports one of unrecoverable
146 * - Storage error uncorrected
147 * - Storage key error uncorrected
148 * - Storage degradation with Failing-storage-address validity
150 .macro CHKSTG errlabel
151 TSTMSK __LC_MCCK_CODE,(MCCK_CODE_STG_ERROR|MCCK_CODE_STG_KEY_ERROR)
153 TSTMSK __LC_MCCK_CODE,MCCK_CODE_STG_DEGRAD
155 TSTMSK __LC_MCCK_CODE,MCCK_CODE_STG_FAIL_ADDR
160 #if IS_ENABLED(CONFIG_KVM)
162 * The OUTSIDE macro jumps to the provided label in case the value
163 * in the provided register is outside of the provided range. The
164 * macro is useful for checking whether a PSW stored in a register
165 * pair points inside or outside of a block of instructions.
166 * @reg: register to check
167 * @start: start of the range
168 * @end: end of the range
169 * @outside_label: jump here if @reg is outside of [@start..@end)
171 .macro OUTSIDE reg,start,end,outside_label
175 #ifdef CONFIG_AS_IS_LLVM
176 clgfrl %r14,.Lrange_size\@
178 clgfi %r14,\end - \start
181 #ifdef CONFIG_AS_IS_LLVM
182 .section .rodata, "a"
191 lg %r9,__SF_SIE_CONTROL(%r15) # get control block pointer
192 ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE
193 lctlg %c1,%c1,__LC_KERNEL_ASCE # load primary asce
194 larl %r9,sie_exit # skip forward to sie_exit
200 .section .kprobes.text, "ax"
203 * This nop exists only in order to avoid that __bpon starts at
204 * the beginning of the kprobes text section. In that case we would
205 * have several symbols at the same address. E.g. objdump would take
206 * an arbitrary symbol name when disassembling this code.
207 * With the added nop in between the __bpon symbol is unique
219 * Scheduler resume function, called by switch_to
220 * gpr2 = (task_struct *) prev
221 * gpr3 = (task_struct *) next
226 stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task
227 lghi %r4,__TASK_stack
228 lghi %r1,__TASK_thread
230 stg %r15,__THREAD_ksp(%r1,%r2) # store kernel stack of prev
231 lg %r15,0(%r4,%r3) # start of kernel stack of next
232 agr %r15,%r5 # end of kernel stack of next
233 stg %r3,__LC_CURRENT # store task struct of next
234 stg %r15,__LC_KERNEL_STACK # store end of kernel stack
235 lg %r15,__THREAD_ksp(%r1,%r3) # load kernel stack of next
237 mvc __LC_CURRENT_PID(4,%r0),0(%r3) # store pid of next
238 lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
239 ALTERNATIVE "nop", "lpp _LPP_OFFSET", 40
243 #if IS_ENABLED(CONFIG_KVM)
245 * sie64a calling convention:
246 * %r2 pointer to sie control block
247 * %r3 guest register save area
250 stmg %r6,%r14,__SF_GPRS(%r15) # save kernel registers
252 stg %r2,__SF_SIE_CONTROL(%r15) # save control block pointer
253 stg %r3,__SF_SIE_SAVEAREA(%r15) # save guest register save area
254 xc __SF_SIE_REASON(8,%r15),__SF_SIE_REASON(%r15) # reason code = 0
255 mvc __SF_SIE_FLAGS(8,%r15),__TI_flags(%r12) # copy thread flags
256 lmg %r0,%r13,0(%r3) # load guest gprs 0-13
257 lg %r14,__LC_GMAP # get gmap pointer
260 lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce
262 lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer
263 oi __SIE_PROG0C+3(%r14),1 # we are going into SIE now
264 tm __SIE_PROG20+3(%r14),3 # last exit...
266 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
267 jo .Lsie_skip # exit if fp/vx regs changed
268 BPEXIT __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
272 BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
274 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
275 lctlg %c1,%c1,__LC_KERNEL_ASCE # load primary asce
277 # some program checks are suppressing. C code (e.g. do_protection_exception)
278 # will rewind the PSW by the ILC, which is often 4 bytes in case of SIE. There
279 # are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable.
280 # Other instructions between sie64a and .Lsie_done should not cause program
281 # interrupts. So lets use 3 nops as a landing pad for all possible rewinds.
290 lg %r14,__SF_SIE_SAVEAREA(%r15) # load guest register save area
291 stmg %r0,%r13,0(%r14) # save guest gprs 0-13
292 xgr %r0,%r0 # clear guest registers to
293 xgr %r1,%r1 # prevent speculative use
297 lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers
298 lg %r2,__SF_SIE_REASON(%r15) # return exit reason code
302 stg %r14,__SF_SIE_REASON(%r15) # set exit reason code
305 EX_TABLE(.Lrewind_pad6,.Lsie_fault)
306 EX_TABLE(.Lrewind_pad4,.Lsie_fault)
307 EX_TABLE(.Lrewind_pad2,.Lsie_fault)
308 EX_TABLE(sie_exit,.Lsie_fault)
310 EXPORT_SYMBOL(sie64a)
311 EXPORT_SYMBOL(sie_exit)
315 * SVC interrupt handler routine. System calls are synchronous events and
316 * are entered with interrupts disabled.
320 stpt __LC_SYS_ENTER_TIMER
321 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
325 STBEAR __LC_LAST_BREAK
326 lctlg %c1,%c1,__LC_KERNEL_ASCE
328 lg %r15,__LC_KERNEL_STACK
329 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
330 stmg %r0,%r7,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
331 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
332 # clear user controlled register to prevent speculative use
343 la %r2,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs
344 mvc __PT_R8(64,%r2),__LC_SAVE_AREA_SYNC
347 brasl %r14,__do_syscall
348 lctlg %c1,%c1,__LC_USER_ASCE
349 mvc __LC_RETURN_PSW(16),STACK_FRAME_OVERHEAD+__PT_PSW(%r15)
350 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
351 LBEAR STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15)
352 lmg %r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
354 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE
358 # a new process exits the kernel with ret_from_fork
362 brasl %r14,__ret_from_fork
363 lctlg %c1,%c1,__LC_USER_ASCE
364 mvc __LC_RETURN_PSW(16),STACK_FRAME_OVERHEAD+__PT_PSW(%r15)
365 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
366 LBEAR STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15)
367 lmg %r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
369 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE
370 ENDPROC(ret_from_fork)
373 * Program check handler routine
376 ENTRY(pgm_check_handler)
377 stpt __LC_SYS_ENTER_TIMER
379 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
382 lmg %r8,%r9,__LC_PGM_OLD_PSW
383 tmhh %r8,0x0001 # coming from user space?
385 lctlg %c1,%c1,__LC_KERNEL_ASCE
386 j 3f # -> fault in user space
388 #if IS_ENABLED(CONFIG_KVM)
389 # cleanup critical section for program checks in sie64a
390 OUTSIDE %r9,.Lsie_gmap,.Lsie_done,1f
392 lghi %r10,_PIF_GUEST_FAULT
394 1: tmhh %r8,0x4000 # PER bit set in old PSW ?
395 jnz 2f # -> enabled, can't be a double fault
396 tm __LC_PGM_ILC+3,0x80 # check for per exception
397 jnz .Lpgm_svcper # -> single stepped svc
398 2: CHECK_STACK __LC_SAVE_AREA_SYNC
399 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
400 # CHECK_VMAP_STACK branches to stack_overflow or 4f
401 CHECK_VMAP_STACK __LC_SAVE_AREA_SYNC,4f
402 3: BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
403 lg %r15,__LC_KERNEL_STACK
404 4: la %r11,STACK_FRAME_OVERHEAD(%r15)
405 stg %r10,__PT_FLAGS(%r11)
406 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
407 stmg %r0,%r7,__PT_R0(%r11)
408 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
409 mvc __PT_LAST_BREAK(8,%r11),__LC_PGM_LAST_BREAK
410 stmg %r8,%r9,__PT_PSW(%r11)
412 # clear user controlled registers to prevent speculative use
421 brasl %r14,__do_pgm_check
422 tmhh %r8,0x0001 # returning to user space?
423 jno .Lpgm_exit_kernel
424 lctlg %c1,%c1,__LC_USER_ASCE
425 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
428 mvc __LC_RETURN_PSW(16),STACK_FRAME_OVERHEAD+__PT_PSW(%r15)
429 LBEAR STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15)
430 lmg %r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
431 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE
434 # single stepped system call
437 mvc __LC_RETURN_PSW(8),__LC_SVC_NEW_PSW
439 stg %r14,__LC_RETURN_PSW+8
441 LBEAR __LC_PGM_LAST_BREAK
442 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE # branch to .Lsysc_per
443 ENDPROC(pgm_check_handler)
446 * Interrupt handler macro used for external and IO interrupts.
448 .macro INT_HANDLER name,lc_old_psw,handler
451 stpt __LC_SYS_ENTER_TIMER
452 STBEAR __LC_LAST_BREAK
454 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
456 lmg %r8,%r9,\lc_old_psw
457 tmhh %r8,0x0001 # interrupting from user ?
459 #if IS_ENABLED(CONFIG_KVM)
460 OUTSIDE %r9,.Lsie_gmap,.Lsie_done,0f
461 BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
464 0: CHECK_STACK __LC_SAVE_AREA_ASYNC
465 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
467 1: BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
468 lctlg %c1,%c1,__LC_KERNEL_ASCE
469 lg %r15,__LC_KERNEL_STACK
470 2: xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
471 la %r11,STACK_FRAME_OVERHEAD(%r15)
472 stmg %r0,%r7,__PT_R0(%r11)
473 # clear user controlled registers to prevent speculative use
482 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
483 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
485 stmg %r8,%r9,__PT_PSW(%r11)
486 lgr %r2,%r11 # pass pointer to pt_regs
488 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
489 tmhh %r8,0x0001 # returning to user ?
491 lctlg %c1,%c1,__LC_USER_ASCE
492 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
494 2: LBEAR __PT_LAST_BREAK(%r11)
495 lmg %r0,%r15,__PT_R0(%r11)
496 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE
500 INT_HANDLER ext_int_handler,__LC_EXT_OLD_PSW,do_ext_irq
501 INT_HANDLER io_int_handler,__LC_IO_OLD_PSW,do_io_irq
507 stg %r14,(__SF_GPRS+8*8)(%r15)
508 stg %r3,__SF_EMPTY(%r15)
509 larl %r1,psw_idle_exit
510 stg %r1,__SF_EMPTY+8(%r15)
511 larl %r1,smp_cpu_mtid
515 .insn rsy,0xeb0000000017,%r1,5,__MT_CYCLES_ENTER(%r2)
517 oi __LC_CPU_FLAGS+7,_CIF_ENABLED_WAIT
519 stckf __CLOCK_IDLE_ENTER(%r2)
520 stpt __TIMER_IDLE_ENTER(%r2)
521 lpswe __SF_EMPTY(%r15)
528 * Machine check handler routines
530 ENTRY(mcck_int_handler)
531 stckf __LC_MCCK_CLOCK
533 la %r1,4095 # validate r1
534 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # validate cpu timer
535 LBEAR __LC_LAST_BREAK_SAVE_AREA-4095(%r1) # validate bear
536 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# validate gprs
538 lmg %r8,%r9,__LC_MCK_OLD_PSW
539 TSTMSK __LC_MCCK_CODE,MCCK_CODE_SYSTEM_DAMAGE
540 jo .Lmcck_panic # yes -> rest of mcck code invalid
541 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CR_VALID
542 jno .Lmcck_panic # control registers invalid -> panic
544 lctlg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r14) # validate ctl regs
546 lghi %r14,__LC_CPU_TIMER_SAVE_AREA
547 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
548 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID
550 la %r14,__LC_SYS_ENTER_TIMER
551 clc 0(8,%r14),__LC_EXIT_TIMER
553 la %r14,__LC_EXIT_TIMER
554 1: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
556 la %r14,__LC_LAST_UPDATE_TIMER
558 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
559 3: TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_MWP_VALID
561 tmhh %r8,0x0001 # interrupting from user ?
563 TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_IA_VALID
565 #if IS_ENABLED(CONFIG_KVM)
566 OUTSIDE %r9,.Lsie_gmap,.Lsie_done,6f
567 OUTSIDE %r9,.Lsie_entry,.Lsie_skip,4f
568 oi __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST
570 4: CHKSTG .Lmcck_panic
571 5: larl %r14,.Lstosm_tmp
572 stosm 0(%r14),0x04 # turn dat on, keep irqs off
573 BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
577 6: CHKSTG .Lmcck_panic
578 larl %r14,.Lstosm_tmp
579 stosm 0(%r14),0x04 # turn dat on, keep irqs off
580 tmhh %r8,0x0001 # interrupting from user ?
582 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
584 lg %r15,__LC_MCCK_STACK
585 la %r11,STACK_FRAME_OVERHEAD(%r15)
586 stctg %c1,%c1,__PT_CR1(%r11)
587 lctlg %c1,%c1,__LC_KERNEL_ASCE
588 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
589 lghi %r14,__LC_GPREGS_SAVE_AREA+64
590 stmg %r0,%r7,__PT_R0(%r11)
591 # clear user controlled registers to prevent speculative use
600 mvc __PT_R8(64,%r11),0(%r14)
601 stmg %r8,%r9,__PT_PSW(%r11)
602 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
603 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
604 lgr %r2,%r11 # pass pointer to pt_regs
605 brasl %r14,s390_do_machine_check
608 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
609 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
610 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
611 la %r11,STACK_FRAME_OVERHEAD(%r1)
614 brasl %r14,s390_handle_mcck
616 lctlg %c1,%c1,__PT_CR1(%r11)
617 lmg %r0,%r10,__PT_R0(%r11)
618 mvc __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
619 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
621 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
623 0: ALTERNATIVE "nop", __stringify(lghi %r12,__LC_LAST_BREAK_SAVE_AREA),193
625 lmg %r11,%r15,__PT_R11(%r11)
626 LPSWEY __LC_RETURN_MCCK_PSW,__LC_RETURN_MCCK_LPSWE
630 * Iterate over all possible CPU addresses in the range 0..0xffff
631 * and stop each CPU using signal processor. Use compare and swap
632 * to allow just one CPU-stopper and prevent concurrent CPUs from
633 * stopping each other while leaving the others running.
638 cs %r5,%r6,0(%r7) # single CPU-stopper only
641 stap 0(%r7) # this CPU address
645 sll %r0,16 # CPU counter
646 lhi %r3,0 # next CPU address
649 1: sigp %r1,%r3,SIGP_STOP # stop next CPU
653 3: sigp %r1,%r4,SIGP_STOP # stop this CPU
656 ENDPROC(mcck_int_handler)
658 ENTRY(restart_int_handler)
659 ALTERNATIVE "nop", "lpp _LPP_OFFSET", 40
660 stg %r15,__LC_SAVE_AREA_RESTART
661 TSTMSK __LC_RESTART_FLAGS,RESTART_FLAG_CTLREGS,4
664 lctlg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r15)
665 0: larl %r15,.Lstosm_tmp
666 stosm 0(%r15),0x04 # turn dat on, keep irqs off
667 lg %r15,__LC_RESTART_STACK
668 xc STACK_FRAME_OVERHEAD(__PT_SIZE,%r15),STACK_FRAME_OVERHEAD(%r15)
669 stmg %r0,%r14,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
670 mvc STACK_FRAME_OVERHEAD+__PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
671 mvc STACK_FRAME_OVERHEAD+__PT_PSW(16,%r15),__LC_RST_OLD_PSW
672 xc 0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
673 lg %r1,__LC_RESTART_FN # load fn, parm & source cpu
674 lg %r2,__LC_RESTART_DATA
675 lgf %r3,__LC_RESTART_SOURCE
676 ltgr %r3,%r3 # test source cpu address
677 jm 1f # negative -> skip source stop
678 0: sigp %r4,%r3,SIGP_SENSE # sigp sense to source cpu
679 brc 10,0b # wait for status stored
680 1: basr %r14,%r1 # call function
681 stap __SF_EMPTY(%r15) # store cpu address
682 llgh %r3,__SF_EMPTY(%r15)
683 2: sigp %r4,%r3,SIGP_STOP # sigp stop to current cpu
686 ENDPROC(restart_int_handler)
688 .section .kprobes.text, "ax"
690 #if defined(CONFIG_CHECK_STACK) || defined(CONFIG_VMAP_STACK)
692 * The synchronous or the asynchronous stack overflowed. We are dead.
693 * No need to properly save the registers, we are going to panic anyway.
694 * Setup a pt_regs so that show_trace can provide a good call trace.
696 ENTRY(stack_overflow)
697 lg %r15,__LC_NODAT_STACK # change to panic stack
698 la %r11,STACK_FRAME_OVERHEAD(%r15)
699 stmg %r0,%r7,__PT_R0(%r11)
700 stmg %r8,%r9,__PT_PSW(%r11)
701 mvc __PT_R8(64,%r11),0(%r14)
702 stg %r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
703 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
704 lgr %r2,%r11 # pass pointer to pt_regs
705 jg kernel_stack_overflow
706 ENDPROC(stack_overflow)
714 .section .rodata, "a"
715 #define SYSCALL(esame,emu) .quad __s390x_ ## esame
716 .globl sys_call_table
718 #include "asm/syscall_table.h"
723 #define SYSCALL(esame,emu) .quad __s390_ ## emu
724 .globl sys_call_table_emu
726 #include "asm/syscall_table.h"