1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Support for Vector Instructions
5 * Assembler macros to generate .byte/.word code for particular
6 * vector instructions that are supported by recent binutils (>= 2.26) only.
8 * Copyright IBM Corp. 2015
9 * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
12 #ifndef __ASM_S390_VX_INSN_H
13 #define __ASM_S390_VX_INSN_H
18 /* Macros to generate vector instruction byte code */
20 /* GR_NUM - Retrieve general-purpose register number
22 * @opd: Operand to store register number
23 * @r64: String designation register in the format "%rN"
80 /* VX_NUM - Retrieve vector register number
82 * @opd: Operand to store register number
83 * @vxr: String designation register in the format "%vN"
85 * The vector register number is used for as input number to the
86 * instruction and, as well as, to compute the RXB field of the
192 /* RXB - Compute most significant bit used vector registers
194 * @rxb: Operand to store computed RXB value
195 * @v1: First vector register designated operand
196 * @v2: Second vector register designated operand
197 * @v3: Third vector register designated operand
198 * @v4: Fourth vector register designated operand
200 .macro RXB rxb v1 v2=0 v3=0 v4=0
216 /* MRXB - Generate Element Size Control and RXB value
218 * @m: Element size control
219 * @v1: First vector register designated operand (for RXB)
220 * @v2: Second vector register designated operand (for RXB)
221 * @v3: Third vector register designated operand (for RXB)
222 * @v4: Fourth vector register designated operand (for RXB)
224 .macro MRXB m v1 v2=0 v3=0 v4=0
226 RXB rxb, \v1, \v2, \v3, \v4
227 .byte (\m << 4) | rxb
230 /* MRXBOPC - Generate Element Size Control, RXB, and final Opcode fields
232 * @m: Element size control
234 * @v1: First vector register designated operand (for RXB)
235 * @v2: Second vector register designated operand (for RXB)
236 * @v3: Third vector register designated operand (for RXB)
237 * @v4: Fourth vector register designated operand (for RXB)
239 .macro MRXBOPC m opc v1 v2=0 v3=0 v4=0
240 MRXB \m, \v1, \v2, \v3, \v4
244 /* Vector support instructions */
246 /* VECTOR GENERATE BYTE MASK */
249 .word (0xE700 | ((v1&15) << 4))
260 /* VECTOR LOAD VR ELEMENT FROM GR */
261 .macro VLVG v, gr, disp, m
265 .word 0xE700 | ((v1&15) << 4) | r3
266 .word (b2 << 12) | (\disp)
269 .macro VLVGB v, gr, index, base
270 VLVG \v, \gr, \index, \base, 0
272 .macro VLVGH v, gr, index
273 VLVG \v, \gr, \index, 1
275 .macro VLVGF v, gr, index
276 VLVG \v, \gr, \index, 2
278 .macro VLVGG v, gr, index
279 VLVG \v, \gr, \index, 3
282 /* VECTOR LOAD REGISTER */
286 .word 0xE700 | ((v1&15) << 4) | (v2&15)
288 MRXBOPC 0, 0x56, v1, v2
292 .macro VL v, disp, index="%r0", base
296 .word 0xE700 | ((v1&15) << 4) | x2
297 .word (b2 << 12) | (\disp)
301 /* VECTOR LOAD ELEMENT */
302 .macro VLEx vr1, disp, index="%r0", base, m3, opc
306 .word 0xE700 | ((v1&15) << 4) | x2
307 .word (b2 << 12) | (\disp)
308 MRXBOPC \m3, \opc, v1
310 .macro VLEB vr1, disp, index="%r0", base, m3
311 VLEx \vr1, \disp, \index, \base, \m3, 0x00
313 .macro VLEH vr1, disp, index="%r0", base, m3
314 VLEx \vr1, \disp, \index, \base, \m3, 0x01
316 .macro VLEF vr1, disp, index="%r0", base, m3
317 VLEx \vr1, \disp, \index, \base, \m3, 0x03
319 .macro VLEG vr1, disp, index="%r0", base, m3
320 VLEx \vr1, \disp, \index, \base, \m3, 0x02
323 /* VECTOR LOAD ELEMENT IMMEDIATE */
324 .macro VLEIx vr1, imm2, m3, opc
326 .word 0xE700 | ((v1&15) << 4)
328 MRXBOPC \m3, \opc, v1
330 .macro VLEIB vr1, imm2, index
331 VLEIx \vr1, \imm2, \index, 0x40
333 .macro VLEIH vr1, imm2, index
334 VLEIx \vr1, \imm2, \index, 0x41
336 .macro VLEIF vr1, imm2, index
337 VLEIx \vr1, \imm2, \index, 0x43
339 .macro VLEIG vr1, imm2, index
340 VLEIx \vr1, \imm2, \index, 0x42
343 /* VECTOR LOAD GR FROM VR ELEMENT */
344 .macro VLGV gr, vr, disp, base="%r0", m
348 .word 0xE700 | (r1 << 4) | (v3&15)
349 .word (b2 << 12) | (\disp)
352 .macro VLGVB gr, vr, disp, base="%r0"
353 VLGV \gr, \vr, \disp, \base, 0
355 .macro VLGVH gr, vr, disp, base="%r0"
356 VLGV \gr, \vr, \disp, \base, 1
358 .macro VLGVF gr, vr, disp, base="%r0"
359 VLGV \gr, \vr, \disp, \base, 2
361 .macro VLGVG gr, vr, disp, base="%r0"
362 VLGV \gr, \vr, \disp, \base, 3
365 /* VECTOR LOAD MULTIPLE */
366 .macro VLM vfrom, vto, disp, base, hint=3
370 .word 0xE700 | ((v1&15) << 4) | (v3&15)
371 .word (b2 << 12) | (\disp)
372 MRXBOPC \hint, 0x36, v1, v3
376 .macro VST vr1, disp, index="%r0", base
380 .word 0xE700 | ((v1&15) << 4) | (x2&15)
381 .word (b2 << 12) | (\disp)
385 /* VECTOR STORE MULTIPLE */
386 .macro VSTM vfrom, vto, disp, base, hint=3
390 .word 0xE700 | ((v1&15) << 4) | (v3&15)
391 .word (b2 << 12) | (\disp)
392 MRXBOPC \hint, 0x3E, v1, v3
396 .macro VPERM vr1, vr2, vr3, vr4
401 .word 0xE700 | ((v1&15) << 4) | (v2&15)
402 .word ((v3&15) << 12)
403 MRXBOPC (v4&15), 0x8C, v1, v2, v3, v4
406 /* VECTOR UNPACK LOGICAL LOW */
407 .macro VUPLL vr1, vr2, m3
410 .word 0xE700 | ((v1&15) << 4) | (v2&15)
412 MRXBOPC \m3, 0xD4, v1, v2
414 .macro VUPLLB vr1, vr2
417 .macro VUPLLH vr1, vr2
420 .macro VUPLLF vr1, vr2
424 /* VECTOR PERMUTE DOUBLEWORD IMMEDIATE */
425 .macro VPDI vr1, vr2, vr3, m4
429 .word 0xE700 | ((v1&15) << 4) | (v2&15)
430 .word ((v3&15) << 12)
431 MRXBOPC \m4, 0x84, v1, v2, v3
434 /* VECTOR REPLICATE */
435 .macro VREP vr1, vr3, imm2, m4
438 .word 0xE700 | ((v1&15) << 4) | (v3&15)
440 MRXBOPC \m4, 0x4D, v1, v3
442 .macro VREPB vr1, vr3, imm2
443 VREP \vr1, \vr3, \imm2, 0
445 .macro VREPH vr1, vr3, imm2
446 VREP \vr1, \vr3, \imm2, 1
448 .macro VREPF vr1, vr3, imm2
449 VREP \vr1, \vr3, \imm2, 2
451 .macro VREPG vr1, vr3, imm2
452 VREP \vr1, \vr3, \imm2, 3
455 /* VECTOR MERGE HIGH */
456 .macro VMRH vr1, vr2, vr3, m4
460 .word 0xE700 | ((v1&15) << 4) | (v2&15)
461 .word ((v3&15) << 12)
462 MRXBOPC \m4, 0x61, v1, v2, v3
464 .macro VMRHB vr1, vr2, vr3
465 VMRH \vr1, \vr2, \vr3, 0
467 .macro VMRHH vr1, vr2, vr3
468 VMRH \vr1, \vr2, \vr3, 1
470 .macro VMRHF vr1, vr2, vr3
471 VMRH \vr1, \vr2, \vr3, 2
473 .macro VMRHG vr1, vr2, vr3
474 VMRH \vr1, \vr2, \vr3, 3
477 /* VECTOR MERGE LOW */
478 .macro VMRL vr1, vr2, vr3, m4
482 .word 0xE700 | ((v1&15) << 4) | (v2&15)
483 .word ((v3&15) << 12)
484 MRXBOPC \m4, 0x60, v1, v2, v3
486 .macro VMRLB vr1, vr2, vr3
487 VMRL \vr1, \vr2, \vr3, 0
489 .macro VMRLH vr1, vr2, vr3
490 VMRL \vr1, \vr2, \vr3, 1
492 .macro VMRLF vr1, vr2, vr3
493 VMRL \vr1, \vr2, \vr3, 2
495 .macro VMRLG vr1, vr2, vr3
496 VMRL \vr1, \vr2, \vr3, 3
500 /* Vector integer instructions */
503 .macro VN vr1, vr2, vr3
507 .word 0xE700 | ((v1&15) << 4) | (v2&15)
508 .word ((v3&15) << 12)
509 MRXBOPC 0, 0x68, v1, v2, v3
512 /* VECTOR EXCLUSIVE OR */
513 .macro VX vr1, vr2, vr3
517 .word 0xE700 | ((v1&15) << 4) | (v2&15)
518 .word ((v3&15) << 12)
519 MRXBOPC 0, 0x6D, v1, v2, v3
522 /* VECTOR GALOIS FIELD MULTIPLY SUM */
523 .macro VGFM vr1, vr2, vr3, m4
527 .word 0xE700 | ((v1&15) << 4) | (v2&15)
528 .word ((v3&15) << 12)
529 MRXBOPC \m4, 0xB4, v1, v2, v3
531 .macro VGFMB vr1, vr2, vr3
532 VGFM \vr1, \vr2, \vr3, 0
534 .macro VGFMH vr1, vr2, vr3
535 VGFM \vr1, \vr2, \vr3, 1
537 .macro VGFMF vr1, vr2, vr3
538 VGFM \vr1, \vr2, \vr3, 2
540 .macro VGFMG vr1, vr2, vr3
541 VGFM \vr1, \vr2, \vr3, 3
544 /* VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE */
545 .macro VGFMA vr1, vr2, vr3, vr4, m5
550 .word 0xE700 | ((v1&15) << 4) | (v2&15)
551 .word ((v3&15) << 12) | (\m5 << 8)
552 MRXBOPC (v4&15), 0xBC, v1, v2, v3, v4
554 .macro VGFMAB vr1, vr2, vr3, vr4
555 VGFMA \vr1, \vr2, \vr3, \vr4, 0
557 .macro VGFMAH vr1, vr2, vr3, vr4
558 VGFMA \vr1, \vr2, \vr3, \vr4, 1
560 .macro VGFMAF vr1, vr2, vr3, vr4
561 VGFMA \vr1, \vr2, \vr3, \vr4, 2
563 .macro VGFMAG vr1, vr2, vr3, vr4
564 VGFMA \vr1, \vr2, \vr3, \vr4, 3
567 /* VECTOR SHIFT RIGHT LOGICAL BY BYTE */
568 .macro VSRLB vr1, vr2, vr3
572 .word 0xE700 | ((v1&15) << 4) | (v2&15)
573 .word ((v3&15) << 12)
574 MRXBOPC 0, 0x7D, v1, v2, v3
577 /* VECTOR REPLICATE IMMEDIATE */
578 .macro VREPI vr1, imm2, m3
580 .word 0xE700 | ((v1&15) << 4)
582 MRXBOPC \m3, 0x45, v1
584 .macro VREPIB vr1, imm2
587 .macro VREPIH vr1, imm2
590 .macro VREPIF vr1, imm2
593 .macro VREPIG vr1, imm2
598 .macro VA vr1, vr2, vr3, m4
602 .word 0xE700 | ((v1&15) << 4) | (v2&15)
603 .word ((v3&15) << 12)
604 MRXBOPC \m4, 0xF3, v1, v2, v3
606 .macro VAB vr1, vr2, vr3
607 VA \vr1, \vr2, \vr3, 0
609 .macro VAH vr1, vr2, vr3
610 VA \vr1, \vr2, \vr3, 1
612 .macro VAF vr1, vr2, vr3
613 VA \vr1, \vr2, \vr3, 2
615 .macro VAG vr1, vr2, vr3
616 VA \vr1, \vr2, \vr3, 3
618 .macro VAQ vr1, vr2, vr3
619 VA \vr1, \vr2, \vr3, 4
622 /* VECTOR ELEMENT SHIFT RIGHT ARITHMETIC */
623 .macro VESRAV vr1, vr2, vr3, m4
627 .word 0xE700 | ((v1&15) << 4) | (v2&15)
628 .word ((v3&15) << 12)
629 MRXBOPC \m4, 0x7A, v1, v2, v3
632 .macro VESRAVB vr1, vr2, vr3
633 VESRAV \vr1, \vr2, \vr3, 0
635 .macro VESRAVH vr1, vr2, vr3
636 VESRAV \vr1, \vr2, \vr3, 1
638 .macro VESRAVF vr1, vr2, vr3
639 VESRAV \vr1, \vr2, \vr3, 2
641 .macro VESRAVG vr1, vr2, vr3
642 VESRAV \vr1, \vr2, \vr3, 3
645 /* VECTOR ELEMENT ROTATE LEFT LOGICAL */
646 .macro VERLL vr1, vr3, disp, base="%r0", m4
650 .word 0xE700 | ((v1&15) << 4) | (v3&15)
651 .word (b2 << 12) | (\disp)
652 MRXBOPC \m4, 0x33, v1, v3
654 .macro VERLLB vr1, vr3, disp, base="%r0"
655 VERLL \vr1, \vr3, \disp, \base, 0
657 .macro VERLLH vr1, vr3, disp, base="%r0"
658 VERLL \vr1, \vr3, \disp, \base, 1
660 .macro VERLLF vr1, vr3, disp, base="%r0"
661 VERLL \vr1, \vr3, \disp, \base, 2
663 .macro VERLLG vr1, vr3, disp, base="%r0"
664 VERLL \vr1, \vr3, \disp, \base, 3
667 /* VECTOR SHIFT LEFT DOUBLE BY BYTE */
668 .macro VSLDB vr1, vr2, vr3, imm4
672 .word 0xE700 | ((v1&15) << 4) | (v2&15)
673 .word ((v3&15) << 12) | (\imm4)
674 MRXBOPC 0, 0x77, v1, v2, v3
677 #endif /* __ASSEMBLY__ */
678 #endif /* __ASM_S390_VX_INSN_H */