1 // SPDX-License-Identifier: GPL-2.0
2 /* BPF JIT compiler for RV64G
4 * Copyright(c) 2019 Björn Töpel <bjorn.topel@gmail.com>
9 #include <linux/filter.h>
10 #include <asm/cacheflush.h>
13 RV_REG_ZERO = 0, /* The constant value 0 */
14 RV_REG_RA = 1, /* Return address */
15 RV_REG_SP = 2, /* Stack pointer */
16 RV_REG_GP = 3, /* Global pointer */
17 RV_REG_TP = 4, /* Thread pointer */
18 RV_REG_T0 = 5, /* Temporaries */
22 RV_REG_S1 = 9, /* Saved registers */
23 RV_REG_A0 = 10, /* Function argument/return values */
24 RV_REG_A1 = 11, /* Function arguments */
31 RV_REG_S2 = 18, /* Saved registers */
41 RV_REG_T3 = 28, /* Temporaries */
47 #define RV_REG_TCC RV_REG_A6
48 #define RV_REG_TCC_SAVED RV_REG_S6 /* Store A6 in S6 if program do calls */
50 static const int regmap[] = {
51 [BPF_REG_0] = RV_REG_A5,
52 [BPF_REG_1] = RV_REG_A0,
53 [BPF_REG_2] = RV_REG_A1,
54 [BPF_REG_3] = RV_REG_A2,
55 [BPF_REG_4] = RV_REG_A3,
56 [BPF_REG_5] = RV_REG_A4,
57 [BPF_REG_6] = RV_REG_S1,
58 [BPF_REG_7] = RV_REG_S2,
59 [BPF_REG_8] = RV_REG_S3,
60 [BPF_REG_9] = RV_REG_S4,
61 [BPF_REG_FP] = RV_REG_S5,
62 [BPF_REG_AX] = RV_REG_T0,
66 RV_CTX_F_SEEN_TAIL_CALL = 0,
67 RV_CTX_F_SEEN_CALL = RV_REG_RA,
68 RV_CTX_F_SEEN_S1 = RV_REG_S1,
69 RV_CTX_F_SEEN_S2 = RV_REG_S2,
70 RV_CTX_F_SEEN_S3 = RV_REG_S3,
71 RV_CTX_F_SEEN_S4 = RV_REG_S4,
72 RV_CTX_F_SEEN_S5 = RV_REG_S5,
73 RV_CTX_F_SEEN_S6 = RV_REG_S6,
76 struct rv_jit_context {
77 struct bpf_prog *prog;
78 u32 *insns; /* RV insns */
81 int *offset; /* BPF to RV */
87 struct bpf_binary_header *header;
89 struct rv_jit_context ctx;
92 static u8 bpf_to_rv_reg(int bpf_reg, struct rv_jit_context *ctx)
94 u8 reg = regmap[bpf_reg];
97 case RV_CTX_F_SEEN_S1:
98 case RV_CTX_F_SEEN_S2:
99 case RV_CTX_F_SEEN_S3:
100 case RV_CTX_F_SEEN_S4:
101 case RV_CTX_F_SEEN_S5:
102 case RV_CTX_F_SEEN_S6:
103 __set_bit(reg, &ctx->flags);
108 static bool seen_reg(int reg, struct rv_jit_context *ctx)
111 case RV_CTX_F_SEEN_CALL:
112 case RV_CTX_F_SEEN_S1:
113 case RV_CTX_F_SEEN_S2:
114 case RV_CTX_F_SEEN_S3:
115 case RV_CTX_F_SEEN_S4:
116 case RV_CTX_F_SEEN_S5:
117 case RV_CTX_F_SEEN_S6:
118 return test_bit(reg, &ctx->flags);
123 static void mark_fp(struct rv_jit_context *ctx)
125 __set_bit(RV_CTX_F_SEEN_S5, &ctx->flags);
128 static void mark_call(struct rv_jit_context *ctx)
130 __set_bit(RV_CTX_F_SEEN_CALL, &ctx->flags);
133 static bool seen_call(struct rv_jit_context *ctx)
135 return test_bit(RV_CTX_F_SEEN_CALL, &ctx->flags);
138 static void mark_tail_call(struct rv_jit_context *ctx)
140 __set_bit(RV_CTX_F_SEEN_TAIL_CALL, &ctx->flags);
143 static bool seen_tail_call(struct rv_jit_context *ctx)
145 return test_bit(RV_CTX_F_SEEN_TAIL_CALL, &ctx->flags);
148 static u8 rv_tail_call_reg(struct rv_jit_context *ctx)
152 if (seen_call(ctx)) {
153 __set_bit(RV_CTX_F_SEEN_S6, &ctx->flags);
159 static void emit(const u32 insn, struct rv_jit_context *ctx)
162 ctx->insns[ctx->ninsns] = insn;
167 static u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd, u8 opcode)
169 return (funct7 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) |
173 static u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 funct3, u8 rd, u8 opcode)
175 return (imm11_0 << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) |
179 static u32 rv_s_insn(u16 imm11_0, u8 rs2, u8 rs1, u8 funct3, u8 opcode)
181 u8 imm11_5 = imm11_0 >> 5, imm4_0 = imm11_0 & 0x1f;
183 return (imm11_5 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) |
184 (imm4_0 << 7) | opcode;
187 static u32 rv_sb_insn(u16 imm12_1, u8 rs2, u8 rs1, u8 funct3, u8 opcode)
189 u8 imm12 = ((imm12_1 & 0x800) >> 5) | ((imm12_1 & 0x3f0) >> 4);
190 u8 imm4_1 = ((imm12_1 & 0xf) << 1) | ((imm12_1 & 0x400) >> 10);
192 return (imm12 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) |
193 (imm4_1 << 7) | opcode;
196 static u32 rv_u_insn(u32 imm31_12, u8 rd, u8 opcode)
198 return (imm31_12 << 12) | (rd << 7) | opcode;
201 static u32 rv_uj_insn(u32 imm20_1, u8 rd, u8 opcode)
205 imm = (imm20_1 & 0x80000) | ((imm20_1 & 0x3ff) << 9) |
206 ((imm20_1 & 0x400) >> 2) | ((imm20_1 & 0x7f800) >> 11);
208 return (imm << 12) | (rd << 7) | opcode;
211 static u32 rv_amo_insn(u8 funct5, u8 aq, u8 rl, u8 rs2, u8 rs1,
212 u8 funct3, u8 rd, u8 opcode)
214 u8 funct7 = (funct5 << 2) | (aq << 1) | rl;
216 return rv_r_insn(funct7, rs2, rs1, funct3, rd, opcode);
219 static u32 rv_addiw(u8 rd, u8 rs1, u16 imm11_0)
221 return rv_i_insn(imm11_0, rs1, 0, rd, 0x1b);
224 static u32 rv_addi(u8 rd, u8 rs1, u16 imm11_0)
226 return rv_i_insn(imm11_0, rs1, 0, rd, 0x13);
229 static u32 rv_addw(u8 rd, u8 rs1, u8 rs2)
231 return rv_r_insn(0, rs2, rs1, 0, rd, 0x3b);
234 static u32 rv_add(u8 rd, u8 rs1, u8 rs2)
236 return rv_r_insn(0, rs2, rs1, 0, rd, 0x33);
239 static u32 rv_subw(u8 rd, u8 rs1, u8 rs2)
241 return rv_r_insn(0x20, rs2, rs1, 0, rd, 0x3b);
244 static u32 rv_sub(u8 rd, u8 rs1, u8 rs2)
246 return rv_r_insn(0x20, rs2, rs1, 0, rd, 0x33);
249 static u32 rv_and(u8 rd, u8 rs1, u8 rs2)
251 return rv_r_insn(0, rs2, rs1, 7, rd, 0x33);
254 static u32 rv_or(u8 rd, u8 rs1, u8 rs2)
256 return rv_r_insn(0, rs2, rs1, 6, rd, 0x33);
259 static u32 rv_xor(u8 rd, u8 rs1, u8 rs2)
261 return rv_r_insn(0, rs2, rs1, 4, rd, 0x33);
264 static u32 rv_mulw(u8 rd, u8 rs1, u8 rs2)
266 return rv_r_insn(1, rs2, rs1, 0, rd, 0x3b);
269 static u32 rv_mul(u8 rd, u8 rs1, u8 rs2)
271 return rv_r_insn(1, rs2, rs1, 0, rd, 0x33);
274 static u32 rv_divuw(u8 rd, u8 rs1, u8 rs2)
276 return rv_r_insn(1, rs2, rs1, 5, rd, 0x3b);
279 static u32 rv_divu(u8 rd, u8 rs1, u8 rs2)
281 return rv_r_insn(1, rs2, rs1, 5, rd, 0x33);
284 static u32 rv_remuw(u8 rd, u8 rs1, u8 rs2)
286 return rv_r_insn(1, rs2, rs1, 7, rd, 0x3b);
289 static u32 rv_remu(u8 rd, u8 rs1, u8 rs2)
291 return rv_r_insn(1, rs2, rs1, 7, rd, 0x33);
294 static u32 rv_sllw(u8 rd, u8 rs1, u8 rs2)
296 return rv_r_insn(0, rs2, rs1, 1, rd, 0x3b);
299 static u32 rv_sll(u8 rd, u8 rs1, u8 rs2)
301 return rv_r_insn(0, rs2, rs1, 1, rd, 0x33);
304 static u32 rv_srlw(u8 rd, u8 rs1, u8 rs2)
306 return rv_r_insn(0, rs2, rs1, 5, rd, 0x3b);
309 static u32 rv_srl(u8 rd, u8 rs1, u8 rs2)
311 return rv_r_insn(0, rs2, rs1, 5, rd, 0x33);
314 static u32 rv_sraw(u8 rd, u8 rs1, u8 rs2)
316 return rv_r_insn(0x20, rs2, rs1, 5, rd, 0x3b);
319 static u32 rv_sra(u8 rd, u8 rs1, u8 rs2)
321 return rv_r_insn(0x20, rs2, rs1, 5, rd, 0x33);
324 static u32 rv_lui(u8 rd, u32 imm31_12)
326 return rv_u_insn(imm31_12, rd, 0x37);
329 static u32 rv_slli(u8 rd, u8 rs1, u16 imm11_0)
331 return rv_i_insn(imm11_0, rs1, 1, rd, 0x13);
334 static u32 rv_andi(u8 rd, u8 rs1, u16 imm11_0)
336 return rv_i_insn(imm11_0, rs1, 7, rd, 0x13);
339 static u32 rv_ori(u8 rd, u8 rs1, u16 imm11_0)
341 return rv_i_insn(imm11_0, rs1, 6, rd, 0x13);
344 static u32 rv_xori(u8 rd, u8 rs1, u16 imm11_0)
346 return rv_i_insn(imm11_0, rs1, 4, rd, 0x13);
349 static u32 rv_slliw(u8 rd, u8 rs1, u16 imm11_0)
351 return rv_i_insn(imm11_0, rs1, 1, rd, 0x1b);
354 static u32 rv_srliw(u8 rd, u8 rs1, u16 imm11_0)
356 return rv_i_insn(imm11_0, rs1, 5, rd, 0x1b);
359 static u32 rv_srli(u8 rd, u8 rs1, u16 imm11_0)
361 return rv_i_insn(imm11_0, rs1, 5, rd, 0x13);
364 static u32 rv_sraiw(u8 rd, u8 rs1, u16 imm11_0)
366 return rv_i_insn(0x400 | imm11_0, rs1, 5, rd, 0x1b);
369 static u32 rv_srai(u8 rd, u8 rs1, u16 imm11_0)
371 return rv_i_insn(0x400 | imm11_0, rs1, 5, rd, 0x13);
374 static u32 rv_jal(u8 rd, u32 imm20_1)
376 return rv_uj_insn(imm20_1, rd, 0x6f);
379 static u32 rv_jalr(u8 rd, u8 rs1, u16 imm11_0)
381 return rv_i_insn(imm11_0, rs1, 0, rd, 0x67);
384 static u32 rv_beq(u8 rs1, u8 rs2, u16 imm12_1)
386 return rv_sb_insn(imm12_1, rs2, rs1, 0, 0x63);
389 static u32 rv_bltu(u8 rs1, u8 rs2, u16 imm12_1)
391 return rv_sb_insn(imm12_1, rs2, rs1, 6, 0x63);
394 static u32 rv_bgeu(u8 rs1, u8 rs2, u16 imm12_1)
396 return rv_sb_insn(imm12_1, rs2, rs1, 7, 0x63);
399 static u32 rv_bne(u8 rs1, u8 rs2, u16 imm12_1)
401 return rv_sb_insn(imm12_1, rs2, rs1, 1, 0x63);
404 static u32 rv_blt(u8 rs1, u8 rs2, u16 imm12_1)
406 return rv_sb_insn(imm12_1, rs2, rs1, 4, 0x63);
409 static u32 rv_bge(u8 rs1, u8 rs2, u16 imm12_1)
411 return rv_sb_insn(imm12_1, rs2, rs1, 5, 0x63);
414 static u32 rv_sb(u8 rs1, u16 imm11_0, u8 rs2)
416 return rv_s_insn(imm11_0, rs2, rs1, 0, 0x23);
419 static u32 rv_sh(u8 rs1, u16 imm11_0, u8 rs2)
421 return rv_s_insn(imm11_0, rs2, rs1, 1, 0x23);
424 static u32 rv_sw(u8 rs1, u16 imm11_0, u8 rs2)
426 return rv_s_insn(imm11_0, rs2, rs1, 2, 0x23);
429 static u32 rv_sd(u8 rs1, u16 imm11_0, u8 rs2)
431 return rv_s_insn(imm11_0, rs2, rs1, 3, 0x23);
434 static u32 rv_lbu(u8 rd, u16 imm11_0, u8 rs1)
436 return rv_i_insn(imm11_0, rs1, 4, rd, 0x03);
439 static u32 rv_lhu(u8 rd, u16 imm11_0, u8 rs1)
441 return rv_i_insn(imm11_0, rs1, 5, rd, 0x03);
444 static u32 rv_lwu(u8 rd, u16 imm11_0, u8 rs1)
446 return rv_i_insn(imm11_0, rs1, 6, rd, 0x03);
449 static u32 rv_ld(u8 rd, u16 imm11_0, u8 rs1)
451 return rv_i_insn(imm11_0, rs1, 3, rd, 0x03);
454 static u32 rv_amoadd_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
456 return rv_amo_insn(0, aq, rl, rs2, rs1, 2, rd, 0x2f);
459 static u32 rv_amoadd_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
461 return rv_amo_insn(0, aq, rl, rs2, rs1, 3, rd, 0x2f);
464 static u32 rv_auipc(u8 rd, u32 imm31_12)
466 return rv_u_insn(imm31_12, rd, 0x17);
469 static bool is_12b_int(s64 val)
471 return -(1 << 11) <= val && val < (1 << 11);
474 static bool is_13b_int(s64 val)
476 return -(1 << 12) <= val && val < (1 << 12);
479 static bool is_21b_int(s64 val)
481 return -(1L << 20) <= val && val < (1L << 20);
484 static bool is_32b_int(s64 val)
486 return -(1L << 31) <= val && val < (1L << 31);
489 static int is_12b_check(int off, int insn)
491 if (!is_12b_int(off)) {
492 pr_err("bpf-jit: insn=%d 12b < offset=%d not supported yet!\n",
499 static void emit_imm(u8 rd, s64 val, struct rv_jit_context *ctx)
501 /* Note that the immediate from the add is sign-extended,
502 * which means that we need to compensate this by adding 2^12,
503 * when the 12th bit is set. A simpler way of doing this, and
504 * getting rid of the check, is to just add 2**11 before the
505 * shift. The "Loading a 32-Bit constant" example from the
506 * "Computer Organization and Design, RISC-V edition" book by
507 * Patterson/Hennessy highlights this fact.
509 * This also means that we need to process LSB to MSB.
511 s64 upper = (val + (1 << 11)) >> 12, lower = val & 0xfff;
514 if (is_32b_int(val)) {
516 emit(rv_lui(rd, upper), ctx);
519 emit(rv_addi(rd, RV_REG_ZERO, lower), ctx);
523 emit(rv_addiw(rd, rd, lower), ctx);
527 shift = __ffs(upper);
531 emit_imm(rd, upper, ctx);
533 emit(rv_slli(rd, rd, shift), ctx);
535 emit(rv_addi(rd, rd, lower), ctx);
538 static int rv_offset(int insn, int off, struct rv_jit_context *ctx)
542 off++; /* BPF branch is from PC+1, RV is from PC */
543 from = (insn > 0) ? ctx->offset[insn - 1] : 0;
544 to = (insn + off > 0) ? ctx->offset[insn + off - 1] : 0;
545 return (to - from) << 2;
548 static int epilogue_offset(struct rv_jit_context *ctx)
550 int to = ctx->epilogue_offset, from = ctx->ninsns;
552 return (to - from) << 2;
555 static void __build_epilogue(u8 reg, struct rv_jit_context *ctx)
557 int stack_adjust = ctx->stack_size, store_offset = stack_adjust - 8;
559 if (seen_reg(RV_REG_RA, ctx)) {
560 emit(rv_ld(RV_REG_RA, store_offset, RV_REG_SP), ctx);
563 emit(rv_ld(RV_REG_FP, store_offset, RV_REG_SP), ctx);
565 if (seen_reg(RV_REG_S1, ctx)) {
566 emit(rv_ld(RV_REG_S1, store_offset, RV_REG_SP), ctx);
569 if (seen_reg(RV_REG_S2, ctx)) {
570 emit(rv_ld(RV_REG_S2, store_offset, RV_REG_SP), ctx);
573 if (seen_reg(RV_REG_S3, ctx)) {
574 emit(rv_ld(RV_REG_S3, store_offset, RV_REG_SP), ctx);
577 if (seen_reg(RV_REG_S4, ctx)) {
578 emit(rv_ld(RV_REG_S4, store_offset, RV_REG_SP), ctx);
581 if (seen_reg(RV_REG_S5, ctx)) {
582 emit(rv_ld(RV_REG_S5, store_offset, RV_REG_SP), ctx);
585 if (seen_reg(RV_REG_S6, ctx)) {
586 emit(rv_ld(RV_REG_S6, store_offset, RV_REG_SP), ctx);
590 emit(rv_addi(RV_REG_SP, RV_REG_SP, stack_adjust), ctx);
591 /* Set return value. */
592 if (reg == RV_REG_RA)
593 emit(rv_addi(RV_REG_A0, RV_REG_A5, 0), ctx);
594 emit(rv_jalr(RV_REG_ZERO, reg, 0), ctx);
597 /* return -1 or inverted cond */
598 static int invert_bpf_cond(u8 cond)
625 static void emit_bcc(u8 cond, u8 rd, u8 rs, int rvoff,
626 struct rv_jit_context *ctx)
630 emit(rv_beq(rd, rs, rvoff >> 1), ctx);
633 emit(rv_bltu(rs, rd, rvoff >> 1), ctx);
636 emit(rv_bltu(rd, rs, rvoff >> 1), ctx);
639 emit(rv_bgeu(rd, rs, rvoff >> 1), ctx);
642 emit(rv_bgeu(rs, rd, rvoff >> 1), ctx);
645 emit(rv_bne(rd, rs, rvoff >> 1), ctx);
648 emit(rv_blt(rs, rd, rvoff >> 1), ctx);
651 emit(rv_blt(rd, rs, rvoff >> 1), ctx);
654 emit(rv_bge(rd, rs, rvoff >> 1), ctx);
657 emit(rv_bge(rs, rd, rvoff >> 1), ctx);
661 static void emit_branch(u8 cond, u8 rd, u8 rs, int rvoff,
662 struct rv_jit_context *ctx)
666 if (is_13b_int(rvoff)) {
667 emit_bcc(cond, rd, rs, rvoff, ctx);
682 cond = invert_bpf_cond(cond);
683 if (is_21b_int(rvoff)) {
684 emit_bcc(cond, rd, rs, 8, ctx);
685 emit(rv_jal(RV_REG_ZERO, rvoff >> 1), ctx);
689 /* 32b No need for an additional rvoff adjustment, since we
690 * get that from the auipc at PC', where PC = PC' + 4.
692 upper = (rvoff + (1 << 11)) >> 12;
693 lower = rvoff & 0xfff;
695 emit_bcc(cond, rd, rs, 12, ctx);
696 emit(rv_auipc(RV_REG_T1, upper), ctx);
697 emit(rv_jalr(RV_REG_ZERO, RV_REG_T1, lower), ctx);
700 static void emit_zext_32(u8 reg, struct rv_jit_context *ctx)
702 emit(rv_slli(reg, reg, 32), ctx);
703 emit(rv_srli(reg, reg, 32), ctx);
706 static int emit_bpf_tail_call(int insn, struct rv_jit_context *ctx)
708 int tc_ninsn, off, start_insn = ctx->ninsns;
709 u8 tcc = rv_tail_call_reg(ctx);
715 * if (index >= array->map.max_entries)
718 tc_ninsn = insn ? ctx->offset[insn] - ctx->offset[insn - 1] :
720 emit_zext_32(RV_REG_A2, ctx);
722 off = offsetof(struct bpf_array, map.max_entries);
723 if (is_12b_check(off, insn))
725 emit(rv_lwu(RV_REG_T1, off, RV_REG_A1), ctx);
726 off = (tc_ninsn - (ctx->ninsns - start_insn)) << 2;
727 emit_branch(BPF_JGE, RV_REG_A2, RV_REG_T1, off, ctx);
732 emit(rv_addi(RV_REG_T1, tcc, -1), ctx);
733 off = (tc_ninsn - (ctx->ninsns - start_insn)) << 2;
734 emit_branch(BPF_JSLT, RV_REG_T1, RV_REG_ZERO, off, ctx);
736 /* prog = array->ptrs[index];
740 emit(rv_slli(RV_REG_T2, RV_REG_A2, 3), ctx);
741 emit(rv_add(RV_REG_T2, RV_REG_T2, RV_REG_A1), ctx);
742 off = offsetof(struct bpf_array, ptrs);
743 if (is_12b_check(off, insn))
745 emit(rv_ld(RV_REG_T2, off, RV_REG_T2), ctx);
746 off = (tc_ninsn - (ctx->ninsns - start_insn)) << 2;
747 emit_branch(BPF_JEQ, RV_REG_T2, RV_REG_ZERO, off, ctx);
749 /* goto *(prog->bpf_func + 4); */
750 off = offsetof(struct bpf_prog, bpf_func);
751 if (is_12b_check(off, insn))
753 emit(rv_ld(RV_REG_T3, off, RV_REG_T2), ctx);
754 emit(rv_addi(RV_REG_T3, RV_REG_T3, 4), ctx);
755 emit(rv_addi(RV_REG_TCC, RV_REG_T1, 0), ctx);
756 __build_epilogue(RV_REG_T3, ctx);
760 static void init_regs(u8 *rd, u8 *rs, const struct bpf_insn *insn,
761 struct rv_jit_context *ctx)
763 u8 code = insn->code;
766 case BPF_JMP | BPF_JA:
767 case BPF_JMP | BPF_CALL:
768 case BPF_JMP | BPF_EXIT:
769 case BPF_JMP | BPF_TAIL_CALL:
772 *rd = bpf_to_rv_reg(insn->dst_reg, ctx);
775 if (code & (BPF_ALU | BPF_X) || code & (BPF_ALU64 | BPF_X) ||
776 code & (BPF_JMP | BPF_X) || code & (BPF_JMP32 | BPF_X) ||
777 code & BPF_LDX || code & BPF_STX)
778 *rs = bpf_to_rv_reg(insn->src_reg, ctx);
781 static void emit_zext_32_rd_rs(u8 *rd, u8 *rs, struct rv_jit_context *ctx)
783 emit(rv_addi(RV_REG_T2, *rd, 0), ctx);
784 emit_zext_32(RV_REG_T2, ctx);
785 emit(rv_addi(RV_REG_T1, *rs, 0), ctx);
786 emit_zext_32(RV_REG_T1, ctx);
791 static void emit_sext_32_rd_rs(u8 *rd, u8 *rs, struct rv_jit_context *ctx)
793 emit(rv_addiw(RV_REG_T2, *rd, 0), ctx);
794 emit(rv_addiw(RV_REG_T1, *rs, 0), ctx);
799 static void emit_zext_32_rd_t1(u8 *rd, struct rv_jit_context *ctx)
801 emit(rv_addi(RV_REG_T2, *rd, 0), ctx);
802 emit_zext_32(RV_REG_T2, ctx);
803 emit_zext_32(RV_REG_T1, ctx);
807 static void emit_sext_32_rd(u8 *rd, struct rv_jit_context *ctx)
809 emit(rv_addiw(RV_REG_T2, *rd, 0), ctx);
813 static void emit_jump_and_link(u8 rd, int rvoff, struct rv_jit_context *ctx)
817 if (is_21b_int(rvoff)) {
818 emit(rv_jal(rd, rvoff >> 1), ctx);
822 upper = (rvoff + (1 << 11)) >> 12;
823 lower = rvoff & 0xfff;
824 emit(rv_auipc(RV_REG_T1, upper), ctx);
825 emit(rv_jalr(rd, RV_REG_T1, lower), ctx);
828 static bool is_signed_bpf_cond(u8 cond)
830 return cond == BPF_JSGT || cond == BPF_JSLT ||
831 cond == BPF_JSGE || cond == BPF_JSLE;
834 static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
837 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64 ||
838 BPF_CLASS(insn->code) == BPF_JMP;
839 int s, e, rvoff, i = insn - ctx->prog->insnsi;
840 struct bpf_prog_aux *aux = ctx->prog->aux;
841 u8 rd = -1, rs = -1, code = insn->code;
845 init_regs(&rd, &rs, insn, ctx);
849 case BPF_ALU | BPF_MOV | BPF_X:
850 case BPF_ALU64 | BPF_MOV | BPF_X:
852 /* Special mov32 for zext */
853 emit_zext_32(rd, ctx);
856 emit(is64 ? rv_addi(rd, rs, 0) : rv_addiw(rd, rs, 0), ctx);
857 if (!is64 && !aux->verifier_zext)
858 emit_zext_32(rd, ctx);
861 /* dst = dst OP src */
862 case BPF_ALU | BPF_ADD | BPF_X:
863 case BPF_ALU64 | BPF_ADD | BPF_X:
864 emit(is64 ? rv_add(rd, rd, rs) : rv_addw(rd, rd, rs), ctx);
865 if (!is64 && !aux->verifier_zext)
866 emit_zext_32(rd, ctx);
868 case BPF_ALU | BPF_SUB | BPF_X:
869 case BPF_ALU64 | BPF_SUB | BPF_X:
870 emit(is64 ? rv_sub(rd, rd, rs) : rv_subw(rd, rd, rs), ctx);
871 if (!is64 && !aux->verifier_zext)
872 emit_zext_32(rd, ctx);
874 case BPF_ALU | BPF_AND | BPF_X:
875 case BPF_ALU64 | BPF_AND | BPF_X:
876 emit(rv_and(rd, rd, rs), ctx);
877 if (!is64 && !aux->verifier_zext)
878 emit_zext_32(rd, ctx);
880 case BPF_ALU | BPF_OR | BPF_X:
881 case BPF_ALU64 | BPF_OR | BPF_X:
882 emit(rv_or(rd, rd, rs), ctx);
883 if (!is64 && !aux->verifier_zext)
884 emit_zext_32(rd, ctx);
886 case BPF_ALU | BPF_XOR | BPF_X:
887 case BPF_ALU64 | BPF_XOR | BPF_X:
888 emit(rv_xor(rd, rd, rs), ctx);
889 if (!is64 && !aux->verifier_zext)
890 emit_zext_32(rd, ctx);
892 case BPF_ALU | BPF_MUL | BPF_X:
893 case BPF_ALU64 | BPF_MUL | BPF_X:
894 emit(is64 ? rv_mul(rd, rd, rs) : rv_mulw(rd, rd, rs), ctx);
895 if (!is64 && !aux->verifier_zext)
896 emit_zext_32(rd, ctx);
898 case BPF_ALU | BPF_DIV | BPF_X:
899 case BPF_ALU64 | BPF_DIV | BPF_X:
900 emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx);
901 if (!is64 && !aux->verifier_zext)
902 emit_zext_32(rd, ctx);
904 case BPF_ALU | BPF_MOD | BPF_X:
905 case BPF_ALU64 | BPF_MOD | BPF_X:
906 emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx);
907 if (!is64 && !aux->verifier_zext)
908 emit_zext_32(rd, ctx);
910 case BPF_ALU | BPF_LSH | BPF_X:
911 case BPF_ALU64 | BPF_LSH | BPF_X:
912 emit(is64 ? rv_sll(rd, rd, rs) : rv_sllw(rd, rd, rs), ctx);
914 emit_zext_32(rd, ctx);
916 case BPF_ALU | BPF_RSH | BPF_X:
917 case BPF_ALU64 | BPF_RSH | BPF_X:
918 emit(is64 ? rv_srl(rd, rd, rs) : rv_srlw(rd, rd, rs), ctx);
919 if (!is64 && !aux->verifier_zext)
920 emit_zext_32(rd, ctx);
922 case BPF_ALU | BPF_ARSH | BPF_X:
923 case BPF_ALU64 | BPF_ARSH | BPF_X:
924 emit(is64 ? rv_sra(rd, rd, rs) : rv_sraw(rd, rd, rs), ctx);
925 if (!is64 && !aux->verifier_zext)
926 emit_zext_32(rd, ctx);
930 case BPF_ALU | BPF_NEG:
931 case BPF_ALU64 | BPF_NEG:
932 emit(is64 ? rv_sub(rd, RV_REG_ZERO, rd) :
933 rv_subw(rd, RV_REG_ZERO, rd), ctx);
934 if (!is64 && !aux->verifier_zext)
935 emit_zext_32(rd, ctx);
938 /* dst = BSWAP##imm(dst) */
939 case BPF_ALU | BPF_END | BPF_FROM_LE:
941 int shift = 64 - imm;
943 emit(rv_slli(rd, rd, shift), ctx);
944 emit(rv_srli(rd, rd, shift), ctx);
947 case BPF_ALU | BPF_END | BPF_FROM_BE:
948 emit(rv_addi(RV_REG_T2, RV_REG_ZERO, 0), ctx);
950 emit(rv_andi(RV_REG_T1, rd, 0xff), ctx);
951 emit(rv_add(RV_REG_T2, RV_REG_T2, RV_REG_T1), ctx);
952 emit(rv_slli(RV_REG_T2, RV_REG_T2, 8), ctx);
953 emit(rv_srli(rd, rd, 8), ctx);
957 emit(rv_andi(RV_REG_T1, rd, 0xff), ctx);
958 emit(rv_add(RV_REG_T2, RV_REG_T2, RV_REG_T1), ctx);
959 emit(rv_slli(RV_REG_T2, RV_REG_T2, 8), ctx);
960 emit(rv_srli(rd, rd, 8), ctx);
962 emit(rv_andi(RV_REG_T1, rd, 0xff), ctx);
963 emit(rv_add(RV_REG_T2, RV_REG_T2, RV_REG_T1), ctx);
964 emit(rv_slli(RV_REG_T2, RV_REG_T2, 8), ctx);
965 emit(rv_srli(rd, rd, 8), ctx);
969 emit(rv_andi(RV_REG_T1, rd, 0xff), ctx);
970 emit(rv_add(RV_REG_T2, RV_REG_T2, RV_REG_T1), ctx);
971 emit(rv_slli(RV_REG_T2, RV_REG_T2, 8), ctx);
972 emit(rv_srli(rd, rd, 8), ctx);
974 emit(rv_andi(RV_REG_T1, rd, 0xff), ctx);
975 emit(rv_add(RV_REG_T2, RV_REG_T2, RV_REG_T1), ctx);
976 emit(rv_slli(RV_REG_T2, RV_REG_T2, 8), ctx);
977 emit(rv_srli(rd, rd, 8), ctx);
979 emit(rv_andi(RV_REG_T1, rd, 0xff), ctx);
980 emit(rv_add(RV_REG_T2, RV_REG_T2, RV_REG_T1), ctx);
981 emit(rv_slli(RV_REG_T2, RV_REG_T2, 8), ctx);
982 emit(rv_srli(rd, rd, 8), ctx);
984 emit(rv_andi(RV_REG_T1, rd, 0xff), ctx);
985 emit(rv_add(RV_REG_T2, RV_REG_T2, RV_REG_T1), ctx);
986 emit(rv_slli(RV_REG_T2, RV_REG_T2, 8), ctx);
987 emit(rv_srli(rd, rd, 8), ctx);
989 emit(rv_andi(RV_REG_T1, rd, 0xff), ctx);
990 emit(rv_add(RV_REG_T2, RV_REG_T2, RV_REG_T1), ctx);
992 emit(rv_addi(rd, RV_REG_T2, 0), ctx);
996 case BPF_ALU | BPF_MOV | BPF_K:
997 case BPF_ALU64 | BPF_MOV | BPF_K:
998 emit_imm(rd, imm, ctx);
999 if (!is64 && !aux->verifier_zext)
1000 emit_zext_32(rd, ctx);
1003 /* dst = dst OP imm */
1004 case BPF_ALU | BPF_ADD | BPF_K:
1005 case BPF_ALU64 | BPF_ADD | BPF_K:
1006 if (is_12b_int(imm)) {
1007 emit(is64 ? rv_addi(rd, rd, imm) :
1008 rv_addiw(rd, rd, imm), ctx);
1010 emit_imm(RV_REG_T1, imm, ctx);
1011 emit(is64 ? rv_add(rd, rd, RV_REG_T1) :
1012 rv_addw(rd, rd, RV_REG_T1), ctx);
1014 if (!is64 && !aux->verifier_zext)
1015 emit_zext_32(rd, ctx);
1017 case BPF_ALU | BPF_SUB | BPF_K:
1018 case BPF_ALU64 | BPF_SUB | BPF_K:
1019 if (is_12b_int(-imm)) {
1020 emit(is64 ? rv_addi(rd, rd, -imm) :
1021 rv_addiw(rd, rd, -imm), ctx);
1023 emit_imm(RV_REG_T1, imm, ctx);
1024 emit(is64 ? rv_sub(rd, rd, RV_REG_T1) :
1025 rv_subw(rd, rd, RV_REG_T1), ctx);
1027 if (!is64 && !aux->verifier_zext)
1028 emit_zext_32(rd, ctx);
1030 case BPF_ALU | BPF_AND | BPF_K:
1031 case BPF_ALU64 | BPF_AND | BPF_K:
1032 if (is_12b_int(imm)) {
1033 emit(rv_andi(rd, rd, imm), ctx);
1035 emit_imm(RV_REG_T1, imm, ctx);
1036 emit(rv_and(rd, rd, RV_REG_T1), ctx);
1038 if (!is64 && !aux->verifier_zext)
1039 emit_zext_32(rd, ctx);
1041 case BPF_ALU | BPF_OR | BPF_K:
1042 case BPF_ALU64 | BPF_OR | BPF_K:
1043 if (is_12b_int(imm)) {
1044 emit(rv_ori(rd, rd, imm), ctx);
1046 emit_imm(RV_REG_T1, imm, ctx);
1047 emit(rv_or(rd, rd, RV_REG_T1), ctx);
1049 if (!is64 && !aux->verifier_zext)
1050 emit_zext_32(rd, ctx);
1052 case BPF_ALU | BPF_XOR | BPF_K:
1053 case BPF_ALU64 | BPF_XOR | BPF_K:
1054 if (is_12b_int(imm)) {
1055 emit(rv_xori(rd, rd, imm), ctx);
1057 emit_imm(RV_REG_T1, imm, ctx);
1058 emit(rv_xor(rd, rd, RV_REG_T1), ctx);
1060 if (!is64 && !aux->verifier_zext)
1061 emit_zext_32(rd, ctx);
1063 case BPF_ALU | BPF_MUL | BPF_K:
1064 case BPF_ALU64 | BPF_MUL | BPF_K:
1065 emit_imm(RV_REG_T1, imm, ctx);
1066 emit(is64 ? rv_mul(rd, rd, RV_REG_T1) :
1067 rv_mulw(rd, rd, RV_REG_T1), ctx);
1068 if (!is64 && !aux->verifier_zext)
1069 emit_zext_32(rd, ctx);
1071 case BPF_ALU | BPF_DIV | BPF_K:
1072 case BPF_ALU64 | BPF_DIV | BPF_K:
1073 emit_imm(RV_REG_T1, imm, ctx);
1074 emit(is64 ? rv_divu(rd, rd, RV_REG_T1) :
1075 rv_divuw(rd, rd, RV_REG_T1), ctx);
1076 if (!is64 && !aux->verifier_zext)
1077 emit_zext_32(rd, ctx);
1079 case BPF_ALU | BPF_MOD | BPF_K:
1080 case BPF_ALU64 | BPF_MOD | BPF_K:
1081 emit_imm(RV_REG_T1, imm, ctx);
1082 emit(is64 ? rv_remu(rd, rd, RV_REG_T1) :
1083 rv_remuw(rd, rd, RV_REG_T1), ctx);
1084 if (!is64 && !aux->verifier_zext)
1085 emit_zext_32(rd, ctx);
1087 case BPF_ALU | BPF_LSH | BPF_K:
1088 case BPF_ALU64 | BPF_LSH | BPF_K:
1089 emit(is64 ? rv_slli(rd, rd, imm) : rv_slliw(rd, rd, imm), ctx);
1091 emit_zext_32(rd, ctx);
1093 case BPF_ALU | BPF_RSH | BPF_K:
1094 case BPF_ALU64 | BPF_RSH | BPF_K:
1095 emit(is64 ? rv_srli(rd, rd, imm) : rv_srliw(rd, rd, imm), ctx);
1097 emit_zext_32(rd, ctx);
1099 case BPF_ALU | BPF_ARSH | BPF_K:
1100 case BPF_ALU64 | BPF_ARSH | BPF_K:
1101 emit(is64 ? rv_srai(rd, rd, imm) : rv_sraiw(rd, rd, imm), ctx);
1103 emit_zext_32(rd, ctx);
1107 case BPF_JMP | BPF_JA:
1108 rvoff = rv_offset(i, off, ctx);
1109 emit_jump_and_link(RV_REG_ZERO, rvoff, ctx);
1112 /* IF (dst COND src) JUMP off */
1113 case BPF_JMP | BPF_JEQ | BPF_X:
1114 case BPF_JMP32 | BPF_JEQ | BPF_X:
1115 case BPF_JMP | BPF_JGT | BPF_X:
1116 case BPF_JMP32 | BPF_JGT | BPF_X:
1117 case BPF_JMP | BPF_JLT | BPF_X:
1118 case BPF_JMP32 | BPF_JLT | BPF_X:
1119 case BPF_JMP | BPF_JGE | BPF_X:
1120 case BPF_JMP32 | BPF_JGE | BPF_X:
1121 case BPF_JMP | BPF_JLE | BPF_X:
1122 case BPF_JMP32 | BPF_JLE | BPF_X:
1123 case BPF_JMP | BPF_JNE | BPF_X:
1124 case BPF_JMP32 | BPF_JNE | BPF_X:
1125 case BPF_JMP | BPF_JSGT | BPF_X:
1126 case BPF_JMP32 | BPF_JSGT | BPF_X:
1127 case BPF_JMP | BPF_JSLT | BPF_X:
1128 case BPF_JMP32 | BPF_JSLT | BPF_X:
1129 case BPF_JMP | BPF_JSGE | BPF_X:
1130 case BPF_JMP32 | BPF_JSGE | BPF_X:
1131 case BPF_JMP | BPF_JSLE | BPF_X:
1132 case BPF_JMP32 | BPF_JSLE | BPF_X:
1133 case BPF_JMP | BPF_JSET | BPF_X:
1134 case BPF_JMP32 | BPF_JSET | BPF_X:
1135 rvoff = rv_offset(i, off, ctx);
1138 if (is_signed_bpf_cond(BPF_OP(code)))
1139 emit_sext_32_rd_rs(&rd, &rs, ctx);
1141 emit_zext_32_rd_rs(&rd, &rs, ctx);
1144 /* Adjust for extra insns */
1145 rvoff -= (e - s) << 2;
1148 if (BPF_OP(code) == BPF_JSET) {
1149 /* Adjust for and */
1151 emit(rv_and(RV_REG_T1, rd, rs), ctx);
1152 emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff,
1155 emit_branch(BPF_OP(code), rd, rs, rvoff, ctx);
1159 /* IF (dst COND imm) JUMP off */
1160 case BPF_JMP | BPF_JEQ | BPF_K:
1161 case BPF_JMP32 | BPF_JEQ | BPF_K:
1162 case BPF_JMP | BPF_JGT | BPF_K:
1163 case BPF_JMP32 | BPF_JGT | BPF_K:
1164 case BPF_JMP | BPF_JLT | BPF_K:
1165 case BPF_JMP32 | BPF_JLT | BPF_K:
1166 case BPF_JMP | BPF_JGE | BPF_K:
1167 case BPF_JMP32 | BPF_JGE | BPF_K:
1168 case BPF_JMP | BPF_JLE | BPF_K:
1169 case BPF_JMP32 | BPF_JLE | BPF_K:
1170 case BPF_JMP | BPF_JNE | BPF_K:
1171 case BPF_JMP32 | BPF_JNE | BPF_K:
1172 case BPF_JMP | BPF_JSGT | BPF_K:
1173 case BPF_JMP32 | BPF_JSGT | BPF_K:
1174 case BPF_JMP | BPF_JSLT | BPF_K:
1175 case BPF_JMP32 | BPF_JSLT | BPF_K:
1176 case BPF_JMP | BPF_JSGE | BPF_K:
1177 case BPF_JMP32 | BPF_JSGE | BPF_K:
1178 case BPF_JMP | BPF_JSLE | BPF_K:
1179 case BPF_JMP32 | BPF_JSLE | BPF_K:
1180 case BPF_JMP | BPF_JSET | BPF_K:
1181 case BPF_JMP32 | BPF_JSET | BPF_K:
1182 rvoff = rv_offset(i, off, ctx);
1184 emit_imm(RV_REG_T1, imm, ctx);
1186 if (is_signed_bpf_cond(BPF_OP(code)))
1187 emit_sext_32_rd(&rd, ctx);
1189 emit_zext_32_rd_t1(&rd, ctx);
1193 /* Adjust for extra insns */
1194 rvoff -= (e - s) << 2;
1196 if (BPF_OP(code) == BPF_JSET) {
1197 /* Adjust for and */
1199 emit(rv_and(RV_REG_T1, rd, RV_REG_T1), ctx);
1200 emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff,
1203 emit_branch(BPF_OP(code), rd, RV_REG_T1, rvoff, ctx);
1208 case BPF_JMP | BPF_CALL:
1215 ret = bpf_jit_get_func_addr(ctx->prog, insn, extra_pass, &addr,
1220 emit_imm(RV_REG_T1, addr, ctx);
1223 emit_imm(RV_REG_T1, addr, ctx);
1224 for (i = ctx->ninsns - i; i < 8; i++) {
1226 emit(rv_addi(RV_REG_ZERO, RV_REG_ZERO, 0),
1230 emit(rv_jalr(RV_REG_RA, RV_REG_T1, 0), ctx);
1231 rd = bpf_to_rv_reg(BPF_REG_0, ctx);
1232 emit(rv_addi(rd, RV_REG_A0, 0), ctx);
1236 case BPF_JMP | BPF_TAIL_CALL:
1237 if (emit_bpf_tail_call(i, ctx))
1241 /* function return */
1242 case BPF_JMP | BPF_EXIT:
1243 if (i == ctx->prog->len - 1)
1246 rvoff = epilogue_offset(ctx);
1247 emit_jump_and_link(RV_REG_ZERO, rvoff, ctx);
1251 case BPF_LD | BPF_IMM | BPF_DW:
1253 struct bpf_insn insn1 = insn[1];
1256 imm64 = (u64)insn1.imm << 32 | (u32)imm;
1257 emit_imm(rd, imm64, ctx);
1261 /* LDX: dst = *(size *)(src + off) */
1262 case BPF_LDX | BPF_MEM | BPF_B:
1263 if (is_12b_int(off)) {
1264 emit(rv_lbu(rd, off, rs), ctx);
1268 emit_imm(RV_REG_T1, off, ctx);
1269 emit(rv_add(RV_REG_T1, RV_REG_T1, rs), ctx);
1270 emit(rv_lbu(rd, 0, RV_REG_T1), ctx);
1271 if (insn_is_zext(&insn[1]))
1274 case BPF_LDX | BPF_MEM | BPF_H:
1275 if (is_12b_int(off)) {
1276 emit(rv_lhu(rd, off, rs), ctx);
1280 emit_imm(RV_REG_T1, off, ctx);
1281 emit(rv_add(RV_REG_T1, RV_REG_T1, rs), ctx);
1282 emit(rv_lhu(rd, 0, RV_REG_T1), ctx);
1283 if (insn_is_zext(&insn[1]))
1286 case BPF_LDX | BPF_MEM | BPF_W:
1287 if (is_12b_int(off)) {
1288 emit(rv_lwu(rd, off, rs), ctx);
1292 emit_imm(RV_REG_T1, off, ctx);
1293 emit(rv_add(RV_REG_T1, RV_REG_T1, rs), ctx);
1294 emit(rv_lwu(rd, 0, RV_REG_T1), ctx);
1295 if (insn_is_zext(&insn[1]))
1298 case BPF_LDX | BPF_MEM | BPF_DW:
1299 if (is_12b_int(off)) {
1300 emit(rv_ld(rd, off, rs), ctx);
1304 emit_imm(RV_REG_T1, off, ctx);
1305 emit(rv_add(RV_REG_T1, RV_REG_T1, rs), ctx);
1306 emit(rv_ld(rd, 0, RV_REG_T1), ctx);
1309 /* ST: *(size *)(dst + off) = imm */
1310 case BPF_ST | BPF_MEM | BPF_B:
1311 emit_imm(RV_REG_T1, imm, ctx);
1312 if (is_12b_int(off)) {
1313 emit(rv_sb(rd, off, RV_REG_T1), ctx);
1317 emit_imm(RV_REG_T2, off, ctx);
1318 emit(rv_add(RV_REG_T2, RV_REG_T2, rd), ctx);
1319 emit(rv_sb(RV_REG_T2, 0, RV_REG_T1), ctx);
1322 case BPF_ST | BPF_MEM | BPF_H:
1323 emit_imm(RV_REG_T1, imm, ctx);
1324 if (is_12b_int(off)) {
1325 emit(rv_sh(rd, off, RV_REG_T1), ctx);
1329 emit_imm(RV_REG_T2, off, ctx);
1330 emit(rv_add(RV_REG_T2, RV_REG_T2, rd), ctx);
1331 emit(rv_sh(RV_REG_T2, 0, RV_REG_T1), ctx);
1333 case BPF_ST | BPF_MEM | BPF_W:
1334 emit_imm(RV_REG_T1, imm, ctx);
1335 if (is_12b_int(off)) {
1336 emit(rv_sw(rd, off, RV_REG_T1), ctx);
1340 emit_imm(RV_REG_T2, off, ctx);
1341 emit(rv_add(RV_REG_T2, RV_REG_T2, rd), ctx);
1342 emit(rv_sw(RV_REG_T2, 0, RV_REG_T1), ctx);
1344 case BPF_ST | BPF_MEM | BPF_DW:
1345 emit_imm(RV_REG_T1, imm, ctx);
1346 if (is_12b_int(off)) {
1347 emit(rv_sd(rd, off, RV_REG_T1), ctx);
1351 emit_imm(RV_REG_T2, off, ctx);
1352 emit(rv_add(RV_REG_T2, RV_REG_T2, rd), ctx);
1353 emit(rv_sd(RV_REG_T2, 0, RV_REG_T1), ctx);
1356 /* STX: *(size *)(dst + off) = src */
1357 case BPF_STX | BPF_MEM | BPF_B:
1358 if (is_12b_int(off)) {
1359 emit(rv_sb(rd, off, rs), ctx);
1363 emit_imm(RV_REG_T1, off, ctx);
1364 emit(rv_add(RV_REG_T1, RV_REG_T1, rd), ctx);
1365 emit(rv_sb(RV_REG_T1, 0, rs), ctx);
1367 case BPF_STX | BPF_MEM | BPF_H:
1368 if (is_12b_int(off)) {
1369 emit(rv_sh(rd, off, rs), ctx);
1373 emit_imm(RV_REG_T1, off, ctx);
1374 emit(rv_add(RV_REG_T1, RV_REG_T1, rd), ctx);
1375 emit(rv_sh(RV_REG_T1, 0, rs), ctx);
1377 case BPF_STX | BPF_MEM | BPF_W:
1378 if (is_12b_int(off)) {
1379 emit(rv_sw(rd, off, rs), ctx);
1383 emit_imm(RV_REG_T1, off, ctx);
1384 emit(rv_add(RV_REG_T1, RV_REG_T1, rd), ctx);
1385 emit(rv_sw(RV_REG_T1, 0, rs), ctx);
1387 case BPF_STX | BPF_MEM | BPF_DW:
1388 if (is_12b_int(off)) {
1389 emit(rv_sd(rd, off, rs), ctx);
1393 emit_imm(RV_REG_T1, off, ctx);
1394 emit(rv_add(RV_REG_T1, RV_REG_T1, rd), ctx);
1395 emit(rv_sd(RV_REG_T1, 0, rs), ctx);
1397 /* STX XADD: lock *(u32 *)(dst + off) += src */
1398 case BPF_STX | BPF_XADD | BPF_W:
1399 /* STX XADD: lock *(u64 *)(dst + off) += src */
1400 case BPF_STX | BPF_XADD | BPF_DW:
1402 if (is_12b_int(off)) {
1403 emit(rv_addi(RV_REG_T1, rd, off), ctx);
1405 emit_imm(RV_REG_T1, off, ctx);
1406 emit(rv_add(RV_REG_T1, RV_REG_T1, rd), ctx);
1412 emit(BPF_SIZE(code) == BPF_W ?
1413 rv_amoadd_w(RV_REG_ZERO, rs, rd, 0, 0) :
1414 rv_amoadd_d(RV_REG_ZERO, rs, rd, 0, 0), ctx);
1417 pr_err("bpf-jit: unknown opcode %02x\n", code);
1424 static void build_prologue(struct rv_jit_context *ctx)
1426 int stack_adjust = 0, store_offset, bpf_stack_adjust;
1428 bpf_stack_adjust = round_up(ctx->prog->aux->stack_depth, 16);
1429 if (bpf_stack_adjust)
1432 if (seen_reg(RV_REG_RA, ctx))
1434 stack_adjust += 8; /* RV_REG_FP */
1435 if (seen_reg(RV_REG_S1, ctx))
1437 if (seen_reg(RV_REG_S2, ctx))
1439 if (seen_reg(RV_REG_S3, ctx))
1441 if (seen_reg(RV_REG_S4, ctx))
1443 if (seen_reg(RV_REG_S5, ctx))
1445 if (seen_reg(RV_REG_S6, ctx))
1448 stack_adjust = round_up(stack_adjust, 16);
1449 stack_adjust += bpf_stack_adjust;
1451 store_offset = stack_adjust - 8;
1453 /* First instruction is always setting the tail-call-counter
1454 * (TCC) register. This instruction is skipped for tail calls.
1456 emit(rv_addi(RV_REG_TCC, RV_REG_ZERO, MAX_TAIL_CALL_CNT), ctx);
1458 emit(rv_addi(RV_REG_SP, RV_REG_SP, -stack_adjust), ctx);
1460 if (seen_reg(RV_REG_RA, ctx)) {
1461 emit(rv_sd(RV_REG_SP, store_offset, RV_REG_RA), ctx);
1464 emit(rv_sd(RV_REG_SP, store_offset, RV_REG_FP), ctx);
1466 if (seen_reg(RV_REG_S1, ctx)) {
1467 emit(rv_sd(RV_REG_SP, store_offset, RV_REG_S1), ctx);
1470 if (seen_reg(RV_REG_S2, ctx)) {
1471 emit(rv_sd(RV_REG_SP, store_offset, RV_REG_S2), ctx);
1474 if (seen_reg(RV_REG_S3, ctx)) {
1475 emit(rv_sd(RV_REG_SP, store_offset, RV_REG_S3), ctx);
1478 if (seen_reg(RV_REG_S4, ctx)) {
1479 emit(rv_sd(RV_REG_SP, store_offset, RV_REG_S4), ctx);
1482 if (seen_reg(RV_REG_S5, ctx)) {
1483 emit(rv_sd(RV_REG_SP, store_offset, RV_REG_S5), ctx);
1486 if (seen_reg(RV_REG_S6, ctx)) {
1487 emit(rv_sd(RV_REG_SP, store_offset, RV_REG_S6), ctx);
1491 emit(rv_addi(RV_REG_FP, RV_REG_SP, stack_adjust), ctx);
1493 if (bpf_stack_adjust)
1494 emit(rv_addi(RV_REG_S5, RV_REG_SP, bpf_stack_adjust), ctx);
1496 /* Program contains calls and tail calls, so RV_REG_TCC need
1497 * to be saved across calls.
1499 if (seen_tail_call(ctx) && seen_call(ctx))
1500 emit(rv_addi(RV_REG_TCC_SAVED, RV_REG_TCC, 0), ctx);
1502 ctx->stack_size = stack_adjust;
1505 static void build_epilogue(struct rv_jit_context *ctx)
1507 __build_epilogue(RV_REG_RA, ctx);
1510 static int build_body(struct rv_jit_context *ctx, bool extra_pass)
1512 const struct bpf_prog *prog = ctx->prog;
1515 for (i = 0; i < prog->len; i++) {
1516 const struct bpf_insn *insn = &prog->insnsi[i];
1519 ret = emit_insn(insn, ctx, extra_pass);
1522 if (ctx->insns == NULL)
1523 ctx->offset[i] = ctx->ninsns;
1526 if (ctx->insns == NULL)
1527 ctx->offset[i] = ctx->ninsns;
1534 static void bpf_fill_ill_insns(void *area, unsigned int size)
1536 memset(area, 0, size);
1539 static void bpf_flush_icache(void *start, void *end)
1541 flush_icache_range((unsigned long)start, (unsigned long)end);
1544 bool bpf_jit_needs_zext(void)
1549 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
1551 bool tmp_blinded = false, extra_pass = false;
1552 struct bpf_prog *tmp, *orig_prog = prog;
1553 int pass = 0, prev_ninsns = 0, i;
1554 struct rv_jit_data *jit_data;
1555 struct rv_jit_context *ctx;
1556 unsigned int image_size;
1558 if (!prog->jit_requested)
1561 tmp = bpf_jit_blind_constants(prog);
1569 jit_data = prog->aux->jit_data;
1571 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
1576 prog->aux->jit_data = jit_data;
1579 ctx = &jit_data->ctx;
1583 image_size = sizeof(u32) * ctx->ninsns;
1588 ctx->offset = kcalloc(prog->len, sizeof(int), GFP_KERNEL);
1593 for (i = 0; i < prog->len; i++) {
1595 ctx->offset[i] = prev_ninsns;
1598 for (i = 0; i < 16; i++) {
1601 if (build_body(ctx, extra_pass)) {
1605 build_prologue(ctx);
1606 ctx->epilogue_offset = ctx->ninsns;
1607 build_epilogue(ctx);
1608 if (ctx->ninsns == prev_ninsns)
1610 prev_ninsns = ctx->ninsns;
1613 /* Allocate image, now that we know the size. */
1614 image_size = sizeof(u32) * ctx->ninsns;
1615 jit_data->header = bpf_jit_binary_alloc(image_size, &jit_data->image,
1617 bpf_fill_ill_insns);
1618 if (!jit_data->header) {
1623 /* Second, real pass, that acutally emits the image. */
1624 ctx->insns = (u32 *)jit_data->image;
1629 build_prologue(ctx);
1630 if (build_body(ctx, extra_pass)) {
1631 bpf_jit_binary_free(jit_data->header);
1635 build_epilogue(ctx);
1637 if (bpf_jit_enable > 1)
1638 bpf_jit_dump(prog->len, image_size, pass, ctx->insns);
1640 prog->bpf_func = (void *)ctx->insns;
1642 prog->jited_len = image_size;
1644 bpf_flush_icache(jit_data->header, ctx->insns + ctx->ninsns);
1646 if (!prog->is_func || extra_pass) {
1650 prog->aux->jit_data = NULL;
1654 bpf_jit_prog_release_other(prog, prog == orig_prog ?