1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 SiFive
6 #include <asm/pgtable.h>
7 #include <asm/cacheflush.h>
13 static void ipi_remote_fence_i(void *info)
15 return local_flush_icache_all();
18 void flush_icache_all(void)
20 if (IS_ENABLED(CONFIG_RISCV_SBI))
21 sbi_remote_fence_i(NULL);
23 on_each_cpu(ipi_remote_fence_i, NULL, 1);
25 EXPORT_SYMBOL(flush_icache_all);
28 * Performs an icache flush for the given MM context. RISC-V has no direct
29 * mechanism for instruction cache shoot downs, so instead we send an IPI that
30 * informs the remote harts they need to flush their local instruction caches.
31 * To avoid pathologically slow behavior in a common case (a bunch of
32 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
33 * IPIs for harts that are not currently executing a MM context and instead
34 * schedule a deferred local instruction cache flush to be performed before
35 * execution resumes on each hart.
37 void flush_icache_mm(struct mm_struct *mm, bool local)
40 cpumask_t others, *mask;
44 /* Mark every hart's icache as needing a flush for this MM. */
45 mask = &mm->context.icache_stale_mask;
47 /* Flush this hart's I$ now, and mark it as flushed. */
48 cpu = smp_processor_id();
49 cpumask_clear_cpu(cpu, mask);
50 local_flush_icache_all();
53 * Flush the I$ of other harts concurrently executing, and mark them as
56 cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
57 local |= cpumask_empty(&others);
58 if (mm == current->active_mm && local) {
60 * It's assumed that at least one strongly ordered operation is
61 * performed on this hart between setting a hart's cpumask bit
62 * and scheduling this MM context on that hart. Sending an SBI
63 * remote message will do this, but in the case where no
64 * messages are sent we still need to order this hart's writes
65 * with flush_icache_deferred().
68 } else if (IS_ENABLED(CONFIG_RISCV_SBI)) {
69 cpumask_t hartid_mask;
71 riscv_cpuid_to_hartid_mask(&others, &hartid_mask);
72 sbi_remote_fence_i(cpumask_bits(&hartid_mask));
74 on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1);
80 #endif /* CONFIG_SMP */
83 void flush_icache_pte(pte_t pte)
85 struct page *page = pte_page(pte);
87 if (!test_and_set_bit(PG_dcache_clean, &page->flags))
90 #endif /* CONFIG_MMU */