1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 SiFive
7 #include <asm/cacheflush.h>
13 static void ipi_remote_fence_i(void *info)
15 return local_flush_icache_all();
18 void flush_icache_all(void)
20 local_flush_icache_all();
22 if (IS_ENABLED(CONFIG_RISCV_SBI) && !riscv_use_ipi_for_rfence())
23 sbi_remote_fence_i(NULL);
25 on_each_cpu(ipi_remote_fence_i, NULL, 1);
27 EXPORT_SYMBOL(flush_icache_all);
30 * Performs an icache flush for the given MM context. RISC-V has no direct
31 * mechanism for instruction cache shoot downs, so instead we send an IPI that
32 * informs the remote harts they need to flush their local instruction caches.
33 * To avoid pathologically slow behavior in a common case (a bunch of
34 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
35 * IPIs for harts that are not currently executing a MM context and instead
36 * schedule a deferred local instruction cache flush to be performed before
37 * execution resumes on each hart.
39 void flush_icache_mm(struct mm_struct *mm, bool local)
42 cpumask_t others, *mask;
46 /* Mark every hart's icache as needing a flush for this MM. */
47 mask = &mm->context.icache_stale_mask;
49 /* Flush this hart's I$ now, and mark it as flushed. */
50 cpu = smp_processor_id();
51 cpumask_clear_cpu(cpu, mask);
52 local_flush_icache_all();
55 * Flush the I$ of other harts concurrently executing, and mark them as
58 cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
59 local |= cpumask_empty(&others);
60 if (mm == current->active_mm && local) {
62 * It's assumed that at least one strongly ordered operation is
63 * performed on this hart between setting a hart's cpumask bit
64 * and scheduling this MM context on that hart. Sending an SBI
65 * remote message will do this, but in the case where no
66 * messages are sent we still need to order this hart's writes
67 * with flush_icache_deferred().
70 } else if (IS_ENABLED(CONFIG_RISCV_SBI) &&
71 !riscv_use_ipi_for_rfence()) {
72 sbi_remote_fence_i(&others);
74 on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1);
80 #endif /* CONFIG_SMP */
83 void flush_icache_pte(pte_t pte)
85 struct page *page = pte_page(pte);
88 * HugeTLB pages are always fully mapped, so only setting head page's
89 * PG_dcache_clean flag is enough.
92 page = compound_head(page);
94 if (!test_bit(PG_dcache_clean, &page->flags)) {
96 set_bit(PG_dcache_clean, &page->flags);
99 #endif /* CONFIG_MMU */
101 unsigned int riscv_cbom_block_size;
102 EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
104 unsigned int riscv_cboz_block_size;
105 EXPORT_SYMBOL_GPL(riscv_cboz_block_size);
107 static void cbo_get_block_size(struct device_node *node,
108 const char *name, u32 *block_size,
109 unsigned long *first_hartid)
111 unsigned long hartid;
114 if (riscv_of_processor_hartid(node, &hartid))
117 if (of_property_read_u32(node, name, &val))
122 *first_hartid = hartid;
123 } else if (*block_size != val) {
124 pr_warn("%s mismatched between harts %lu and %lu\n",
125 name, *first_hartid, hartid);
129 void riscv_init_cbo_blocksizes(void)
131 unsigned long cbom_hartid, cboz_hartid;
132 u32 cbom_block_size = 0, cboz_block_size = 0;
133 struct device_node *node;
135 for_each_of_cpu_node(node) {
136 /* set block-size for cbom and/or cboz extension if available */
137 cbo_get_block_size(node, "riscv,cbom-block-size",
138 &cbom_block_size, &cbom_hartid);
139 cbo_get_block_size(node, "riscv,cboz-block-size",
140 &cboz_block_size, &cboz_hartid);
144 riscv_cbom_block_size = cbom_block_size;
147 riscv_cboz_block_size = cboz_block_size;