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RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs
[linux-2.6-microblaze.git]
/
arch
/
riscv
/
mm
/
Makefile
1
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CFLAGS_init.o := -mcmodel=medany
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ifdef CONFIG_FTRACE
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CFLAGS_REMOVE_init.o = -pg
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endif
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obj-y += init.o
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obj-y += fault.o
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obj-y += extable.o
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obj-y += ioremap.o
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obj-y += cacheflush.o
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obj-y += context.o
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obj-y += sifive_l2_cache.o