1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Western Digital Corporation or its affiliates.
6 * Anup Patel <anup.patel@wdc.com>
9 #include <linux/bitops.h>
10 #include <linux/errno.h>
11 #include <linux/err.h>
12 #include <linux/kdebug.h>
13 #include <linux/module.h>
14 #include <linux/percpu.h>
15 #include <linux/uaccess.h>
16 #include <linux/vmalloc.h>
17 #include <linux/sched/signal.h>
19 #include <linux/kvm_host.h>
21 #include <asm/hwcap.h>
23 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
24 KVM_GENERIC_VCPU_STATS(),
25 STATS_DESC_COUNTER(VCPU, ecall_exit_stat),
26 STATS_DESC_COUNTER(VCPU, wfi_exit_stat),
27 STATS_DESC_COUNTER(VCPU, mmio_exit_user),
28 STATS_DESC_COUNTER(VCPU, mmio_exit_kernel),
29 STATS_DESC_COUNTER(VCPU, exits)
32 const struct kvm_stats_header kvm_vcpu_stats_header = {
33 .name_size = KVM_STATS_NAME_SIZE,
34 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
35 .id_offset = sizeof(struct kvm_stats_header),
36 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
37 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
38 sizeof(kvm_vcpu_stats_desc),
41 #define KVM_RISCV_ISA_DISABLE_ALLOWED (riscv_isa_extension_mask(d) | \
42 riscv_isa_extension_mask(f))
44 #define KVM_RISCV_ISA_DISABLE_NOT_ALLOWED (riscv_isa_extension_mask(a) | \
45 riscv_isa_extension_mask(c) | \
46 riscv_isa_extension_mask(i) | \
47 riscv_isa_extension_mask(m))
49 #define KVM_RISCV_ISA_ALLOWED (KVM_RISCV_ISA_DISABLE_ALLOWED | \
50 KVM_RISCV_ISA_DISABLE_NOT_ALLOWED)
52 static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu)
54 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
55 struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr;
56 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
57 struct kvm_cpu_context *reset_cntx = &vcpu->arch.guest_reset_context;
61 * The preemption should be disabled here because it races with
62 * kvm_sched_out/kvm_sched_in(called from preempt notifiers) which
63 * also calls vcpu_load/put.
66 loaded = (vcpu->cpu != -1);
68 kvm_arch_vcpu_put(vcpu);
70 vcpu->arch.last_exit_cpu = -1;
72 memcpy(csr, reset_csr, sizeof(*csr));
74 memcpy(cntx, reset_cntx, sizeof(*cntx));
76 kvm_riscv_vcpu_fp_reset(vcpu);
78 kvm_riscv_vcpu_timer_reset(vcpu);
80 WRITE_ONCE(vcpu->arch.irqs_pending, 0);
81 WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0);
83 vcpu->arch.hfence_head = 0;
84 vcpu->arch.hfence_tail = 0;
85 memset(vcpu->arch.hfence_queue, 0, sizeof(vcpu->arch.hfence_queue));
87 /* Reset the guest CSRs for hotplug usecase */
89 kvm_arch_vcpu_load(vcpu, smp_processor_id());
93 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
98 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
100 struct kvm_cpu_context *cntx;
101 struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr;
103 /* Mark this VCPU never ran */
104 vcpu->arch.ran_atleast_once = false;
105 vcpu->arch.mmu_page_cache.gfp_zero = __GFP_ZERO;
107 /* Setup ISA features available to VCPU */
108 vcpu->arch.isa = riscv_isa_extension_base(NULL) & KVM_RISCV_ISA_ALLOWED;
110 /* Setup VCPU hfence queue */
111 spin_lock_init(&vcpu->arch.hfence_lock);
113 /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */
114 cntx = &vcpu->arch.guest_reset_context;
115 cntx->sstatus = SR_SPP | SR_SPIE;
117 cntx->hstatus |= HSTATUS_VTW;
118 cntx->hstatus |= HSTATUS_SPVP;
119 cntx->hstatus |= HSTATUS_SPV;
121 /* By default, make CY, TM, and IR counters accessible in VU mode */
122 reset_csr->scounteren = 0x7;
124 /* Setup VCPU timer */
125 kvm_riscv_vcpu_timer_init(vcpu);
128 kvm_riscv_reset_vcpu(vcpu);
133 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
136 * vcpu with id 0 is the designated boot cpu.
137 * Keep all vcpus with non-zero id in power-off state so that
138 * they can be brought up using SBI HSM extension.
140 if (vcpu->vcpu_idx != 0)
141 kvm_riscv_vcpu_power_off(vcpu);
144 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
146 /* Cleanup VCPU timer */
147 kvm_riscv_vcpu_timer_deinit(vcpu);
149 /* Free unused pages pre-allocated for G-stage page table mappings */
150 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache);
153 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
155 return kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER);
158 void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
162 void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu)
166 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
168 return (kvm_riscv_vcpu_has_interrupts(vcpu, -1UL) &&
169 !vcpu->arch.power_off && !vcpu->arch.pause);
172 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
174 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
177 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
179 return (vcpu->arch.guest_context.sstatus & SR_SPP) ? true : false;
182 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
184 return VM_FAULT_SIGBUS;
187 static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
188 const struct kvm_one_reg *reg)
190 unsigned long __user *uaddr =
191 (unsigned long __user *)(unsigned long)reg->addr;
192 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
194 KVM_REG_RISCV_CONFIG);
195 unsigned long reg_val;
197 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
201 case KVM_REG_RISCV_CONFIG_REG(isa):
202 reg_val = vcpu->arch.isa;
208 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
214 static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
215 const struct kvm_one_reg *reg)
217 unsigned long __user *uaddr =
218 (unsigned long __user *)(unsigned long)reg->addr;
219 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
221 KVM_REG_RISCV_CONFIG);
222 unsigned long reg_val;
224 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
227 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
231 case KVM_REG_RISCV_CONFIG_REG(isa):
232 if (!vcpu->arch.ran_atleast_once) {
233 /* Ignore the disable request for these extensions */
234 vcpu->arch.isa = reg_val | KVM_RISCV_ISA_DISABLE_NOT_ALLOWED;
235 vcpu->arch.isa &= riscv_isa_extension_base(NULL);
236 vcpu->arch.isa &= KVM_RISCV_ISA_ALLOWED;
237 kvm_riscv_vcpu_fp_reset(vcpu);
249 static int kvm_riscv_vcpu_get_reg_core(struct kvm_vcpu *vcpu,
250 const struct kvm_one_reg *reg)
252 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
253 unsigned long __user *uaddr =
254 (unsigned long __user *)(unsigned long)reg->addr;
255 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
258 unsigned long reg_val;
260 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
262 if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
265 if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
266 reg_val = cntx->sepc;
267 else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
268 reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
269 reg_val = ((unsigned long *)cntx)[reg_num];
270 else if (reg_num == KVM_REG_RISCV_CORE_REG(mode))
271 reg_val = (cntx->sstatus & SR_SPP) ?
272 KVM_RISCV_MODE_S : KVM_RISCV_MODE_U;
276 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
282 static int kvm_riscv_vcpu_set_reg_core(struct kvm_vcpu *vcpu,
283 const struct kvm_one_reg *reg)
285 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
286 unsigned long __user *uaddr =
287 (unsigned long __user *)(unsigned long)reg->addr;
288 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
291 unsigned long reg_val;
293 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
295 if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
298 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
301 if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
302 cntx->sepc = reg_val;
303 else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
304 reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
305 ((unsigned long *)cntx)[reg_num] = reg_val;
306 else if (reg_num == KVM_REG_RISCV_CORE_REG(mode)) {
307 if (reg_val == KVM_RISCV_MODE_S)
308 cntx->sstatus |= SR_SPP;
310 cntx->sstatus &= ~SR_SPP;
317 static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu,
318 const struct kvm_one_reg *reg)
320 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
321 unsigned long __user *uaddr =
322 (unsigned long __user *)(unsigned long)reg->addr;
323 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
326 unsigned long reg_val;
328 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
330 if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
333 if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
334 kvm_riscv_vcpu_flush_interrupts(vcpu);
335 reg_val = (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK;
337 reg_val = ((unsigned long *)csr)[reg_num];
339 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
345 static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu,
346 const struct kvm_one_reg *reg)
348 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
349 unsigned long __user *uaddr =
350 (unsigned long __user *)(unsigned long)reg->addr;
351 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
354 unsigned long reg_val;
356 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
358 if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
361 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
364 if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
365 reg_val &= VSIP_VALID_MASK;
366 reg_val <<= VSIP_TO_HVIP_SHIFT;
369 ((unsigned long *)csr)[reg_num] = reg_val;
371 if (reg_num == KVM_REG_RISCV_CSR_REG(sip))
372 WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0);
377 /* Mapping between KVM ISA Extension ID & Host ISA extension ID */
378 static unsigned long kvm_isa_ext_arr[] = {
388 static int kvm_riscv_vcpu_get_reg_isa_ext(struct kvm_vcpu *vcpu,
389 const struct kvm_one_reg *reg)
391 unsigned long __user *uaddr =
392 (unsigned long __user *)(unsigned long)reg->addr;
393 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
395 KVM_REG_RISCV_ISA_EXT);
396 unsigned long reg_val = 0;
397 unsigned long host_isa_ext;
399 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
402 if (reg_num >= KVM_RISCV_ISA_EXT_MAX || reg_num >= ARRAY_SIZE(kvm_isa_ext_arr))
405 host_isa_ext = kvm_isa_ext_arr[reg_num];
406 if (__riscv_isa_extension_available(&vcpu->arch.isa, host_isa_ext))
407 reg_val = 1; /* Mark the given extension as available */
409 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
415 static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu,
416 const struct kvm_one_reg *reg)
418 unsigned long __user *uaddr =
419 (unsigned long __user *)(unsigned long)reg->addr;
420 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
422 KVM_REG_RISCV_ISA_EXT);
423 unsigned long reg_val;
424 unsigned long host_isa_ext;
425 unsigned long host_isa_ext_mask;
427 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
430 if (reg_num >= KVM_RISCV_ISA_EXT_MAX || reg_num >= ARRAY_SIZE(kvm_isa_ext_arr))
433 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
436 host_isa_ext = kvm_isa_ext_arr[reg_num];
437 if (!__riscv_isa_extension_available(NULL, host_isa_ext))
440 if (host_isa_ext >= RISCV_ISA_EXT_BASE &&
441 host_isa_ext < RISCV_ISA_EXT_MAX) {
443 * Multi-letter ISA extension. Currently there is no provision
444 * to enable/disable the multi-letter ISA extensions for guests.
445 * Return success if the request is to enable any ISA extension
446 * that is available in the hardware.
447 * Return -EOPNOTSUPP otherwise.
455 /* Single letter base ISA extension */
456 if (!vcpu->arch.ran_atleast_once) {
457 host_isa_ext_mask = BIT_MASK(host_isa_ext);
458 if (!reg_val && (host_isa_ext_mask & KVM_RISCV_ISA_DISABLE_ALLOWED))
459 vcpu->arch.isa &= ~host_isa_ext_mask;
461 vcpu->arch.isa |= host_isa_ext_mask;
462 vcpu->arch.isa &= riscv_isa_extension_base(NULL);
463 vcpu->arch.isa &= KVM_RISCV_ISA_ALLOWED;
464 kvm_riscv_vcpu_fp_reset(vcpu);
472 static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
473 const struct kvm_one_reg *reg)
475 if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
476 return kvm_riscv_vcpu_set_reg_config(vcpu, reg);
477 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
478 return kvm_riscv_vcpu_set_reg_core(vcpu, reg);
479 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
480 return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
481 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
482 return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
483 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
484 return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
486 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
487 return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
489 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
490 return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
495 static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
496 const struct kvm_one_reg *reg)
498 if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
499 return kvm_riscv_vcpu_get_reg_config(vcpu, reg);
500 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
501 return kvm_riscv_vcpu_get_reg_core(vcpu, reg);
502 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
503 return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
504 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
505 return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
506 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
507 return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
509 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
510 return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
512 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
513 return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg);
518 long kvm_arch_vcpu_async_ioctl(struct file *filp,
519 unsigned int ioctl, unsigned long arg)
521 struct kvm_vcpu *vcpu = filp->private_data;
522 void __user *argp = (void __user *)arg;
524 if (ioctl == KVM_INTERRUPT) {
525 struct kvm_interrupt irq;
527 if (copy_from_user(&irq, argp, sizeof(irq)))
530 if (irq.irq == KVM_INTERRUPT_SET)
531 return kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_VS_EXT);
533 return kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_EXT);
539 long kvm_arch_vcpu_ioctl(struct file *filp,
540 unsigned int ioctl, unsigned long arg)
542 struct kvm_vcpu *vcpu = filp->private_data;
543 void __user *argp = (void __user *)arg;
547 case KVM_SET_ONE_REG:
548 case KVM_GET_ONE_REG: {
549 struct kvm_one_reg reg;
552 if (copy_from_user(®, argp, sizeof(reg)))
555 if (ioctl == KVM_SET_ONE_REG)
556 r = kvm_riscv_vcpu_set_reg(vcpu, ®);
558 r = kvm_riscv_vcpu_get_reg(vcpu, ®);
568 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
569 struct kvm_sregs *sregs)
574 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
575 struct kvm_sregs *sregs)
580 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
585 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
590 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
591 struct kvm_translation *tr)
596 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
601 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
606 void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *vcpu)
608 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
609 unsigned long mask, val;
611 if (READ_ONCE(vcpu->arch.irqs_pending_mask)) {
612 mask = xchg_acquire(&vcpu->arch.irqs_pending_mask, 0);
613 val = READ_ONCE(vcpu->arch.irqs_pending) & mask;
620 void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu)
623 struct kvm_vcpu_arch *v = &vcpu->arch;
624 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
626 /* Read current HVIP and VSIE CSRs */
627 csr->vsie = csr_read(CSR_VSIE);
629 /* Sync-up HVIP.VSSIP bit changes does by Guest */
630 hvip = csr_read(CSR_HVIP);
631 if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) {
632 if (hvip & (1UL << IRQ_VS_SOFT)) {
633 if (!test_and_set_bit(IRQ_VS_SOFT,
634 &v->irqs_pending_mask))
635 set_bit(IRQ_VS_SOFT, &v->irqs_pending);
637 if (!test_and_set_bit(IRQ_VS_SOFT,
638 &v->irqs_pending_mask))
639 clear_bit(IRQ_VS_SOFT, &v->irqs_pending);
644 int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq)
646 if (irq != IRQ_VS_SOFT &&
647 irq != IRQ_VS_TIMER &&
651 set_bit(irq, &vcpu->arch.irqs_pending);
652 smp_mb__before_atomic();
653 set_bit(irq, &vcpu->arch.irqs_pending_mask);
660 int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq)
662 if (irq != IRQ_VS_SOFT &&
663 irq != IRQ_VS_TIMER &&
667 clear_bit(irq, &vcpu->arch.irqs_pending);
668 smp_mb__before_atomic();
669 set_bit(irq, &vcpu->arch.irqs_pending_mask);
674 bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, unsigned long mask)
676 unsigned long ie = ((vcpu->arch.guest_csr.vsie & VSIP_VALID_MASK)
677 << VSIP_TO_HVIP_SHIFT) & mask;
679 return (READ_ONCE(vcpu->arch.irqs_pending) & ie) ? true : false;
682 void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu)
684 vcpu->arch.power_off = true;
685 kvm_make_request(KVM_REQ_SLEEP, vcpu);
689 void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu)
691 vcpu->arch.power_off = false;
692 kvm_vcpu_wake_up(vcpu);
695 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
696 struct kvm_mp_state *mp_state)
698 if (vcpu->arch.power_off)
699 mp_state->mp_state = KVM_MP_STATE_STOPPED;
701 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
706 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
707 struct kvm_mp_state *mp_state)
711 switch (mp_state->mp_state) {
712 case KVM_MP_STATE_RUNNABLE:
713 vcpu->arch.power_off = false;
715 case KVM_MP_STATE_STOPPED:
716 kvm_riscv_vcpu_power_off(vcpu);
725 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
726 struct kvm_guest_debug *dbg)
728 /* TODO; To be implemented later. */
732 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
734 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
736 csr_write(CSR_VSSTATUS, csr->vsstatus);
737 csr_write(CSR_VSIE, csr->vsie);
738 csr_write(CSR_VSTVEC, csr->vstvec);
739 csr_write(CSR_VSSCRATCH, csr->vsscratch);
740 csr_write(CSR_VSEPC, csr->vsepc);
741 csr_write(CSR_VSCAUSE, csr->vscause);
742 csr_write(CSR_VSTVAL, csr->vstval);
743 csr_write(CSR_HVIP, csr->hvip);
744 csr_write(CSR_VSATP, csr->vsatp);
746 kvm_riscv_gstage_update_hgatp(vcpu);
748 kvm_riscv_vcpu_timer_restore(vcpu);
750 kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context);
751 kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context,
757 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
759 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
763 kvm_riscv_vcpu_guest_fp_save(&vcpu->arch.guest_context,
765 kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context);
767 csr->vsstatus = csr_read(CSR_VSSTATUS);
768 csr->vsie = csr_read(CSR_VSIE);
769 csr->vstvec = csr_read(CSR_VSTVEC);
770 csr->vsscratch = csr_read(CSR_VSSCRATCH);
771 csr->vsepc = csr_read(CSR_VSEPC);
772 csr->vscause = csr_read(CSR_VSCAUSE);
773 csr->vstval = csr_read(CSR_VSTVAL);
774 csr->hvip = csr_read(CSR_HVIP);
775 csr->vsatp = csr_read(CSR_VSATP);
778 static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu)
780 struct rcuwait *wait = kvm_arch_vcpu_get_wait(vcpu);
782 if (kvm_request_pending(vcpu)) {
783 if (kvm_check_request(KVM_REQ_SLEEP, vcpu)) {
784 kvm_vcpu_srcu_read_unlock(vcpu);
785 rcuwait_wait_event(wait,
786 (!vcpu->arch.power_off) && (!vcpu->arch.pause),
788 kvm_vcpu_srcu_read_lock(vcpu);
790 if (vcpu->arch.power_off || vcpu->arch.pause) {
792 * Awaken to handle a signal, request to
795 kvm_make_request(KVM_REQ_SLEEP, vcpu);
799 if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu))
800 kvm_riscv_reset_vcpu(vcpu);
802 if (kvm_check_request(KVM_REQ_UPDATE_HGATP, vcpu))
803 kvm_riscv_gstage_update_hgatp(vcpu);
805 if (kvm_check_request(KVM_REQ_FENCE_I, vcpu))
806 kvm_riscv_fence_i_process(vcpu);
809 * The generic KVM_REQ_TLB_FLUSH is same as
810 * KVM_REQ_HFENCE_GVMA_VMID_ALL
812 if (kvm_check_request(KVM_REQ_HFENCE_GVMA_VMID_ALL, vcpu))
813 kvm_riscv_hfence_gvma_vmid_all_process(vcpu);
815 if (kvm_check_request(KVM_REQ_HFENCE_VVMA_ALL, vcpu))
816 kvm_riscv_hfence_vvma_all_process(vcpu);
818 if (kvm_check_request(KVM_REQ_HFENCE, vcpu))
819 kvm_riscv_hfence_process(vcpu);
823 static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu)
825 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
827 csr_write(CSR_HVIP, csr->hvip);
831 * Actually run the vCPU, entering an RCU extended quiescent state (EQS) while
832 * the vCPU is running.
834 * This must be noinstr as instrumentation may make use of RCU, and this is not
835 * safe during the EQS.
837 static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu)
839 guest_state_enter_irqoff();
840 __kvm_riscv_switch_to(&vcpu->arch);
841 vcpu->arch.last_exit_cpu = vcpu->cpu;
842 guest_state_exit_irqoff();
845 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
848 struct kvm_cpu_trap trap;
849 struct kvm_run *run = vcpu->run;
851 /* Mark this VCPU ran at least once */
852 vcpu->arch.ran_atleast_once = true;
854 kvm_vcpu_srcu_read_lock(vcpu);
856 /* Process MMIO value returned from user-space */
857 if (run->exit_reason == KVM_EXIT_MMIO) {
858 ret = kvm_riscv_vcpu_mmio_return(vcpu, vcpu->run);
860 kvm_vcpu_srcu_read_unlock(vcpu);
865 /* Process SBI value returned from user-space */
866 if (run->exit_reason == KVM_EXIT_RISCV_SBI) {
867 ret = kvm_riscv_vcpu_sbi_return(vcpu, vcpu->run);
869 kvm_vcpu_srcu_read_unlock(vcpu);
874 if (run->immediate_exit) {
875 kvm_vcpu_srcu_read_unlock(vcpu);
881 kvm_sigset_activate(vcpu);
884 run->exit_reason = KVM_EXIT_UNKNOWN;
886 /* Check conditions before entering the guest */
889 kvm_riscv_gstage_vmid_update(vcpu);
891 kvm_riscv_check_vcpu_requests(vcpu);
898 * Exit if we have a signal pending so that we can deliver
899 * the signal to user space.
901 if (signal_pending(current)) {
903 run->exit_reason = KVM_EXIT_INTR;
907 * Ensure we set mode to IN_GUEST_MODE after we disable
908 * interrupts and before the final VCPU requests check.
909 * See the comment in kvm_vcpu_exiting_guest_mode() and
910 * Documentation/virt/kvm/vcpu-requests.rst
912 vcpu->mode = IN_GUEST_MODE;
914 kvm_vcpu_srcu_read_unlock(vcpu);
915 smp_mb__after_srcu_read_unlock();
918 * We might have got VCPU interrupts updated asynchronously
919 * so update it in HW.
921 kvm_riscv_vcpu_flush_interrupts(vcpu);
923 /* Update HVIP CSR for current CPU */
924 kvm_riscv_update_hvip(vcpu);
927 kvm_riscv_gstage_vmid_ver_changed(&vcpu->kvm->arch.vmid) ||
928 kvm_request_pending(vcpu)) {
929 vcpu->mode = OUTSIDE_GUEST_MODE;
932 kvm_vcpu_srcu_read_lock(vcpu);
937 * Cleanup stale TLB enteries
939 * Note: This should be done after G-stage VMID has been
940 * updated using kvm_riscv_gstage_vmid_ver_changed()
942 kvm_riscv_local_tlb_sanitize(vcpu);
944 guest_timing_enter_irqoff();
946 kvm_riscv_vcpu_enter_exit(vcpu);
948 vcpu->mode = OUTSIDE_GUEST_MODE;
952 * Save SCAUSE, STVAL, HTVAL, and HTINST because we might
953 * get an interrupt between __kvm_riscv_switch_to() and
954 * local_irq_enable() which can potentially change CSRs.
956 trap.sepc = vcpu->arch.guest_context.sepc;
957 trap.scause = csr_read(CSR_SCAUSE);
958 trap.stval = csr_read(CSR_STVAL);
959 trap.htval = csr_read(CSR_HTVAL);
960 trap.htinst = csr_read(CSR_HTINST);
962 /* Syncup interrupts state with HW */
963 kvm_riscv_vcpu_sync_interrupts(vcpu);
966 * We must ensure that any pending interrupts are taken before
967 * we exit guest timing so that timer ticks are accounted as
968 * guest time. Transiently unmask interrupts so that any
969 * pending interrupts are taken.
971 * There's no barrier which ensures that pending interrupts are
972 * recognised, so we just hope that the CPU takes any pending
973 * interrupts between the enable and disable.
978 guest_timing_exit_irqoff();
984 kvm_vcpu_srcu_read_lock(vcpu);
986 ret = kvm_riscv_vcpu_exit(vcpu, run, &trap);
989 kvm_sigset_deactivate(vcpu);
993 kvm_vcpu_srcu_read_unlock(vcpu);