1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012 Regents of the University of California
4 * Copyright (C) 2017 SiFive
5 * Copyright (C) 2020 Vitaly Wool, Konsulko AB
8 #include <asm/pgtable.h>
9 #define LOAD_OFFSET KERNEL_LINK_ADDR
10 /* No __ro_after_init data in the .rodata section - which will always be ro */
11 #define RO_AFTER_INIT_DATA
13 #include <asm/vmlinux.lds.h>
15 #include <asm/pgtable.h>
16 #include <asm/cache.h>
17 #include <asm/thread_info.h>
26 /* Beginning of code and text segment */
31 INIT_TEXT_SECTION(PAGE_SIZE)
32 /* we have to discard exit text and such at runtime, not link time */
52 RO_DATA(L1_CACHE_BYTES)
62 _exiprom = .; /* End of XIP ROM area */
66 * From this point, stuff is considered writable and will be copied to RAM
68 __data_loc = ALIGN(16); /* location in file */
69 . = LOAD_OFFSET + XIP_OFFSET; /* location in memory */
71 _sdata = .; /* Start of data section */
73 RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
75 __start_ro_after_init = .;
76 .data.ro_after_init : AT(ADDR(.data.ro_after_init) - LOAD_OFFSET) {
77 *(.data..ro_after_init)
79 __end_ro_after_init = .;
90 __soc_early_init_table : {
91 __soc_early_init_table_start = .;
92 KEEP(*(__soc_early_init_table))
93 __soc_early_init_table_end = .;
95 __soc_builtin_dtb_table : {
96 __soc_builtin_dtb_table_start = .;
97 KEEP(*(__soc_builtin_dtb_table))
98 __soc_builtin_dtb_table_end = .;
100 PERCPU_SECTION(L1_CACHE_BYTES)
112 __xip_traps_start = .;
117 . = ALIGN(PAGE_SIZE);
119 __global_pointer$ = . + 0x800;
124 BSS_SECTION(PAGE_SIZE, PAGE_SIZE, 0)
125 EXCEPTION_TABLE(0x10)
127 .rel.dyn : AT(ADDR(.rel.dyn) - LOAD_OFFSET) {
132 * End of copied data. We need a dummy section to get its LMA.
133 * Also located before final ALIGN() as trailing padding is not stored
134 * in the resulting binary file and useless to copy.
136 .data.endmark : AT(ADDR(.data.endmark) - LOAD_OFFSET) { }
137 _edata_loc = LOADADDR(.data.endmark);
139 . = ALIGN(PAGE_SIZE);