1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012 Regents of the University of California
6 #include <asm/thread_info.h>
7 #include <asm/asm-offsets.h>
9 #include <linux/init.h>
10 #include <linux/linkage.h>
11 #include <asm/thread_info.h>
14 #include <asm/hwcap.h>
15 #include <asm/image.h>
20 * Image header expected by Linux boot-loaders. The image header data
21 * structure is described in asm/image.h.
22 * Do not modify it without modifying the structure and all bootloaders
23 * that expects this header format!!
25 /* jump to start kernel */
30 #if __riscv_xlen == 64
31 /* Image load offset(2MB) from start of RAM */
34 /* Image load offset(4MB) from start of RAM */
37 /* Effective size of kernel image */
40 .word RISCV_HEADER_VERSION
43 .ascii RISCV_IMAGE_MAGIC
45 .ascii RISCV_IMAGE_MAGIC2
50 /* Mask all interrupts */
54 #ifdef CONFIG_RISCV_M_MODE
55 /* flush the instruction cache */
58 /* Reset all registers except ra, a0, a1 */
62 * The hartid in a0 is expected later on, and we have no firmware
66 #endif /* CONFIG_RISCV_M_MODE */
68 /* Load the global pointer */
71 la gp, __global_pointer$
75 * Disable FPU to detect illegal usage of
76 * floating point in kernel space
83 blt a0, t0, .Lgood_cores
88 /* Pick one hart to run the main boot sequence */
92 bnez a3, .Lsecondary_start
94 /* Clear BSS for flat non-ELF images */
97 ble a4, a3, clear_bss_done
100 add a3, a3, RISCV_SZPTR
101 blt a3, a4, clear_bss
104 /* Save hart ID and DTB physical address */
107 la a2, boot_cpu_hartid
110 /* Initialize page tables and relocate to virtual addresses */
111 la sp, init_thread_union + THREAD_SIZE
117 #endif /* CONFIG_MMU */
119 /* Restore C environment */
121 sw zero, TASK_TI_CPU(tp)
122 la sp, init_thread_union + THREAD_SIZE
124 /* Start the kernel */
130 /* Relocate return address */
136 /* Point stvec to virtual address of intruction after satp write */
141 /* Compute satp for kernel page tables, but don't load it yet */
142 srl a2, a0, PAGE_SHIFT
147 * Load trampoline page directory, which will cause us to trap to
148 * stvec if VA != PA, or simply fall through if VA == PA. We need a
149 * full fence here because setup_vm() just wrote these PTEs and we need
150 * to ensure the new translations are in use.
152 la a0, trampoline_pg_dir
153 srl a0, a0, PAGE_SHIFT
159 /* Set trap vector to spin forever to help debug */
160 la a0, .Lsecondary_park
163 /* Reload the global pointer */
166 la gp, __global_pointer$
170 * Switch to kernel page tables. A full fence is necessary in order to
171 * avoid using the trampoline translations, which are only correct for
172 * the first superpage. Fetching the fence is guarnteed to work
173 * because that first superpage is translated the same way.
179 #endif /* CONFIG_MMU */
183 /* Set trap vector to spin forever to help debug */
184 la a3, .Lsecondary_park
188 la a1, __cpu_up_stack_pointer
189 la a2, __cpu_up_task_pointer
194 * This hart didn't win the lottery, so we wait for the winning hart to
195 * get far enough along the boot process that it should continue.
198 /* FIXME: We should WFI to save some energy here. */
201 beqz sp, .Lwait_for_cpu_up
202 beqz tp, .Lwait_for_cpu_up
206 /* Enable virtual memory and relocate to virtual address */
207 la a0, swapper_pg_dir
216 #ifdef CONFIG_RISCV_M_MODE
250 andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
251 beqz t0, .Lreset_regs_done
288 /* note that the caller must clear SR_FS */
289 #endif /* CONFIG_FPU */
293 #endif /* CONFIG_RISCV_M_MODE */
295 .section ".text", "ax",@progbits
298 /* We lack SMP support or have too many harts, so park this hart */
303 /* Empty zero page */