1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2015 Regents of the University of California
6 #ifndef _ASM_RISCV_CSR_H
7 #define _ASM_RISCV_CSR_H
10 #include <linux/const.h>
12 /* Status register flags */
13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
22 #define SR_FS_OFF _AC(0x00000000, UL)
23 #define SR_FS_INITIAL _AC(0x00002000, UL)
24 #define SR_FS_CLEAN _AC(0x00004000, UL)
25 #define SR_FS_DIRTY _AC(0x00006000, UL)
27 #define SR_XS _AC(0x00018000, UL) /* Extension Status */
28 #define SR_XS_OFF _AC(0x00000000, UL)
29 #define SR_XS_INITIAL _AC(0x00008000, UL)
30 #define SR_XS_CLEAN _AC(0x00010000, UL)
31 #define SR_XS_DIRTY _AC(0x00018000, UL)
34 #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
36 #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
41 #define SATP_PPN _AC(0x003FFFFF, UL)
42 #define SATP_MODE_32 _AC(0x80000000, UL)
43 #define SATP_MODE SATP_MODE_32
44 #define SATP_ASID_BITS 9
45 #define SATP_ASID_SHIFT 22
46 #define SATP_ASID_MASK _AC(0x1FF, UL)
48 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
49 #define SATP_MODE_39 _AC(0x8000000000000000, UL)
50 #define SATP_MODE SATP_MODE_39
51 #define SATP_ASID_BITS 16
52 #define SATP_ASID_SHIFT 44
53 #define SATP_ASID_MASK _AC(0xFFFF, UL)
56 /* Exception cause high bit - is an interrupt if set */
57 #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
59 /* Interrupt causes (minus the high bit) */
67 /* Exception causes */
68 #define EXC_INST_MISALIGNED 0
69 #define EXC_INST_ACCESS 1
70 #define EXC_BREAKPOINT 3
71 #define EXC_LOAD_ACCESS 5
72 #define EXC_STORE_ACCESS 7
74 #define EXC_INST_PAGE_FAULT 12
75 #define EXC_LOAD_PAGE_FAULT 13
76 #define EXC_STORE_PAGE_FAULT 15
78 /* PMP configuration */
83 #define PMP_A_TOR 0x08
84 #define PMP_A_NA4 0x10
85 #define PMP_A_NAPOT 0x18
88 /* symbolic CSR names: */
89 #define CSR_CYCLE 0xc00
90 #define CSR_TIME 0xc01
91 #define CSR_INSTRET 0xc02
92 #define CSR_CYCLEH 0xc80
93 #define CSR_TIMEH 0xc81
94 #define CSR_INSTRETH 0xc82
96 #define CSR_SSTATUS 0x100
98 #define CSR_STVEC 0x105
99 #define CSR_SCOUNTEREN 0x106
100 #define CSR_SSCRATCH 0x140
101 #define CSR_SEPC 0x141
102 #define CSR_SCAUSE 0x142
103 #define CSR_STVAL 0x143
104 #define CSR_SIP 0x144
105 #define CSR_SATP 0x180
107 #define CSR_MSTATUS 0x300
108 #define CSR_MISA 0x301
109 #define CSR_MIE 0x304
110 #define CSR_MTVEC 0x305
111 #define CSR_MSCRATCH 0x340
112 #define CSR_MEPC 0x341
113 #define CSR_MCAUSE 0x342
114 #define CSR_MTVAL 0x343
115 #define CSR_MIP 0x344
116 #define CSR_PMPCFG0 0x3a0
117 #define CSR_PMPADDR0 0x3b0
118 #define CSR_MVENDORID 0xf11
119 #define CSR_MARCHID 0xf12
120 #define CSR_MIMPID 0xf13
121 #define CSR_MHARTID 0xf14
123 #ifdef CONFIG_RISCV_M_MODE
124 # define CSR_STATUS CSR_MSTATUS
125 # define CSR_IE CSR_MIE
126 # define CSR_TVEC CSR_MTVEC
127 # define CSR_SCRATCH CSR_MSCRATCH
128 # define CSR_EPC CSR_MEPC
129 # define CSR_CAUSE CSR_MCAUSE
130 # define CSR_TVAL CSR_MTVAL
131 # define CSR_IP CSR_MIP
133 # define SR_IE SR_MIE
134 # define SR_PIE SR_MPIE
135 # define SR_PP SR_MPP
137 # define RV_IRQ_SOFT IRQ_M_SOFT
138 # define RV_IRQ_TIMER IRQ_M_TIMER
139 # define RV_IRQ_EXT IRQ_M_EXT
140 #else /* CONFIG_RISCV_M_MODE */
141 # define CSR_STATUS CSR_SSTATUS
142 # define CSR_IE CSR_SIE
143 # define CSR_TVEC CSR_STVEC
144 # define CSR_SCRATCH CSR_SSCRATCH
145 # define CSR_EPC CSR_SEPC
146 # define CSR_CAUSE CSR_SCAUSE
147 # define CSR_TVAL CSR_STVAL
148 # define CSR_IP CSR_SIP
150 # define SR_IE SR_SIE
151 # define SR_PIE SR_SPIE
152 # define SR_PP SR_SPP
154 # define RV_IRQ_SOFT IRQ_S_SOFT
155 # define RV_IRQ_TIMER IRQ_S_TIMER
156 # define RV_IRQ_EXT IRQ_S_EXT
157 #endif /* CONFIG_RISCV_M_MODE */
159 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
160 #define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT)
161 #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
162 #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
166 #define csr_swap(csr, val) \
168 unsigned long __v = (unsigned long)(val); \
169 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
170 : "=r" (__v) : "rK" (__v) \
175 #define csr_read(csr) \
177 register unsigned long __v; \
178 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
184 #define csr_write(csr, val) \
186 unsigned long __v = (unsigned long)(val); \
187 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
192 #define csr_read_set(csr, val) \
194 unsigned long __v = (unsigned long)(val); \
195 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
196 : "=r" (__v) : "rK" (__v) \
201 #define csr_set(csr, val) \
203 unsigned long __v = (unsigned long)(val); \
204 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
209 #define csr_read_clear(csr, val) \
211 unsigned long __v = (unsigned long)(val); \
212 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
213 : "=r" (__v) : "rK" (__v) \
218 #define csr_clear(csr, val) \
220 unsigned long __v = (unsigned long)(val); \
221 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \
226 #endif /* __ASSEMBLY__ */
228 #endif /* _ASM_RISCV_CSR_H */