1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020 SiFive, Inc */
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
11 compatible = "sifive,fu740-c000", "sifive,fu740";
26 compatible = "sifive,bullet0", "riscv";
28 i-cache-block-size = <64>;
30 i-cache-size = <16384>;
31 next-level-cache = <&ccache>;
33 riscv,isa = "rv64imac";
35 cpu0_intc: interrupt-controller {
36 #interrupt-cells = <1>;
37 compatible = "riscv,cpu-intc";
42 compatible = "sifive,bullet0", "riscv";
43 d-cache-block-size = <64>;
45 d-cache-size = <32768>;
49 i-cache-block-size = <64>;
51 i-cache-size = <32768>;
54 mmu-type = "riscv,sv39";
55 next-level-cache = <&ccache>;
57 riscv,isa = "rv64imafdc";
59 cpu1_intc: interrupt-controller {
60 #interrupt-cells = <1>;
61 compatible = "riscv,cpu-intc";
66 compatible = "sifive,bullet0", "riscv";
67 d-cache-block-size = <64>;
69 d-cache-size = <32768>;
73 i-cache-block-size = <64>;
75 i-cache-size = <32768>;
78 mmu-type = "riscv,sv39";
79 next-level-cache = <&ccache>;
81 riscv,isa = "rv64imafdc";
83 cpu2_intc: interrupt-controller {
84 #interrupt-cells = <1>;
85 compatible = "riscv,cpu-intc";
90 compatible = "sifive,bullet0", "riscv";
91 d-cache-block-size = <64>;
93 d-cache-size = <32768>;
97 i-cache-block-size = <64>;
99 i-cache-size = <32768>;
102 mmu-type = "riscv,sv39";
103 next-level-cache = <&ccache>;
105 riscv,isa = "rv64imafdc";
107 cpu3_intc: interrupt-controller {
108 #interrupt-cells = <1>;
109 compatible = "riscv,cpu-intc";
110 interrupt-controller;
114 compatible = "sifive,bullet0", "riscv";
115 d-cache-block-size = <64>;
117 d-cache-size = <32768>;
121 i-cache-block-size = <64>;
122 i-cache-sets = <128>;
123 i-cache-size = <32768>;
126 mmu-type = "riscv,sv39";
127 next-level-cache = <&ccache>;
129 riscv,isa = "rv64imafdc";
131 cpu4_intc: interrupt-controller {
132 #interrupt-cells = <1>;
133 compatible = "riscv,cpu-intc";
134 interrupt-controller;
139 #address-cells = <2>;
141 compatible = "simple-bus";
143 plic0: interrupt-controller@c000000 {
144 #interrupt-cells = <1>;
145 #address-cells = <0>;
146 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
147 reg = <0x0 0xc000000 0x0 0x4000000>;
149 interrupt-controller;
150 interrupts-extended = <
151 &cpu0_intc 0xffffffff
152 &cpu1_intc 0xffffffff &cpu1_intc 9
153 &cpu2_intc 0xffffffff &cpu2_intc 9
154 &cpu3_intc 0xffffffff &cpu3_intc 9
155 &cpu4_intc 0xffffffff &cpu4_intc 9>;
157 prci: clock-controller@10000000 {
158 compatible = "sifive,fu740-c000-prci";
159 reg = <0x0 0x10000000 0x0 0x1000>;
160 clocks = <&hfclk>, <&rtcclk>;
164 uart0: serial@10010000 {
165 compatible = "sifive,fu740-c000-uart", "sifive,uart0";
166 reg = <0x0 0x10010000 0x0 0x1000>;
167 interrupt-parent = <&plic0>;
169 clocks = <&prci PRCI_CLK_PCLK>;
172 uart1: serial@10011000 {
173 compatible = "sifive,fu740-c000-uart", "sifive,uart0";
174 reg = <0x0 0x10011000 0x0 0x1000>;
175 interrupt-parent = <&plic0>;
177 clocks = <&prci PRCI_CLK_PCLK>;
181 compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
182 reg = <0x0 0x10030000 0x0 0x1000>;
183 interrupt-parent = <&plic0>;
185 clocks = <&prci PRCI_CLK_PCLK>;
188 #address-cells = <1>;
193 compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
194 reg = <0x0 0x10031000 0x0 0x1000>;
195 interrupt-parent = <&plic0>;
197 clocks = <&prci PRCI_CLK_PCLK>;
200 #address-cells = <1>;
204 qspi0: spi@10040000 {
205 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
206 reg = <0x0 0x10040000 0x0 0x1000>,
207 <0x0 0x20000000 0x0 0x10000000>;
208 interrupt-parent = <&plic0>;
210 clocks = <&prci PRCI_CLK_PCLK>;
211 #address-cells = <1>;
215 qspi1: spi@10041000 {
216 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
217 reg = <0x0 0x10041000 0x0 0x1000>,
218 <0x0 0x30000000 0x0 0x10000000>;
219 interrupt-parent = <&plic0>;
221 clocks = <&prci PRCI_CLK_PCLK>;
222 #address-cells = <1>;
227 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
228 reg = <0x0 0x10050000 0x0 0x1000>;
229 interrupt-parent = <&plic0>;
231 clocks = <&prci PRCI_CLK_PCLK>;
232 #address-cells = <1>;
236 eth0: ethernet@10090000 {
237 compatible = "sifive,fu540-c000-gem";
238 interrupt-parent = <&plic0>;
240 reg = <0x0 0x10090000 0x0 0x2000>,
241 <0x0 0x100a0000 0x0 0x1000>;
242 local-mac-address = [00 00 00 00 00 00];
243 clock-names = "pclk", "hclk";
244 clocks = <&prci PRCI_CLK_GEMGXLPLL>,
245 <&prci PRCI_CLK_GEMGXLPLL>;
246 #address-cells = <1>;
251 compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
252 reg = <0x0 0x10020000 0x0 0x1000>;
253 interrupt-parent = <&plic0>;
254 interrupts = <44>, <45>, <46>, <47>;
255 clocks = <&prci PRCI_CLK_PCLK>;
260 compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
261 reg = <0x0 0x10021000 0x0 0x1000>;
262 interrupt-parent = <&plic0>;
263 interrupts = <48>, <49>, <50>, <51>;
264 clocks = <&prci PRCI_CLK_PCLK>;
268 ccache: cache-controller@2010000 {
269 compatible = "sifive,fu740-c000-ccache", "cache";
270 cache-block-size = <64>;
273 cache-size = <2097152>;
275 interrupt-parent = <&plic0>;
276 interrupts = <19 20 21 22>;
277 reg = <0x0 0x2010000 0x0 0x1000>;
279 gpio: gpio@10060000 {
280 compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
281 interrupt-parent = <&plic0>;
282 interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
283 <30>, <31>, <32>, <33>, <34>, <35>, <36>,
285 reg = <0x0 0x10060000 0x0 0x1000>;
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 clocks = <&prci PRCI_CLK_PCLK>;
294 compatible = "sifive,fu740-pcie";
295 #address-cells = <3>;
297 #interrupt-cells = <1>;
298 reg = <0xe 0x00000000 0x0 0x80000000>,
299 <0xd 0xf0000000 0x0 0x10000000>,
300 <0x0 0x100d0000 0x0 0x1000>;
301 reg-names = "dbi", "config", "mgmt";
304 bus-range = <0x0 0xff>;
305 ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
306 <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
307 <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
308 <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
310 interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
311 interrupt-names = "msi", "inta", "intb", "intc", "intd";
312 interrupt-parent = <&plic0>;
313 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
314 interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
315 <0x0 0x0 0x0 0x2 &plic0 58>,
316 <0x0 0x0 0x0 0x3 &plic0 59>,
317 <0x0 0x0 0x0 0x4 &plic0 60>;
318 clock-names = "pcie_aux";
319 clocks = <&prci PRCI_CLK_PCIE_AUX>;
320 pwren-gpios = <&gpio 5 0>;
321 reset-gpios = <&gpio 8 0>;