1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
11 compatible = "sifive,fu540-c000", "sifive,fu540";
24 timebase-frequency = <1000000>;
26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
28 i-cache-block-size = <64>;
30 i-cache-size = <16384>;
32 riscv,isa = "rv64imac";
34 cpu0_intc: interrupt-controller {
35 #interrupt-cells = <1>;
36 compatible = "riscv,cpu-intc";
41 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
42 d-cache-block-size = <64>;
44 d-cache-size = <32768>;
48 i-cache-block-size = <64>;
50 i-cache-size = <32768>;
53 mmu-type = "riscv,sv39";
55 riscv,isa = "rv64imafdc";
57 cpu1_intc: interrupt-controller {
58 #interrupt-cells = <1>;
59 compatible = "riscv,cpu-intc";
64 clock-frequency = <0>;
65 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
66 d-cache-block-size = <64>;
68 d-cache-size = <32768>;
72 i-cache-block-size = <64>;
74 i-cache-size = <32768>;
77 mmu-type = "riscv,sv39";
79 riscv,isa = "rv64imafdc";
81 cpu2_intc: interrupt-controller {
82 #interrupt-cells = <1>;
83 compatible = "riscv,cpu-intc";
88 clock-frequency = <0>;
89 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
90 d-cache-block-size = <64>;
92 d-cache-size = <32768>;
96 i-cache-block-size = <64>;
98 i-cache-size = <32768>;
101 mmu-type = "riscv,sv39";
103 riscv,isa = "rv64imafdc";
105 cpu3_intc: interrupt-controller {
106 #interrupt-cells = <1>;
107 compatible = "riscv,cpu-intc";
108 interrupt-controller;
112 clock-frequency = <0>;
113 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
114 d-cache-block-size = <64>;
116 d-cache-size = <32768>;
120 i-cache-block-size = <64>;
122 i-cache-size = <32768>;
125 mmu-type = "riscv,sv39";
127 riscv,isa = "rv64imafdc";
129 cpu4_intc: interrupt-controller {
130 #interrupt-cells = <1>;
131 compatible = "riscv,cpu-intc";
132 interrupt-controller;
137 #address-cells = <2>;
139 compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
141 plic0: interrupt-controller@c000000 {
142 #interrupt-cells = <1>;
143 compatible = "sifive,plic-1.0.0";
144 reg = <0x0 0xc000000 0x0 0x4000000>;
146 interrupt-controller;
147 interrupts-extended = <
148 &cpu0_intc 0xffffffff
149 &cpu1_intc 0xffffffff &cpu1_intc 9
150 &cpu2_intc 0xffffffff &cpu2_intc 9
151 &cpu3_intc 0xffffffff &cpu3_intc 9
152 &cpu4_intc 0xffffffff &cpu4_intc 9>;
154 prci: clock-controller@10000000 {
155 compatible = "sifive,fu540-c000-prci";
156 reg = <0x0 0x10000000 0x0 0x1000>;
157 clocks = <&hfclk>, <&rtcclk>;
160 uart0: serial@10010000 {
161 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
162 reg = <0x0 0x10010000 0x0 0x1000>;
163 interrupt-parent = <&plic0>;
165 clocks = <&prci PRCI_CLK_TLCLK>;
168 uart1: serial@10011000 {
169 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
170 reg = <0x0 0x10011000 0x0 0x1000>;
171 interrupt-parent = <&plic0>;
173 clocks = <&prci PRCI_CLK_TLCLK>;
177 compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
178 reg = <0x0 0x10030000 0x0 0x1000>;
179 interrupt-parent = <&plic0>;
181 clocks = <&prci PRCI_CLK_TLCLK>;
184 #address-cells = <1>;
188 qspi0: spi@10040000 {
189 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
190 reg = <0x0 0x10040000 0x0 0x1000
191 0x0 0x20000000 0x0 0x10000000>;
192 interrupt-parent = <&plic0>;
194 clocks = <&prci PRCI_CLK_TLCLK>;
195 #address-cells = <1>;
199 qspi1: spi@10041000 {
200 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
201 reg = <0x0 0x10041000 0x0 0x1000
202 0x0 0x30000000 0x0 0x10000000>;
203 interrupt-parent = <&plic0>;
205 clocks = <&prci PRCI_CLK_TLCLK>;
206 #address-cells = <1>;
210 qspi2: spi@10050000 {
211 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
212 reg = <0x0 0x10050000 0x0 0x1000>;
213 interrupt-parent = <&plic0>;
215 clocks = <&prci PRCI_CLK_TLCLK>;
216 #address-cells = <1>;