1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020 Microchip Technology Inc */
9 model = "Microchip MPFS Icicle Kit";
10 compatible = "microchip,mpfs-icicle-kit";
20 clock-frequency = <0>;
21 compatible = "sifive,e51", "sifive,rocket0", "riscv";
23 i-cache-block-size = <64>;
25 i-cache-size = <16384>;
27 riscv,isa = "rv64imac";
30 cpu0_intc: interrupt-controller {
31 #interrupt-cells = <1>;
32 compatible = "riscv,cpu-intc";
38 clock-frequency = <0>;
39 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
40 d-cache-block-size = <64>;
42 d-cache-size = <32768>;
46 i-cache-block-size = <64>;
48 i-cache-size = <32768>;
51 mmu-type = "riscv,sv39";
53 riscv,isa = "rv64imafdc";
57 cpu1_intc: interrupt-controller {
58 #interrupt-cells = <1>;
59 compatible = "riscv,cpu-intc";
65 clock-frequency = <0>;
66 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
67 d-cache-block-size = <64>;
69 d-cache-size = <32768>;
73 i-cache-block-size = <64>;
75 i-cache-size = <32768>;
78 mmu-type = "riscv,sv39";
80 riscv,isa = "rv64imafdc";
84 cpu2_intc: interrupt-controller {
85 #interrupt-cells = <1>;
86 compatible = "riscv,cpu-intc";
92 clock-frequency = <0>;
93 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
94 d-cache-block-size = <64>;
96 d-cache-size = <32768>;
100 i-cache-block-size = <64>;
102 i-cache-size = <32768>;
105 mmu-type = "riscv,sv39";
107 riscv,isa = "rv64imafdc";
111 cpu3_intc: interrupt-controller {
112 #interrupt-cells = <1>;
113 compatible = "riscv,cpu-intc";
114 interrupt-controller;
119 clock-frequency = <0>;
120 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
121 d-cache-block-size = <64>;
123 d-cache-size = <32768>;
127 i-cache-block-size = <64>;
129 i-cache-size = <32768>;
132 mmu-type = "riscv,sv39";
134 riscv,isa = "rv64imafdc";
137 cpu4_intc: interrupt-controller {
138 #interrupt-cells = <1>;
139 compatible = "riscv,cpu-intc";
140 interrupt-controller;
146 #address-cells = <2>;
148 compatible = "simple-bus";
151 cache-controller@2010000 {
152 compatible = "sifive,fu540-c000-ccache", "cache";
153 cache-block-size = <64>;
156 cache-size = <2097152>;
158 interrupt-parent = <&plic>;
159 interrupts = <1 2 3>;
160 reg = <0x0 0x2010000 0x0 0x1000>;
164 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
165 reg = <0x0 0x2000000 0x0 0xC000>;
166 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
167 &cpu1_intc 3 &cpu1_intc 7
168 &cpu2_intc 3 &cpu2_intc 7
169 &cpu3_intc 3 &cpu3_intc 7
170 &cpu4_intc 3 &cpu4_intc 7>;
173 plic: interrupt-controller@c000000 {
174 #interrupt-cells = <1>;
175 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
176 reg = <0x0 0xc000000 0x0 0x4000000>;
178 interrupt-controller;
179 interrupts-extended = <&cpu0_intc 11
180 &cpu1_intc 11 &cpu1_intc 9
181 &cpu2_intc 11 &cpu2_intc 9
182 &cpu3_intc 11 &cpu3_intc 9
183 &cpu4_intc 11 &cpu4_intc 9>;
187 compatible = "sifive,fu540-c000-pdma";
188 reg = <0x0 0x3000000 0x0 0x8000>;
189 interrupt-parent = <&plic>;
190 interrupts = <23 24 25 26 27 28 29 30>;
195 compatible = "fixed-clock";
197 clock-frequency = <600000000>;
198 clock-output-names = "msspllclk";
201 clkcfg: clkcfg@20002000 {
202 compatible = "microchip,mpfs-clkcfg";
203 reg = <0x0 0x20002000 0x0 0x1000>;
204 reg-names = "mss_sysreg";
207 clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */
208 "mac0", "mac1", "mmc", "timer", /* 4-7 */
209 "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */
210 "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */
211 "i2c1", "can0", "can1", "usb", /* 16-19 */
212 "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */
213 "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */
214 "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */
217 serial0: serial@20000000 {
218 compatible = "ns16550a";
219 reg = <0x0 0x20000000 0x0 0x400>;
222 interrupt-parent = <&plic>;
224 current-speed = <115200>;
225 clocks = <&clkcfg 8>;
229 serial1: serial@20100000 {
230 compatible = "ns16550a";
231 reg = <0x0 0x20100000 0x0 0x400>;
234 interrupt-parent = <&plic>;
236 current-speed = <115200>;
237 clocks = <&clkcfg 9>;
241 serial2: serial@20102000 {
242 compatible = "ns16550a";
243 reg = <0x0 0x20102000 0x0 0x400>;
246 interrupt-parent = <&plic>;
248 current-speed = <115200>;
249 clocks = <&clkcfg 10>;
253 serial3: serial@20104000 {
254 compatible = "ns16550a";
255 reg = <0x0 0x20104000 0x0 0x400>;
258 interrupt-parent = <&plic>;
260 current-speed = <115200>;
261 clocks = <&clkcfg 11>;
266 compatible = "cdns,sd4hc";
267 reg = <0x0 0x20008000 0x0 0x1000>;
268 interrupt-parent = <&plic>;
269 interrupts = <88 89>;
270 pinctrl-names = "default";
271 clocks = <&clkcfg 6>;
275 max-frequency = <200000000>;
279 voltage-ranges = <3300 3300>;
283 sdcard: sdhc@20008000 {
284 compatible = "cdns,sd4hc";
285 reg = <0x0 0x20008000 0x0 0x1000>;
286 interrupt-parent = <&plic>;
288 pinctrl-names = "default";
289 clocks = <&clkcfg 6>;
293 card-detect-delay = <200>;
298 max-frequency = <200000000>;
302 emac0: ethernet@20110000 {
303 compatible = "cdns,macb";
304 reg = <0x0 0x20110000 0x0 0x2000>;
305 interrupt-parent = <&plic>;
306 interrupts = <64 65 66 67>;
307 local-mac-address = [00 00 00 00 00 00];
308 clocks = <&clkcfg 4>, <&clkcfg 2>;
309 clock-names = "pclk", "hclk";
311 #address-cells = <1>;
315 emac1: ethernet@20112000 {
316 compatible = "cdns,macb";
317 reg = <0x0 0x20112000 0x0 0x2000>;
318 interrupt-parent = <&plic>;
319 interrupts = <70 71 72 73>;
320 local-mac-address = [00 00 00 00 00 00];
321 clocks = <&clkcfg 5>, <&clkcfg 2>;
323 clock-names = "pclk", "hclk";
324 #address-cells = <1>;