arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
   3
   4 / {
   5         core_pwm0: pwm@41000000 {
   6                 compatible = "microchip,corepwm-rtl-v4";
   7                 reg = <0x0 0x41000000 0x0 0xF0>;
   8                 microchip,sync-update-mask = /bits/ 32 <0>;
   9                 #pwm-cells = <2>;
  10                 clocks = <&clkcfg CLK_FIC3>;
  11                 status = "disabled";
  12         };
  13
  14         i2c2: i2c@44000000 {
  15                 compatible = "microchip,corei2c-rtl-v7";
  16                 reg = <0x0 0x44000000 0x0 0x1000>;
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 clocks = <&clkcfg CLK_FIC3>;
  20                 interrupt-parent = <&plic>;
  21                 interrupts = <122>;
  22                 clock-frequency = <100000>;
  23                 status = "disabled";
  24         };
  25 };