arch/powerpc/sysdev/xive/native.c

   1 /*
   2  * Copyright 2016,2017 IBM Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #define pr_fmt(fmt) "xive: " fmt
  11
  12 #include <linux/types.h>
  13 #include <linux/irq.h>
  14 #include <linux/debugfs.h>
  15 #include <linux/smp.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/seq_file.h>
  18 #include <linux/init.h>
  19 #include <linux/of.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/delay.h>
  23 #include <linux/cpumask.h>
  24 #include <linux/mm.h>
  25
  26 #include <asm/prom.h>
  27 #include <asm/io.h>
  28 #include <asm/smp.h>
  29 #include <asm/irq.h>
  30 #include <asm/errno.h>
  31 #include <asm/xive.h>
  32 #include <asm/xive-regs.h>
  33 #include <asm/opal.h>
  34 #include <asm/kvm_ppc.h>
  35
  36 #include "xive-internal.h"
  37
  38
  39 static u32 xive_provision_size;
  40 static u32 *xive_provision_chips;
  41 static u32 xive_provision_chip_count;
  42 static u32 xive_queue_shift;
  43 static u32 xive_pool_vps = XIVE_INVALID_VP;
  44 static struct kmem_cache *xive_provision_cache;
  45
  46 int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
  47 {
  48         __be64 flags, eoi_page, trig_page;
  49         __be32 esb_shift, src_chip;
  50         u64 opal_flags;
  51         s64 rc;
  52
  53         memset(data, 0, sizeof(*data));
  54
  55         rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page,
  56                                     &esb_shift, &src_chip);
  57         if (rc) {
  58                 pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n",
  59                        hw_irq, rc);
  60                 return -EINVAL;
  61         }
  62
  63         opal_flags = be64_to_cpu(flags);
  64         if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI)
  65                 data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
  66         if (opal_flags & OPAL_XIVE_IRQ_LSI)
  67                 data->flags |= XIVE_IRQ_FLAG_LSI;
  68         if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG)
  69                 data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG;
  70         if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW)
  71                 data->flags |= XIVE_IRQ_FLAG_MASK_FW;
  72         if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
  73                 data->flags |= XIVE_IRQ_FLAG_EOI_FW;
  74         data->eoi_page = be64_to_cpu(eoi_page);
  75         data->trig_page = be64_to_cpu(trig_page);
  76         data->esb_shift = be32_to_cpu(esb_shift);
  77         data->src_chip = be32_to_cpu(src_chip);
  78
  79         data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
  80         if (!data->eoi_mmio) {
  81                 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
  82                 return -ENOMEM;
  83         }
  84
  85         if (!data->trig_page)
  86                 return 0;
  87         if (data->trig_page == data->eoi_page) {
  88                 data->trig_mmio = data->eoi_mmio;
  89                 return 0;
  90         }
  91
  92         data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
  93         if (!data->trig_mmio) {
  94                 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
  95                 return -ENOMEM;
  96         }
  97         return 0;
  98 }
  99 EXPORT_SYMBOL_GPL(xive_native_populate_irq_data);
 100
 101 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
 102 {
 103         s64 rc;
 104
 105         for (;;) {
 106                 rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq);
 107                 if (rc != OPAL_BUSY)
 108                         break;
 109                 msleep(1);
 110         }
 111         return rc == 0 ? 0 : -ENXIO;
 112 }
 113 EXPORT_SYMBOL_GPL(xive_native_configure_irq);
 114
 115
 116 /* This can be called multiple time to change a queue configuration */
 117 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
 118                                 __be32 *qpage, u32 order, bool can_escalate)
 119 {
 120         s64 rc = 0;
 121         __be64 qeoi_page_be;
 122         __be32 esc_irq_be;
 123         u64 flags, qpage_phys;
 124
 125         /* If there's an actual queue page, clean it */
 126         if (order) {
 127                 if (WARN_ON(!qpage))
 128                         return -EINVAL;
 129                 qpage_phys = __pa(qpage);
 130         } else
 131                 qpage_phys = 0;
 132
 133         /* Initialize the rest of the fields */
 134         q->msk = order ? ((1u << (order - 2)) - 1) : 0;
 135         q->idx = 0;
 136         q->toggle = 0;
 137
 138         rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL,
 139                                       &qeoi_page_be,
 140                                       &esc_irq_be,
 141                                       NULL);
 142         if (rc) {
 143                 pr_err("Error %lld getting queue info prio %d\n", rc, prio);
 144                 rc = -EIO;
 145                 goto fail;
 146         }
 147         q->eoi_phys = be64_to_cpu(qeoi_page_be);
 148
 149         /* Default flags */
 150         flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED;
 151
 152         /* Escalation needed ? */
 153         if (can_escalate) {
 154                 q->esc_irq = be32_to_cpu(esc_irq_be);
 155                 flags |= OPAL_XIVE_EQ_ESCALATE;
 156         }
 157
 158         /* Configure and enable the queue in HW */
 159         for (;;) {
 160                 rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags);
 161                 if (rc != OPAL_BUSY)
 162                         break;
 163                 msleep(1);
 164         }
 165         if (rc) {
 166                 pr_err("Error %lld setting queue for prio %d\n", rc, prio);
 167                 rc = -EIO;
 168         } else {
 169                 /*
 170                  * KVM code requires all of the above to be visible before
 171                  * q->qpage is set due to how it manages IPI EOIs
 172                  */
 173                 wmb();
 174                 q->qpage = qpage;
 175         }
 176 fail:
 177         return rc;
 178 }
 179 EXPORT_SYMBOL_GPL(xive_native_configure_queue);
 180
 181 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
 182 {
 183         s64 rc;
 184
 185         /* Disable the queue in HW */
 186         for (;;) {
 187                 rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0);
 188                 if (rc != OPAL_BUSY)
 189                         break;
 190                 msleep(1);
 191         }
 192         if (rc)
 193                 pr_err("Error %lld disabling queue for prio %d\n", rc, prio);
 194 }
 195
 196 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
 197 {
 198         __xive_native_disable_queue(vp_id, q, prio);
 199 }
 200 EXPORT_SYMBOL_GPL(xive_native_disable_queue);
 201
 202 static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
 203 {
 204         struct xive_q *q = &xc->queue[prio];
 205         __be32 *qpage;
 206
 207         qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
 208         if (IS_ERR(qpage))
 209                 return PTR_ERR(qpage);
 210
 211         return xive_native_configure_queue(get_hard_smp_processor_id(cpu),
 212                                            q, prio, qpage, xive_queue_shift, false);
 213 }
 214
 215 static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
 216 {
 217         struct xive_q *q = &xc->queue[prio];
 218         unsigned int alloc_order;
 219
 220         /*
 221          * We use the variant with no iounmap as this is called on exec
 222          * from an IPI and iounmap isn't safe
 223          */
 224         __xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio);
 225         alloc_order = xive_alloc_order(xive_queue_shift);
 226         free_pages((unsigned long)q->qpage, alloc_order);
 227         q->qpage = NULL;
 228 }
 229
 230 static bool xive_native_match(struct device_node *node)
 231 {
 232         return of_device_is_compatible(node, "ibm,opal-xive-vc");
 233 }
 234
 235 #ifdef CONFIG_SMP
 236 static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc)
 237 {
 238         struct device_node *np;
 239         unsigned int chip_id;
 240         s64 irq;
 241
 242         /* Find the chip ID */
 243         np = of_get_cpu_node(cpu, NULL);
 244         if (np) {
 245                 if (of_property_read_u32(np, "ibm,chip-id", &chip_id) < 0)
 246                         chip_id = 0;
 247         }
 248
 249         /* Allocate an IPI and populate info about it */
 250         for (;;) {
 251                 irq = opal_xive_allocate_irq(chip_id);
 252                 if (irq == OPAL_BUSY) {
 253                         msleep(1);
 254                         continue;
 255                 }
 256                 if (irq < 0) {
 257                         pr_err("Failed to allocate IPI on CPU %d\n", cpu);
 258                         return -ENXIO;
 259                 }
 260                 xc->hw_ipi = irq;
 261                 break;
 262         }
 263         return 0;
 264 }
 265 #endif /* CONFIG_SMP */
 266
 267 u32 xive_native_alloc_irq(void)
 268 {
 269         s64 rc;
 270
 271         for (;;) {
 272                 rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP);
 273                 if (rc != OPAL_BUSY)
 274                         break;
 275                 msleep(1);
 276         }
 277         if (rc < 0)
 278                 return 0;
 279         return rc;
 280 }
 281 EXPORT_SYMBOL_GPL(xive_native_alloc_irq);
 282
 283 void xive_native_free_irq(u32 irq)
 284 {
 285         for (;;) {
 286                 s64 rc = opal_xive_free_irq(irq);
 287                 if (rc != OPAL_BUSY)
 288                         break;
 289                 msleep(1);
 290         }
 291 }
 292 EXPORT_SYMBOL_GPL(xive_native_free_irq);
 293
 294 #ifdef CONFIG_SMP
 295 static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc)
 296 {
 297         s64 rc;
 298
 299         /* Free the IPI */
 300         if (!xc->hw_ipi)
 301                 return;
 302         for (;;) {
 303                 rc = opal_xive_free_irq(xc->hw_ipi);
 304                 if (rc == OPAL_BUSY) {
 305                         msleep(1);
 306                         continue;
 307                 }
 308                 xc->hw_ipi = 0;
 309                 break;
 310         }
 311 }
 312 #endif /* CONFIG_SMP */
 313
 314 static void xive_native_shutdown(void)
 315 {
 316         /* Switch the XIVE to emulation mode */
 317         opal_xive_reset(OPAL_XIVE_MODE_EMU);
 318 }
 319
 320 /*
 321  * Perform an "ack" cycle on the current thread, thus
 322  * grabbing the pending active priorities and updating
 323  * the CPPR to the most favored one.
 324  */
 325 static void xive_native_update_pending(struct xive_cpu *xc)
 326 {
 327         u8 he, cppr;
 328         u16 ack;
 329
 330         /* Perform the acknowledge hypervisor to register cycle */
 331         ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG));
 332
 333         /* Synchronize subsequent queue accesses */
 334         mb();
 335
 336         /*
 337          * Grab the CPPR and the "HE" field which indicates the source
 338          * of the hypervisor interrupt (if any)
 339          */
 340         cppr = ack & 0xff;
 341         he = GETFIELD(TM_QW3_NSR_HE, (ack >> 8));
 342         switch(he) {
 343         case TM_QW3_NSR_HE_NONE: /* Nothing to see here */
 344                 break;
 345         case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */
 346                 if (cppr == 0xff)
 347                         return;
 348                 /* Mark the priority pending */
 349                 xc->pending_prio |= 1 << cppr;
 350
 351                 /*
 352                  * A new interrupt should never have a CPPR less favored
 353                  * than our current one.
 354                  */
 355                 if (cppr >= xc->cppr)
 356                         pr_err("CPU %d odd ack CPPR, got %d at %d\n",
 357                                smp_processor_id(), cppr, xc->cppr);
 358
 359                 /* Update our idea of what the CPPR is */
 360                 xc->cppr = cppr;
 361                 break;
 362         case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */
 363         case TM_QW3_NSR_HE_LSI:  /* Legacy FW LSI (unused) */
 364                 pr_err("CPU %d got unexpected interrupt type HE=%d\n",
 365                        smp_processor_id(), he);
 366                 return;
 367         }
 368 }
 369
 370 static void xive_native_eoi(u32 hw_irq)
 371 {
 372         /*
 373          * Not normally used except if specific interrupts need
 374          * a workaround on EOI.
 375          */
 376         opal_int_eoi(hw_irq);
 377 }
 378
 379 static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
 380 {
 381         s64 rc;
 382         u32 vp;
 383         __be64 vp_cam_be;
 384         u64 vp_cam;
 385
 386         if (xive_pool_vps == XIVE_INVALID_VP)
 387                 return;
 388
 389         /* Enable the pool VP */
 390         vp = xive_pool_vps + cpu;
 391         pr_debug("CPU %d setting up pool VP 0x%x\n", cpu, vp);
 392         for (;;) {
 393                 rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0);
 394                 if (rc != OPAL_BUSY)
 395                         break;
 396                 msleep(1);
 397         }
 398         if (rc) {
 399                 pr_err("Failed to enable pool VP on CPU %d\n", cpu);
 400                 return;
 401         }
 402
 403         /* Grab it's CAM value */
 404         rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL);
 405         if (rc) {
 406                 pr_err("Failed to get pool VP info CPU %d\n", cpu);
 407                 return;
 408         }
 409         vp_cam = be64_to_cpu(vp_cam_be);
 410
 411         pr_debug("VP CAM = %llx\n", vp_cam);
 412
 413         /* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */
 414         pr_debug("(Old HW value: %08x)\n",
 415                  in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
 416         out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff);
 417         out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2,
 418                  TM_QW2W2_VP | vp_cam);
 419         pr_debug("(New HW value: %08x)\n",
 420                  in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
 421 }
 422
 423 static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
 424 {
 425         s64 rc;
 426         u32 vp;
 427
 428         if (xive_pool_vps == XIVE_INVALID_VP)
 429                 return;
 430
 431         /* Pull the pool VP from the CPU */
 432         in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
 433
 434         /* Disable it */
 435         vp = xive_pool_vps + cpu;
 436         for (;;) {
 437                 rc = opal_xive_set_vp_info(vp, 0, 0);
 438                 if (rc != OPAL_BUSY)
 439                         break;
 440                 msleep(1);
 441         }
 442 }
 443
 444 void xive_native_sync_source(u32 hw_irq)
 445 {
 446         opal_xive_sync(XIVE_SYNC_EAS, hw_irq);
 447 }
 448 EXPORT_SYMBOL_GPL(xive_native_sync_source);
 449
 450 static const struct xive_ops xive_native_ops = {
 451         .populate_irq_data      = xive_native_populate_irq_data,
 452         .configure_irq          = xive_native_configure_irq,
 453         .setup_queue            = xive_native_setup_queue,
 454         .cleanup_queue          = xive_native_cleanup_queue,
 455         .match                  = xive_native_match,
 456         .shutdown               = xive_native_shutdown,
 457         .update_pending         = xive_native_update_pending,
 458         .eoi                    = xive_native_eoi,
 459         .setup_cpu              = xive_native_setup_cpu,
 460         .teardown_cpu           = xive_native_teardown_cpu,
 461         .sync_source            = xive_native_sync_source,
 462 #ifdef CONFIG_SMP
 463         .get_ipi                = xive_native_get_ipi,
 464         .put_ipi                = xive_native_put_ipi,
 465 #endif /* CONFIG_SMP */
 466         .name                   = "native",
 467 };
 468
 469 static bool xive_parse_provisioning(struct device_node *np)
 470 {
 471         int rc;
 472
 473         if (of_property_read_u32(np, "ibm,xive-provision-page-size",
 474                                  &xive_provision_size) < 0)
 475                 return true;
 476         rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4);
 477         if (rc < 0) {
 478                 pr_err("Error %d getting provision chips array\n", rc);
 479                 return false;
 480         }
 481         xive_provision_chip_count = rc;
 482         if (rc == 0)
 483                 return true;
 484
 485         xive_provision_chips = kzalloc(4 * xive_provision_chip_count,
 486                                        GFP_KERNEL);
 487         if (WARN_ON(!xive_provision_chips))
 488                 return false;
 489
 490         rc = of_property_read_u32_array(np, "ibm,xive-provision-chips",
 491                                         xive_provision_chips,
 492                                         xive_provision_chip_count);
 493         if (rc < 0) {
 494                 pr_err("Error %d reading provision chips array\n", rc);
 495                 return false;
 496         }
 497
 498         xive_provision_cache = kmem_cache_create("xive-provision",
 499                                                  xive_provision_size,
 500                                                  xive_provision_size,
 501                                                  0, NULL);
 502         if (!xive_provision_cache) {
 503                 pr_err("Failed to allocate provision cache\n");
 504                 return false;
 505         }
 506         return true;
 507 }
 508
 509 static void xive_native_setup_pools(void)
 510 {
 511         /* Allocate a pool big enough */
 512         pr_debug("XIVE: Allocating VP block for pool size %d\n", nr_cpu_ids);
 513
 514         xive_pool_vps = xive_native_alloc_vp_block(nr_cpu_ids);
 515         if (WARN_ON(xive_pool_vps == XIVE_INVALID_VP))
 516                 pr_err("XIVE: Failed to allocate pool VP, KVM might not function\n");
 517
 518         pr_debug("XIVE: Pool VPs allocated at 0x%x for %d max CPUs\n",
 519                  xive_pool_vps, nr_cpu_ids);
 520 }
 521
 522 u32 xive_native_default_eq_shift(void)
 523 {
 524         return xive_queue_shift;
 525 }
 526 EXPORT_SYMBOL_GPL(xive_native_default_eq_shift);
 527
 528 bool __init xive_native_init(void)
 529 {
 530         struct device_node *np;
 531         struct resource r;
 532         void __iomem *tima;
 533         struct property *prop;
 534         u8 max_prio = 7;
 535         const __be32 *p;
 536         u32 val, cpu;
 537         s64 rc;
 538
 539         if (xive_cmdline_disabled)
 540                 return false;
 541
 542         pr_devel("xive_native_init()\n");
 543         np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe");
 544         if (!np) {
 545                 pr_devel("not found !\n");
 546                 return false;
 547         }
 548         pr_devel("Found %pOF\n", np);
 549
 550         /* Resource 1 is HV window */
 551         if (of_address_to_resource(np, 1, &r)) {
 552                 pr_err("Failed to get thread mgmnt area resource\n");
 553                 return false;
 554         }
 555         tima = ioremap(r.start, resource_size(&r));
 556         if (!tima) {
 557                 pr_err("Failed to map thread mgmnt area\n");
 558                 return false;
 559         }
 560
 561         /* Read number of priorities */
 562         if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0)
 563                 max_prio = val - 1;
 564
 565         /* Iterate the EQ sizes and pick one */
 566         of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) {
 567                 xive_queue_shift = val;
 568                 if (val == PAGE_SHIFT)
 569                         break;
 570         }
 571
 572         /* Configure Thread Management areas for KVM */
 573         for_each_possible_cpu(cpu)
 574                 kvmppc_set_xive_tima(cpu, r.start, tima);
 575
 576         /* Grab size of provisionning pages */
 577         xive_parse_provisioning(np);
 578
 579         /* Switch the XIVE to exploitation mode */
 580         rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL);
 581         if (rc) {
 582                 pr_err("Switch to exploitation mode failed with error %lld\n", rc);
 583                 return false;
 584         }
 585
 586         /* Setup some dummy HV pool VPs */
 587         xive_native_setup_pools();
 588
 589         /* Initialize XIVE core with our backend */
 590         if (!xive_core_init(&xive_native_ops, tima, TM_QW3_HV_PHYS,
 591                             max_prio)) {
 592                 opal_xive_reset(OPAL_XIVE_MODE_EMU);
 593                 return false;
 594         }
 595         pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
 596         return true;
 597 }
 598
 599 static bool xive_native_provision_pages(void)
 600 {
 601         u32 i;
 602         void *p;
 603
 604         for (i = 0; i < xive_provision_chip_count; i++) {
 605                 u32 chip = xive_provision_chips[i];
 606
 607                 /*
 608                  * XXX TODO: Try to make the allocation local to the node where
 609                  * the chip resides.
 610                  */
 611                 p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL);
 612                 if (!p) {
 613                         pr_err("Failed to allocate provisioning page\n");
 614                         return false;
 615                 }
 616                 opal_xive_donate_page(chip, __pa(p));
 617         }
 618         return true;
 619 }
 620
 621 u32 xive_native_alloc_vp_block(u32 max_vcpus)
 622 {
 623         s64 rc;
 624         u32 order;
 625
 626         order = fls(max_vcpus) - 1;
 627         if (max_vcpus > (1 << order))
 628                 order++;
 629
 630         pr_debug("VP block alloc, for max VCPUs %d use order %d\n",
 631                  max_vcpus, order);
 632
 633         for (;;) {
 634                 rc = opal_xive_alloc_vp_block(order);
 635                 switch (rc) {
 636                 case OPAL_BUSY:
 637                         msleep(1);
 638                         break;
 639                 case OPAL_XIVE_PROVISIONING:
 640                         if (!xive_native_provision_pages())
 641                                 return XIVE_INVALID_VP;
 642                         break;
 643                 default:
 644                         if (rc < 0) {
 645                                 pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n",
 646                                        order, rc);
 647                                 return XIVE_INVALID_VP;
 648                         }
 649                         return rc;
 650                 }
 651         }
 652 }
 653 EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block);
 654
 655 void xive_native_free_vp_block(u32 vp_base)
 656 {
 657         s64 rc;
 658
 659         if (vp_base == XIVE_INVALID_VP)
 660                 return;
 661
 662         rc = opal_xive_free_vp_block(vp_base);
 663         if (rc < 0)
 664                 pr_warn("OPAL error %lld freeing VP block\n", rc);
 665 }
 666 EXPORT_SYMBOL_GPL(xive_native_free_vp_block);
 667
 668 int xive_native_enable_vp(u32 vp_id)
 669 {
 670         s64 rc;
 671
 672         for (;;) {
 673                 rc = opal_xive_set_vp_info(vp_id, OPAL_XIVE_VP_ENABLED, 0);
 674                 if (rc != OPAL_BUSY)
 675                         break;
 676                 msleep(1);
 677         }
 678         return rc ? -EIO : 0;
 679 }
 680 EXPORT_SYMBOL_GPL(xive_native_enable_vp);
 681
 682 int xive_native_disable_vp(u32 vp_id)
 683 {
 684         s64 rc;
 685
 686         for (;;) {
 687                 rc = opal_xive_set_vp_info(vp_id, 0, 0);
 688                 if (rc != OPAL_BUSY)
 689                         break;
 690                 msleep(1);
 691         }
 692         return rc ? -EIO : 0;
 693 }
 694 EXPORT_SYMBOL_GPL(xive_native_disable_vp);
 695
 696 int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id)
 697 {
 698         __be64 vp_cam_be;
 699         __be32 vp_chip_id_be;
 700         s64 rc;
 701
 702         rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be);
 703         if (rc)
 704                 return -EIO;
 705         *out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu;
 706         *out_chip_id = be32_to_cpu(vp_chip_id_be);
 707
 708         return 0;
 709 }
 710 EXPORT_SYMBOL_GPL(xive_native_get_vp_info);