arch/powerpc/sysdev/xive/native.c

   1 /*
   2  * Copyright 2016,2017 IBM Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #define pr_fmt(fmt) "xive: " fmt
  11
  12 #include <linux/types.h>
  13 #include <linux/irq.h>
  14 #include <linux/debugfs.h>
  15 #include <linux/smp.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/seq_file.h>
  18 #include <linux/init.h>
  19 #include <linux/of.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/delay.h>
  23 #include <linux/cpumask.h>
  24 #include <linux/mm.h>
  25
  26 #include <asm/prom.h>
  27 #include <asm/io.h>
  28 #include <asm/smp.h>
  29 #include <asm/irq.h>
  30 #include <asm/errno.h>
  31 #include <asm/xive.h>
  32 #include <asm/xive-regs.h>
  33 #include <asm/opal.h>
  34 #include <asm/kvm_ppc.h>
  35
  36 #include "xive-internal.h"
  37
  38
  39 static u32 xive_provision_size;
  40 static u32 *xive_provision_chips;
  41 static u32 xive_provision_chip_count;
  42 static u32 xive_queue_shift;
  43 static u32 xive_pool_vps = XIVE_INVALID_VP;
  44 static struct kmem_cache *xive_provision_cache;
  45 static bool xive_has_single_esc;
  46
  47 int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
  48 {
  49         __be64 flags, eoi_page, trig_page;
  50         __be32 esb_shift, src_chip;
  51         u64 opal_flags;
  52         s64 rc;
  53
  54         memset(data, 0, sizeof(*data));
  55
  56         rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page,
  57                                     &esb_shift, &src_chip);
  58         if (rc) {
  59                 pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n",
  60                        hw_irq, rc);
  61                 return -EINVAL;
  62         }
  63
  64         opal_flags = be64_to_cpu(flags);
  65         if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI)
  66                 data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
  67         if (opal_flags & OPAL_XIVE_IRQ_LSI)
  68                 data->flags |= XIVE_IRQ_FLAG_LSI;
  69         if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG)
  70                 data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG;
  71         if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW)
  72                 data->flags |= XIVE_IRQ_FLAG_MASK_FW;
  73         if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
  74                 data->flags |= XIVE_IRQ_FLAG_EOI_FW;
  75         data->eoi_page = be64_to_cpu(eoi_page);
  76         data->trig_page = be64_to_cpu(trig_page);
  77         data->esb_shift = be32_to_cpu(esb_shift);
  78         data->src_chip = be32_to_cpu(src_chip);
  79
  80         data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
  81         if (!data->eoi_mmio) {
  82                 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
  83                 return -ENOMEM;
  84         }
  85
  86         data->hw_irq = hw_irq;
  87
  88         if (!data->trig_page)
  89                 return 0;
  90         if (data->trig_page == data->eoi_page) {
  91                 data->trig_mmio = data->eoi_mmio;
  92                 return 0;
  93         }
  94
  95         data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
  96         if (!data->trig_mmio) {
  97                 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
  98                 return -ENOMEM;
  99         }
 100         return 0;
 101 }
 102 EXPORT_SYMBOL_GPL(xive_native_populate_irq_data);
 103
 104 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
 105 {
 106         s64 rc;
 107
 108         for (;;) {
 109                 rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq);
 110                 if (rc != OPAL_BUSY)
 111                         break;
 112                 msleep(1);
 113         }
 114         return rc == 0 ? 0 : -ENXIO;
 115 }
 116 EXPORT_SYMBOL_GPL(xive_native_configure_irq);
 117
 118
 119 /* This can be called multiple time to change a queue configuration */
 120 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
 121                                 __be32 *qpage, u32 order, bool can_escalate)
 122 {
 123         s64 rc = 0;
 124         __be64 qeoi_page_be;
 125         __be32 esc_irq_be;
 126         u64 flags, qpage_phys;
 127
 128         /* If there's an actual queue page, clean it */
 129         if (order) {
 130                 if (WARN_ON(!qpage))
 131                         return -EINVAL;
 132                 qpage_phys = __pa(qpage);
 133         } else
 134                 qpage_phys = 0;
 135
 136         /* Initialize the rest of the fields */
 137         q->msk = order ? ((1u << (order - 2)) - 1) : 0;
 138         q->idx = 0;
 139         q->toggle = 0;
 140
 141         rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL,
 142                                       &qeoi_page_be,
 143                                       &esc_irq_be,
 144                                       NULL);
 145         if (rc) {
 146                 pr_err("Error %lld getting queue info prio %d\n", rc, prio);
 147                 rc = -EIO;
 148                 goto fail;
 149         }
 150         q->eoi_phys = be64_to_cpu(qeoi_page_be);
 151
 152         /* Default flags */
 153         flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED;
 154
 155         /* Escalation needed ? */
 156         if (can_escalate) {
 157                 q->esc_irq = be32_to_cpu(esc_irq_be);
 158                 flags |= OPAL_XIVE_EQ_ESCALATE;
 159         }
 160
 161         /* Configure and enable the queue in HW */
 162         for (;;) {
 163                 rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags);
 164                 if (rc != OPAL_BUSY)
 165                         break;
 166                 msleep(1);
 167         }
 168         if (rc) {
 169                 pr_err("Error %lld setting queue for prio %d\n", rc, prio);
 170                 rc = -EIO;
 171         } else {
 172                 /*
 173                  * KVM code requires all of the above to be visible before
 174                  * q->qpage is set due to how it manages IPI EOIs
 175                  */
 176                 wmb();
 177                 q->qpage = qpage;
 178         }
 179 fail:
 180         return rc;
 181 }
 182 EXPORT_SYMBOL_GPL(xive_native_configure_queue);
 183
 184 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
 185 {
 186         s64 rc;
 187
 188         /* Disable the queue in HW */
 189         for (;;) {
 190                 rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0);
 191                 if (rc != OPAL_BUSY)
 192                         break;
 193                 msleep(1);
 194         }
 195         if (rc)
 196                 pr_err("Error %lld disabling queue for prio %d\n", rc, prio);
 197 }
 198
 199 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
 200 {
 201         __xive_native_disable_queue(vp_id, q, prio);
 202 }
 203 EXPORT_SYMBOL_GPL(xive_native_disable_queue);
 204
 205 static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
 206 {
 207         struct xive_q *q = &xc->queue[prio];
 208         __be32 *qpage;
 209
 210         qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
 211         if (IS_ERR(qpage))
 212                 return PTR_ERR(qpage);
 213
 214         return xive_native_configure_queue(get_hard_smp_processor_id(cpu),
 215                                            q, prio, qpage, xive_queue_shift, false);
 216 }
 217
 218 static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
 219 {
 220         struct xive_q *q = &xc->queue[prio];
 221         unsigned int alloc_order;
 222
 223         /*
 224          * We use the variant with no iounmap as this is called on exec
 225          * from an IPI and iounmap isn't safe
 226          */
 227         __xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio);
 228         alloc_order = xive_alloc_order(xive_queue_shift);
 229         free_pages((unsigned long)q->qpage, alloc_order);
 230         q->qpage = NULL;
 231 }
 232
 233 static bool xive_native_match(struct device_node *node)
 234 {
 235         return of_device_is_compatible(node, "ibm,opal-xive-vc");
 236 }
 237
 238 #ifdef CONFIG_SMP
 239 static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc)
 240 {
 241         struct device_node *np;
 242         unsigned int chip_id;
 243         s64 irq;
 244
 245         /* Find the chip ID */
 246         np = of_get_cpu_node(cpu, NULL);
 247         if (np) {
 248                 if (of_property_read_u32(np, "ibm,chip-id", &chip_id) < 0)
 249                         chip_id = 0;
 250         }
 251
 252         /* Allocate an IPI and populate info about it */
 253         for (;;) {
 254                 irq = opal_xive_allocate_irq(chip_id);
 255                 if (irq == OPAL_BUSY) {
 256                         msleep(1);
 257                         continue;
 258                 }
 259                 if (irq < 0) {
 260                         pr_err("Failed to allocate IPI on CPU %d\n", cpu);
 261                         return -ENXIO;
 262                 }
 263                 xc->hw_ipi = irq;
 264                 break;
 265         }
 266         return 0;
 267 }
 268 #endif /* CONFIG_SMP */
 269
 270 u32 xive_native_alloc_irq(void)
 271 {
 272         s64 rc;
 273
 274         for (;;) {
 275                 rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP);
 276                 if (rc != OPAL_BUSY)
 277                         break;
 278                 msleep(1);
 279         }
 280         if (rc < 0)
 281                 return 0;
 282         return rc;
 283 }
 284 EXPORT_SYMBOL_GPL(xive_native_alloc_irq);
 285
 286 void xive_native_free_irq(u32 irq)
 287 {
 288         for (;;) {
 289                 s64 rc = opal_xive_free_irq(irq);
 290                 if (rc != OPAL_BUSY)
 291                         break;
 292                 msleep(1);
 293         }
 294 }
 295 EXPORT_SYMBOL_GPL(xive_native_free_irq);
 296
 297 #ifdef CONFIG_SMP
 298 static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc)
 299 {
 300         s64 rc;
 301
 302         /* Free the IPI */
 303         if (!xc->hw_ipi)
 304                 return;
 305         for (;;) {
 306                 rc = opal_xive_free_irq(xc->hw_ipi);
 307                 if (rc == OPAL_BUSY) {
 308                         msleep(1);
 309                         continue;
 310                 }
 311                 xc->hw_ipi = 0;
 312                 break;
 313         }
 314 }
 315 #endif /* CONFIG_SMP */
 316
 317 static void xive_native_shutdown(void)
 318 {
 319         /* Switch the XIVE to emulation mode */
 320         opal_xive_reset(OPAL_XIVE_MODE_EMU);
 321 }
 322
 323 /*
 324  * Perform an "ack" cycle on the current thread, thus
 325  * grabbing the pending active priorities and updating
 326  * the CPPR to the most favored one.
 327  */
 328 static void xive_native_update_pending(struct xive_cpu *xc)
 329 {
 330         u8 he, cppr;
 331         u16 ack;
 332
 333         /* Perform the acknowledge hypervisor to register cycle */
 334         ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG));
 335
 336         /* Synchronize subsequent queue accesses */
 337         mb();
 338
 339         /*
 340          * Grab the CPPR and the "HE" field which indicates the source
 341          * of the hypervisor interrupt (if any)
 342          */
 343         cppr = ack & 0xff;
 344         he = GETFIELD(TM_QW3_NSR_HE, (ack >> 8));
 345         switch(he) {
 346         case TM_QW3_NSR_HE_NONE: /* Nothing to see here */
 347                 break;
 348         case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */
 349                 if (cppr == 0xff)
 350                         return;
 351                 /* Mark the priority pending */
 352                 xc->pending_prio |= 1 << cppr;
 353
 354                 /*
 355                  * A new interrupt should never have a CPPR less favored
 356                  * than our current one.
 357                  */
 358                 if (cppr >= xc->cppr)
 359                         pr_err("CPU %d odd ack CPPR, got %d at %d\n",
 360                                smp_processor_id(), cppr, xc->cppr);
 361
 362                 /* Update our idea of what the CPPR is */
 363                 xc->cppr = cppr;
 364                 break;
 365         case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */
 366         case TM_QW3_NSR_HE_LSI:  /* Legacy FW LSI (unused) */
 367                 pr_err("CPU %d got unexpected interrupt type HE=%d\n",
 368                        smp_processor_id(), he);
 369                 return;
 370         }
 371 }
 372
 373 static void xive_native_eoi(u32 hw_irq)
 374 {
 375         /*
 376          * Not normally used except if specific interrupts need
 377          * a workaround on EOI.
 378          */
 379         opal_int_eoi(hw_irq);
 380 }
 381
 382 static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
 383 {
 384         s64 rc;
 385         u32 vp;
 386         __be64 vp_cam_be;
 387         u64 vp_cam;
 388
 389         if (xive_pool_vps == XIVE_INVALID_VP)
 390                 return;
 391
 392         /* Check if pool VP already active, if it is, pull it */
 393         if (in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2) & TM_QW2W2_VP)
 394                 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
 395
 396         /* Enable the pool VP */
 397         vp = xive_pool_vps + cpu;
 398         pr_debug("CPU %d setting up pool VP 0x%x\n", cpu, vp);
 399         for (;;) {
 400                 rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0);
 401                 if (rc != OPAL_BUSY)
 402                         break;
 403                 msleep(1);
 404         }
 405         if (rc) {
 406                 pr_err("Failed to enable pool VP on CPU %d\n", cpu);
 407                 return;
 408         }
 409
 410         /* Grab it's CAM value */
 411         rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL);
 412         if (rc) {
 413                 pr_err("Failed to get pool VP info CPU %d\n", cpu);
 414                 return;
 415         }
 416         vp_cam = be64_to_cpu(vp_cam_be);
 417
 418         pr_debug("VP CAM = %llx\n", vp_cam);
 419
 420         /* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */
 421         pr_debug("(Old HW value: %08x)\n",
 422                  in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
 423         out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff);
 424         out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2,
 425                  TM_QW2W2_VP | vp_cam);
 426         pr_debug("(New HW value: %08x)\n",
 427                  in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
 428 }
 429
 430 static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
 431 {
 432         s64 rc;
 433         u32 vp;
 434
 435         if (xive_pool_vps == XIVE_INVALID_VP)
 436                 return;
 437
 438         /* Pull the pool VP from the CPU */
 439         in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
 440
 441         /* Disable it */
 442         vp = xive_pool_vps + cpu;
 443         for (;;) {
 444                 rc = opal_xive_set_vp_info(vp, 0, 0);
 445                 if (rc != OPAL_BUSY)
 446                         break;
 447                 msleep(1);
 448         }
 449 }
 450
 451 void xive_native_sync_source(u32 hw_irq)
 452 {
 453         opal_xive_sync(XIVE_SYNC_EAS, hw_irq);
 454 }
 455 EXPORT_SYMBOL_GPL(xive_native_sync_source);
 456
 457 static const struct xive_ops xive_native_ops = {
 458         .populate_irq_data      = xive_native_populate_irq_data,
 459         .configure_irq          = xive_native_configure_irq,
 460         .setup_queue            = xive_native_setup_queue,
 461         .cleanup_queue          = xive_native_cleanup_queue,
 462         .match                  = xive_native_match,
 463         .shutdown               = xive_native_shutdown,
 464         .update_pending         = xive_native_update_pending,
 465         .eoi                    = xive_native_eoi,
 466         .setup_cpu              = xive_native_setup_cpu,
 467         .teardown_cpu           = xive_native_teardown_cpu,
 468         .sync_source            = xive_native_sync_source,
 469 #ifdef CONFIG_SMP
 470         .get_ipi                = xive_native_get_ipi,
 471         .put_ipi                = xive_native_put_ipi,
 472 #endif /* CONFIG_SMP */
 473         .name                   = "native",
 474 };
 475
 476 static bool xive_parse_provisioning(struct device_node *np)
 477 {
 478         int rc;
 479
 480         if (of_property_read_u32(np, "ibm,xive-provision-page-size",
 481                                  &xive_provision_size) < 0)
 482                 return true;
 483         rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4);
 484         if (rc < 0) {
 485                 pr_err("Error %d getting provision chips array\n", rc);
 486                 return false;
 487         }
 488         xive_provision_chip_count = rc;
 489         if (rc == 0)
 490                 return true;
 491
 492         xive_provision_chips = kzalloc(4 * xive_provision_chip_count,
 493                                        GFP_KERNEL);
 494         if (WARN_ON(!xive_provision_chips))
 495                 return false;
 496
 497         rc = of_property_read_u32_array(np, "ibm,xive-provision-chips",
 498                                         xive_provision_chips,
 499                                         xive_provision_chip_count);
 500         if (rc < 0) {
 501                 pr_err("Error %d reading provision chips array\n", rc);
 502                 return false;
 503         }
 504
 505         xive_provision_cache = kmem_cache_create("xive-provision",
 506                                                  xive_provision_size,
 507                                                  xive_provision_size,
 508                                                  0, NULL);
 509         if (!xive_provision_cache) {
 510                 pr_err("Failed to allocate provision cache\n");
 511                 return false;
 512         }
 513         return true;
 514 }
 515
 516 static void xive_native_setup_pools(void)
 517 {
 518         /* Allocate a pool big enough */
 519         pr_debug("XIVE: Allocating VP block for pool size %u\n", nr_cpu_ids);
 520
 521         xive_pool_vps = xive_native_alloc_vp_block(nr_cpu_ids);
 522         if (WARN_ON(xive_pool_vps == XIVE_INVALID_VP))
 523                 pr_err("XIVE: Failed to allocate pool VP, KVM might not function\n");
 524
 525         pr_debug("XIVE: Pool VPs allocated at 0x%x for %u max CPUs\n",
 526                  xive_pool_vps, nr_cpu_ids);
 527 }
 528
 529 u32 xive_native_default_eq_shift(void)
 530 {
 531         return xive_queue_shift;
 532 }
 533 EXPORT_SYMBOL_GPL(xive_native_default_eq_shift);
 534
 535 bool __init xive_native_init(void)
 536 {
 537         struct device_node *np;
 538         struct resource r;
 539         void __iomem *tima;
 540         struct property *prop;
 541         u8 max_prio = 7;
 542         const __be32 *p;
 543         u32 val, cpu;
 544         s64 rc;
 545
 546         if (xive_cmdline_disabled)
 547                 return false;
 548
 549         pr_devel("xive_native_init()\n");
 550         np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe");
 551         if (!np) {
 552                 pr_devel("not found !\n");
 553                 return false;
 554         }
 555         pr_devel("Found %pOF\n", np);
 556
 557         /* Resource 1 is HV window */
 558         if (of_address_to_resource(np, 1, &r)) {
 559                 pr_err("Failed to get thread mgmnt area resource\n");
 560                 return false;
 561         }
 562         tima = ioremap(r.start, resource_size(&r));
 563         if (!tima) {
 564                 pr_err("Failed to map thread mgmnt area\n");
 565                 return false;
 566         }
 567
 568         /* Read number of priorities */
 569         if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0)
 570                 max_prio = val - 1;
 571
 572         /* Iterate the EQ sizes and pick one */
 573         of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) {
 574                 xive_queue_shift = val;
 575                 if (val == PAGE_SHIFT)
 576                         break;
 577         }
 578
 579         /* Do we support single escalation */
 580         if (of_get_property(np, "single-escalation-support", NULL) != NULL)
 581                 xive_has_single_esc = true;
 582
 583         /* Configure Thread Management areas for KVM */
 584         for_each_possible_cpu(cpu)
 585                 kvmppc_set_xive_tima(cpu, r.start, tima);
 586
 587         /* Grab size of provisionning pages */
 588         xive_parse_provisioning(np);
 589
 590         /* Switch the XIVE to exploitation mode */
 591         rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL);
 592         if (rc) {
 593                 pr_err("Switch to exploitation mode failed with error %lld\n", rc);
 594                 return false;
 595         }
 596
 597         /* Setup some dummy HV pool VPs */
 598         xive_native_setup_pools();
 599
 600         /* Initialize XIVE core with our backend */
 601         if (!xive_core_init(&xive_native_ops, tima, TM_QW3_HV_PHYS,
 602                             max_prio)) {
 603                 opal_xive_reset(OPAL_XIVE_MODE_EMU);
 604                 return false;
 605         }
 606         pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
 607         return true;
 608 }
 609
 610 static bool xive_native_provision_pages(void)
 611 {
 612         u32 i;
 613         void *p;
 614
 615         for (i = 0; i < xive_provision_chip_count; i++) {
 616                 u32 chip = xive_provision_chips[i];
 617
 618                 /*
 619                  * XXX TODO: Try to make the allocation local to the node where
 620                  * the chip resides.
 621                  */
 622                 p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL);
 623                 if (!p) {
 624                         pr_err("Failed to allocate provisioning page\n");
 625                         return false;
 626                 }
 627                 opal_xive_donate_page(chip, __pa(p));
 628         }
 629         return true;
 630 }
 631
 632 u32 xive_native_alloc_vp_block(u32 max_vcpus)
 633 {
 634         s64 rc;
 635         u32 order;
 636
 637         order = fls(max_vcpus) - 1;
 638         if (max_vcpus > (1 << order))
 639                 order++;
 640
 641         pr_debug("VP block alloc, for max VCPUs %d use order %d\n",
 642                  max_vcpus, order);
 643
 644         for (;;) {
 645                 rc = opal_xive_alloc_vp_block(order);
 646                 switch (rc) {
 647                 case OPAL_BUSY:
 648                         msleep(1);
 649                         break;
 650                 case OPAL_XIVE_PROVISIONING:
 651                         if (!xive_native_provision_pages())
 652                                 return XIVE_INVALID_VP;
 653                         break;
 654                 default:
 655                         if (rc < 0) {
 656                                 pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n",
 657                                        order, rc);
 658                                 return XIVE_INVALID_VP;
 659                         }
 660                         return rc;
 661                 }
 662         }
 663 }
 664 EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block);
 665
 666 void xive_native_free_vp_block(u32 vp_base)
 667 {
 668         s64 rc;
 669
 670         if (vp_base == XIVE_INVALID_VP)
 671                 return;
 672
 673         rc = opal_xive_free_vp_block(vp_base);
 674         if (rc < 0)
 675                 pr_warn("OPAL error %lld freeing VP block\n", rc);
 676 }
 677 EXPORT_SYMBOL_GPL(xive_native_free_vp_block);
 678
 679 int xive_native_enable_vp(u32 vp_id, bool single_escalation)
 680 {
 681         s64 rc;
 682         u64 flags = OPAL_XIVE_VP_ENABLED;
 683
 684         if (single_escalation)
 685                 flags |= OPAL_XIVE_VP_SINGLE_ESCALATION;
 686         for (;;) {
 687                 rc = opal_xive_set_vp_info(vp_id, flags, 0);
 688                 if (rc != OPAL_BUSY)
 689                         break;
 690                 msleep(1);
 691         }
 692         return rc ? -EIO : 0;
 693 }
 694 EXPORT_SYMBOL_GPL(xive_native_enable_vp);
 695
 696 int xive_native_disable_vp(u32 vp_id)
 697 {
 698         s64 rc;
 699
 700         for (;;) {
 701                 rc = opal_xive_set_vp_info(vp_id, 0, 0);
 702                 if (rc != OPAL_BUSY)
 703                         break;
 704                 msleep(1);
 705         }
 706         return rc ? -EIO : 0;
 707 }
 708 EXPORT_SYMBOL_GPL(xive_native_disable_vp);
 709
 710 int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id)
 711 {
 712         __be64 vp_cam_be;
 713         __be32 vp_chip_id_be;
 714         s64 rc;
 715
 716         rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be);
 717         if (rc)
 718                 return -EIO;
 719         *out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu;
 720         *out_chip_id = be32_to_cpu(vp_chip_id_be);
 721
 722         return 0;
 723 }
 724 EXPORT_SYMBOL_GPL(xive_native_get_vp_info);
 725
 726 bool xive_native_has_single_escalation(void)
 727 {
 728         return xive_has_single_esc;
 729 }
 730 EXPORT_SYMBOL_GPL(xive_native_has_single_escalation);