1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * The file intends to implement the platform dependent EEH operations on pseries.
4 * Actually, the pseries platform is built based on RTAS heavily. That means the
5 * pseries platform dependent EEH operations will be built on RTAS calls. The functions
6 * are derived from arch/powerpc/platforms/pseries/eeh.c and necessary cleanup has
9 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2011.
10 * Copyright IBM Corporation 2001, 2005, 2006
11 * Copyright Dave Engebretsen & Todd Inglett 2001
12 * Copyright Linas Vepstas 2005, 2006
15 #include <linux/atomic.h>
16 #include <linux/delay.h>
17 #include <linux/export.h>
18 #include <linux/init.h>
19 #include <linux/list.h>
21 #include <linux/pci.h>
22 #include <linux/proc_fs.h>
23 #include <linux/rbtree.h>
24 #include <linux/sched.h>
25 #include <linux/seq_file.h>
26 #include <linux/spinlock.h>
27 #include <linux/crash_dump.h>
30 #include <asm/eeh_event.h>
32 #include <asm/machdep.h>
33 #include <asm/ppc-pci.h>
36 static int pseries_eeh_get_pe_addr(struct pci_dn *pdn);
39 static int ibm_set_eeh_option;
40 static int ibm_set_slot_reset;
41 static int ibm_read_slot_reset_state;
42 static int ibm_read_slot_reset_state2;
43 static int ibm_slot_error_detail;
44 static int ibm_get_config_addr_info;
45 static int ibm_get_config_addr_info2;
46 static int ibm_configure_pe;
48 void pseries_pcibios_bus_add_device(struct pci_dev *pdev)
50 struct pci_dn *pdn = pci_get_pdn(pdev);
52 if (eeh_has_flag(EEH_FORCE_DISABLED))
55 dev_dbg(&pdev->dev, "EEH: Setting up device\n");
57 if (pdev->is_virtfn) {
58 pdn->device_id = pdev->device;
59 pdn->vendor_id = pdev->vendor;
60 pdn->class_code = pdev->class;
62 * Last allow unfreeze return code used for retrieval
63 * by user space in eeh-sysfs to show the last command
64 * completion from platform.
66 pdn->last_allow_rc = 0;
69 pseries_eeh_init_edev(pdn);
71 if (pdev->is_virtfn) {
73 * FIXME: This really should be handled by choosing the right
74 * parent PE in in pseries_eeh_init_edev().
76 struct eeh_pe *physfn_pe = pci_dev_to_eeh_dev(pdev->physfn)->pe;
77 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
79 edev->pe_config_addr = (pdn->busno << 16) | (pdn->devfn << 8);
80 eeh_pe_tree_remove(edev); /* Remove as it is adding to bus pe */
81 eeh_pe_tree_insert(edev, physfn_pe); /* Add as VF PE type */
84 eeh_probe_device(pdev);
89 * pseries_eeh_get_config_addr - Retrieve config address
91 * Retrieve the assocated config address. Actually, there're 2 RTAS
92 * function calls dedicated for the purpose. We need implement
93 * it through the new function and then the old one. Besides,
94 * you should make sure the config address is figured out from
95 * FDT node before calling the function.
97 * It's notable that zero'ed return value means invalid PE config
100 static int pseries_eeh_get_config_addr(struct pci_controller *phb, int config_addr)
105 if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) {
107 * First of all, we need to make sure there has one PE
108 * associated with the device. Otherwise, PE address is
111 ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
112 config_addr, BUID_HI(phb->buid),
113 BUID_LO(phb->buid), 1);
114 if (ret || (rets[0] == 0))
117 /* Retrieve the associated PE config address */
118 ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
119 config_addr, BUID_HI(phb->buid),
120 BUID_LO(phb->buid), 0);
122 pr_warn("%s: Failed to get address for PHB#%x-PE#%x\n",
123 __func__, phb->global_number, config_addr);
130 if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
131 ret = rtas_call(ibm_get_config_addr_info, 4, 2, rets,
132 config_addr, BUID_HI(phb->buid),
133 BUID_LO(phb->buid), 0);
135 pr_warn("%s: Failed to get address for PHB#%x-PE#%x\n",
136 __func__, phb->global_number, config_addr);
147 * pseries_eeh_phb_reset - Reset the specified PHB
148 * @phb: PCI controller
149 * @config_adddr: the associated config address
150 * @option: reset option
152 * Reset the specified PHB/PE
154 static int pseries_eeh_phb_reset(struct pci_controller *phb, int config_addr, int option)
158 /* Reset PE through RTAS call */
159 ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
160 config_addr, BUID_HI(phb->buid),
161 BUID_LO(phb->buid), option);
163 /* If fundamental-reset not supported, try hot-reset */
164 if (option == EEH_RESET_FUNDAMENTAL && ret == -8) {
165 option = EEH_RESET_HOT;
166 ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
167 config_addr, BUID_HI(phb->buid),
168 BUID_LO(phb->buid), option);
171 /* We need reset hold or settlement delay */
172 if (option == EEH_RESET_FUNDAMENTAL || option == EEH_RESET_HOT)
173 msleep(EEH_PE_RST_HOLD_TIME);
175 msleep(EEH_PE_RST_SETTLE_TIME);
181 * pseries_eeh_phb_configure_bridge - Configure PCI bridges in the indicated PE
182 * @phb: PCI controller
183 * @config_adddr: the associated config address
185 * The function will be called to reconfigure the bridges included
186 * in the specified PE so that the mulfunctional PE would be recovered
189 static int pseries_eeh_phb_configure_bridge(struct pci_controller *phb, int config_addr)
192 /* Waiting 0.2s maximum before skipping configuration */
195 while (max_wait > 0) {
196 ret = rtas_call(ibm_configure_pe, 3, 1, NULL,
197 config_addr, BUID_HI(phb->buid),
206 * If RTAS returns a delay value that's above 100ms, cut it
207 * down to 100ms in case firmware made a mistake. For more
208 * on how these delay values work see rtas_busy_delay_time
210 if (ret > RTAS_EXTENDED_DELAY_MIN+2 &&
211 ret <= RTAS_EXTENDED_DELAY_MAX)
212 ret = RTAS_EXTENDED_DELAY_MIN+2;
214 max_wait -= rtas_busy_delay_time(ret);
219 rtas_busy_delay(ret);
222 pr_warn("%s: Unable to configure bridge PHB#%x-PE#%x (%d)\n",
223 __func__, phb->global_number, config_addr, ret);
224 /* PAPR defines -3 as "Parameter Error" for this function: */
232 * Buffer for reporting slot-error-detail rtas calls. Its here
233 * in BSS, and not dynamically alloced, so that it ends up in
234 * RMO where RTAS can access it.
236 static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX];
237 static DEFINE_SPINLOCK(slot_errbuf_lock);
238 static int eeh_error_buf_size;
241 * pseries_eeh_init - EEH platform dependent initialization
243 * EEH platform dependent initialization on pseries.
245 static int pseries_eeh_init(void)
247 struct pci_controller *phb;
249 int addr, config_addr;
251 /* figure out EEH RTAS function call tokens */
252 ibm_set_eeh_option = rtas_token("ibm,set-eeh-option");
253 ibm_set_slot_reset = rtas_token("ibm,set-slot-reset");
254 ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2");
255 ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state");
256 ibm_slot_error_detail = rtas_token("ibm,slot-error-detail");
257 ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2");
258 ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info");
259 ibm_configure_pe = rtas_token("ibm,configure-pe");
262 * ibm,configure-pe and ibm,configure-bridge have the same semantics,
263 * however ibm,configure-pe can be faster. If we can't find
264 * ibm,configure-pe then fall back to using ibm,configure-bridge.
266 if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE)
267 ibm_configure_pe = rtas_token("ibm,configure-bridge");
270 * Necessary sanity check. We needn't check "get-config-addr-info"
271 * and its variant since the old firmware probably support address
272 * of domain/bus/slot/function for EEH RTAS operations.
274 if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE ||
275 ibm_set_slot_reset == RTAS_UNKNOWN_SERVICE ||
276 (ibm_read_slot_reset_state2 == RTAS_UNKNOWN_SERVICE &&
277 ibm_read_slot_reset_state == RTAS_UNKNOWN_SERVICE) ||
278 ibm_slot_error_detail == RTAS_UNKNOWN_SERVICE ||
279 ibm_configure_pe == RTAS_UNKNOWN_SERVICE) {
280 pr_info("EEH functionality not supported\n");
284 /* Initialize error log lock and size */
285 spin_lock_init(&slot_errbuf_lock);
286 eeh_error_buf_size = rtas_token("rtas-error-log-max");
287 if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) {
288 pr_info("%s: unknown EEH error log size\n",
290 eeh_error_buf_size = 1024;
291 } else if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) {
292 pr_info("%s: EEH error log size %d exceeds the maximal %d\n",
293 __func__, eeh_error_buf_size, RTAS_ERROR_LOG_MAX);
294 eeh_error_buf_size = RTAS_ERROR_LOG_MAX;
297 /* Set EEH probe mode */
298 eeh_add_flag(EEH_PROBE_MODE_DEVTREE | EEH_ENABLE_IO_FOR_LOG);
300 /* Set EEH machine dependent code */
301 ppc_md.pcibios_bus_add_device = pseries_pcibios_bus_add_device;
303 if (is_kdump_kernel() || reset_devices) {
304 pr_info("Issue PHB reset ...\n");
305 list_for_each_entry(phb, &hose_list, list_node) {
306 pdn = list_first_entry(&PCI_DN(phb->dn)->child_list, struct pci_dn, list);
307 addr = (pdn->busno << 16) | (pdn->devfn << 8);
308 config_addr = pseries_eeh_get_config_addr(phb, addr);
309 /* invalid PE config addr */
310 if (config_addr == 0)
313 pseries_eeh_phb_reset(phb, config_addr, EEH_RESET_FUNDAMENTAL);
314 pseries_eeh_phb_reset(phb, config_addr, EEH_RESET_DEACTIVATE);
315 pseries_eeh_phb_configure_bridge(phb, config_addr);
322 static int pseries_eeh_cap_start(struct pci_dn *pdn)
329 rtas_read_config(pdn, PCI_STATUS, 2, &status);
330 if (!(status & PCI_STATUS_CAP_LIST))
333 return PCI_CAPABILITY_LIST;
337 static int pseries_eeh_find_cap(struct pci_dn *pdn, int cap)
339 int pos = pseries_eeh_cap_start(pdn);
340 int cnt = 48; /* Maximal number of capabilities */
347 rtas_read_config(pdn, pos, 1, &pos);
351 rtas_read_config(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
356 pos += PCI_CAP_LIST_NEXT;
362 static int pseries_eeh_find_ecap(struct pci_dn *pdn, int cap)
364 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
367 int ttl = (4096 - 256) / 8;
369 if (!edev || !edev->pcie_cap)
371 if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
377 if (PCI_EXT_CAP_ID(header) == cap && pos)
380 pos = PCI_EXT_CAP_NEXT(header);
384 if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
392 * pseries_eeh_pe_get_parent - Retrieve the parent PE
395 * The whole PEs existing in the system are organized as hierarchy
396 * tree. The function is used to retrieve the parent PE according
397 * to the parent EEH device.
399 static struct eeh_pe *pseries_eeh_pe_get_parent(struct eeh_dev *edev)
401 struct eeh_dev *parent;
402 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
405 * It might have the case for the indirect parent
406 * EEH device already having associated PE, but
407 * the direct parent EEH device doesn't have yet.
410 pdn = pci_get_pdn(edev->physfn);
412 pdn = pdn ? pdn->parent : NULL;
414 /* We're poking out of PCI territory */
415 parent = pdn_to_eeh_dev(pdn);
429 * pseries_eeh_init_edev - initialise the eeh_dev and eeh_pe for a pci_dn
431 * @pdn: PCI device node
433 * When we discover a new PCI device via the device-tree we create a
434 * corresponding pci_dn and we allocate, but don't initialise, an eeh_dev.
435 * This function takes care of the initialisation and inserts the eeh_dev
436 * into the correct eeh_pe. If no eeh_pe exists we'll allocate one.
438 void pseries_eeh_init_edev(struct pci_dn *pdn)
440 struct eeh_dev *edev;
446 if (WARN_ON_ONCE(!eeh_has_flag(EEH_PROBE_MODE_DEVTREE)))
450 * Find the eeh_dev for this pdn. The storage for the eeh_dev was
451 * allocated at the same time as the pci_dn.
453 * XXX: We should probably re-visit that.
455 edev = pdn_to_eeh_dev(pdn);
460 * If ->pe is set then we've already probed this device. We hit
461 * this path when a pci_dev is removed and rescanned while recovering
462 * a PE (i.e. for devices where the driver doesn't support error
468 /* Check class/vendor/device IDs */
469 if (!pdn->vendor_id || !pdn->device_id || !pdn->class_code)
472 /* Skip for PCI-ISA bridge */
473 if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA)
476 eeh_edev_dbg(edev, "Probing device\n");
479 * Update class code and mode of eeh device. We need
480 * correctly reflects that current device is root port
481 * or PCIe switch downstream port.
483 edev->pcix_cap = pseries_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
484 edev->pcie_cap = pseries_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
485 edev->aer_cap = pseries_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
486 edev->mode &= 0xFFFFFF00;
487 if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
488 edev->mode |= EEH_DEV_BRIDGE;
489 if (edev->pcie_cap) {
490 rtas_read_config(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
492 pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
493 if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
494 edev->mode |= EEH_DEV_ROOT_PORT;
495 else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
496 edev->mode |= EEH_DEV_DS_PORT;
500 /* Initialize the fake PE */
501 memset(&pe, 0, sizeof(struct eeh_pe));
503 pe.config_addr = (pdn->busno << 16) | (pdn->devfn << 8);
505 /* Enable EEH on the device */
506 eeh_edev_dbg(edev, "Enabling EEH on device\n");
507 ret = eeh_ops->set_option(&pe, EEH_OPT_ENABLE);
509 eeh_edev_dbg(edev, "EEH failed to enable on device (code %d)\n", ret);
511 struct eeh_pe *parent;
513 /* Retrieve PE address */
514 edev->pe_config_addr = pseries_eeh_get_pe_addr(pdn);
515 pe.addr = edev->pe_config_addr;
517 /* Some older systems (Power4) allow the ibm,set-eeh-option
518 * call to succeed even on nodes where EEH is not supported.
519 * Verify support explicitly.
521 ret = eeh_ops->get_state(&pe, NULL);
522 if (ret > 0 && ret != EEH_STATE_NOT_SUPPORT)
526 * This device doesn't support EEH, but it may have an
527 * EEH parent. In this case any error on the device will
528 * freeze the PE of it's upstream bridge, so added it to
531 parent = pseries_eeh_pe_get_parent(edev);
532 if (parent && !enable)
533 edev->pe_config_addr = parent->addr;
535 if (enable || parent) {
536 eeh_add_flag(EEH_ENABLED);
537 eeh_pe_tree_insert(edev, parent);
539 eeh_edev_dbg(edev, "EEH is %s on device (code %d)\n",
540 (enable ? "enabled" : "unsupported"), ret);
543 /* Save memory bars */
547 static struct eeh_dev *pseries_eeh_probe(struct pci_dev *pdev)
549 struct eeh_dev *edev;
552 pdn = pci_get_pdn_by_devfn(pdev->bus, pdev->devfn);
557 * If the system supports EEH on this device then the eeh_dev was
558 * configured and inserted into a PE in pseries_eeh_init_edev()
560 edev = pdn_to_eeh_dev(pdn);
561 if (!edev || !edev->pe)
568 * pseries_eeh_init_edev_recursive - Enable EEH for the indicated device
569 * @pdn: PCI device node
571 * This routine must be used to perform EEH initialization for the
572 * indicated PCI device that was added after system boot (e.g.
575 void pseries_eeh_init_edev_recursive(struct pci_dn *pdn)
582 list_for_each_entry(n, &pdn->child_list, list)
583 pseries_eeh_init_edev_recursive(n);
585 pseries_eeh_init_edev(pdn);
587 EXPORT_SYMBOL_GPL(pseries_eeh_init_edev_recursive);
590 * pseries_eeh_set_option - Initialize EEH or MMIO/DMA reenable
592 * @option: operation to be issued
594 * The function is used to control the EEH functionality globally.
595 * Currently, following options are support according to PAPR:
596 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
598 static int pseries_eeh_set_option(struct eeh_pe *pe, int option)
604 * When we're enabling or disabling EEH functioality on
605 * the particular PE, the PE config address is possibly
606 * unavailable. Therefore, we have to figure it out from
610 case EEH_OPT_DISABLE:
612 case EEH_OPT_THAW_MMIO:
613 case EEH_OPT_THAW_DMA:
614 config_addr = pe->config_addr;
616 config_addr = pe->addr;
618 case EEH_OPT_FREEZE_PE:
622 pr_err("%s: Invalid option %d\n", __func__, option);
626 ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
627 config_addr, BUID_HI(pe->phb->buid),
628 BUID_LO(pe->phb->buid), option);
634 * pseries_eeh_get_pe_addr - Retrieve PE address
637 * Retrieve the assocated PE address. Actually, there're 2 RTAS
638 * function calls dedicated for the purpose. We need implement
639 * it through the new function and then the old one. Besides,
640 * you should make sure the config address is figured out from
641 * FDT node before calling the function.
643 * It's notable that zero'ed return value means invalid PE config
646 static int pseries_eeh_get_pe_addr(struct pci_dn *pdn)
648 int config_addr = rtas_config_addr(pdn->busno, pdn->devfn, 0);
649 unsigned long buid = pdn->phb->buid;
653 if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) {
655 * First of all, we need to make sure there has one PE
656 * associated with the device. Otherwise, PE address is
659 ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
660 config_addr, BUID_HI(buid), BUID_LO(buid), 1);
661 if (ret || (rets[0] == 0))
664 /* Retrieve the associated PE config address */
665 ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
666 config_addr, BUID_HI(buid), BUID_LO(buid), 0);
668 pr_warn("%s: Failed to get address for PHB#%x-PE#%x\n",
669 __func__, pdn->phb->global_number, config_addr);
676 if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
677 ret = rtas_call(ibm_get_config_addr_info, 4, 2, rets,
678 config_addr, BUID_HI(buid), BUID_LO(buid), 0);
680 pr_warn("%s: Failed to get address for PHB#%x-PE#%x\n",
681 __func__, pdn->phb->global_number, config_addr);
692 * pseries_eeh_get_state - Retrieve PE state
694 * @delay: suggested time to wait if state is unavailable
696 * Retrieve the state of the specified PE. On RTAS compliant
697 * pseries platform, there already has one dedicated RTAS function
698 * for the purpose. It's notable that the associated PE config address
699 * might be ready when calling the function. Therefore, endeavour to
700 * use the PE config address if possible. Further more, there're 2
701 * RTAS calls for the purpose, we need to try the new one and back
702 * to the old one if the new one couldn't work properly.
704 static int pseries_eeh_get_state(struct eeh_pe *pe, int *delay)
711 /* Figure out PE config address if possible */
712 config_addr = pe->config_addr;
714 config_addr = pe->addr;
716 if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) {
717 ret = rtas_call(ibm_read_slot_reset_state2, 3, 4, rets,
718 config_addr, BUID_HI(pe->phb->buid),
719 BUID_LO(pe->phb->buid));
720 } else if (ibm_read_slot_reset_state != RTAS_UNKNOWN_SERVICE) {
721 /* Fake PE unavailable info */
723 ret = rtas_call(ibm_read_slot_reset_state, 3, 3, rets,
724 config_addr, BUID_HI(pe->phb->buid),
725 BUID_LO(pe->phb->buid));
727 return EEH_STATE_NOT_SUPPORT;
733 /* Parse the result out */
735 return EEH_STATE_NOT_SUPPORT;
739 result = EEH_STATE_MMIO_ACTIVE |
740 EEH_STATE_DMA_ACTIVE;
743 result = EEH_STATE_RESET_ACTIVE |
744 EEH_STATE_MMIO_ACTIVE |
745 EEH_STATE_DMA_ACTIVE;
751 result = EEH_STATE_MMIO_ENABLED;
757 result = EEH_STATE_UNAVAILABLE;
759 result = EEH_STATE_NOT_SUPPORT;
763 result = EEH_STATE_NOT_SUPPORT;
770 * pseries_eeh_reset - Reset the specified PE
772 * @option: reset option
774 * Reset the specified PE
776 static int pseries_eeh_reset(struct eeh_pe *pe, int option)
780 /* Figure out PE address */
781 config_addr = pe->config_addr;
783 config_addr = pe->addr;
785 return pseries_eeh_phb_reset(pe->phb, config_addr, option);
789 * pseries_eeh_get_log - Retrieve error log
791 * @severity: temporary or permanent error log
792 * @drv_log: driver log to be combined with retrieved error log
793 * @len: length of driver log
795 * Retrieve the temporary or permanent error from the PE.
796 * Actually, the error will be retrieved through the dedicated
799 static int pseries_eeh_get_log(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len)
805 spin_lock_irqsave(&slot_errbuf_lock, flags);
806 memset(slot_errbuf, 0, eeh_error_buf_size);
808 /* Figure out the PE address */
809 config_addr = pe->config_addr;
811 config_addr = pe->addr;
813 ret = rtas_call(ibm_slot_error_detail, 8, 1, NULL, config_addr,
814 BUID_HI(pe->phb->buid), BUID_LO(pe->phb->buid),
815 virt_to_phys(drv_log), len,
816 virt_to_phys(slot_errbuf), eeh_error_buf_size,
819 log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0);
820 spin_unlock_irqrestore(&slot_errbuf_lock, flags);
826 * pseries_eeh_configure_bridge - Configure PCI bridges in the indicated PE
830 static int pseries_eeh_configure_bridge(struct eeh_pe *pe)
834 /* Figure out the PE address */
835 config_addr = pe->config_addr;
837 config_addr = pe->addr;
839 return pseries_eeh_phb_configure_bridge(pe->phb, config_addr);
843 * pseries_eeh_read_config - Read PCI config space
844 * @edev: EEH device handle
845 * @where: PCI config space offset
846 * @size: size to read
849 * Read config space from the speicifed device
851 static int pseries_eeh_read_config(struct eeh_dev *edev, int where, int size, u32 *val)
853 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
855 return rtas_read_config(pdn, where, size, val);
859 * pseries_eeh_write_config - Write PCI config space
860 * @edev: EEH device handle
861 * @where: PCI config space offset
862 * @size: size to write
863 * @val: value to be written
865 * Write config space to the specified device
867 static int pseries_eeh_write_config(struct eeh_dev *edev, int where, int size, u32 val)
869 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
871 return rtas_write_config(pdn, where, size, val);
874 #ifdef CONFIG_PCI_IOV
875 int pseries_send_allow_unfreeze(struct pci_dn *pdn,
876 u16 *vf_pe_array, int cur_vfs)
879 int ibm_allow_unfreeze = rtas_token("ibm,open-sriov-allow-unfreeze");
880 unsigned long buid, addr;
882 addr = rtas_config_addr(pdn->busno, pdn->devfn, 0);
883 buid = pdn->phb->buid;
884 spin_lock(&rtas_data_buf_lock);
885 memcpy(rtas_data_buf, vf_pe_array, RTAS_DATA_BUF_SIZE);
886 rc = rtas_call(ibm_allow_unfreeze, 5, 1, NULL,
890 rtas_data_buf, cur_vfs * sizeof(u16));
891 spin_unlock(&rtas_data_buf_lock);
893 pr_warn("%s: Failed to allow unfreeze for PHB#%x-PE#%lx, rc=%x\n",
895 pdn->phb->global_number, addr, rc);
899 static int pseries_call_allow_unfreeze(struct eeh_dev *edev)
901 int cur_vfs = 0, rc = 0, vf_index, bus, devfn, vf_pe_num;
902 struct pci_dn *pdn, *tmp, *parent, *physfn_pdn;
905 vf_pe_array = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
908 if (pci_num_vf(edev->physfn ? edev->physfn : edev->pdev)) {
909 if (edev->pdev->is_physfn) {
910 cur_vfs = pci_num_vf(edev->pdev);
911 pdn = eeh_dev_to_pdn(edev);
912 parent = pdn->parent;
913 for (vf_index = 0; vf_index < cur_vfs; vf_index++)
914 vf_pe_array[vf_index] =
915 cpu_to_be16(pdn->pe_num_map[vf_index]);
916 rc = pseries_send_allow_unfreeze(pdn, vf_pe_array,
918 pdn->last_allow_rc = rc;
919 for (vf_index = 0; vf_index < cur_vfs; vf_index++) {
920 list_for_each_entry_safe(pdn, tmp,
923 bus = pci_iov_virtfn_bus(edev->pdev,
925 devfn = pci_iov_virtfn_devfn(edev->pdev,
927 if (pdn->busno != bus ||
930 pdn->last_allow_rc = rc;
934 pdn = pci_get_pdn(edev->pdev);
935 physfn_pdn = pci_get_pdn(edev->physfn);
937 vf_pe_num = physfn_pdn->pe_num_map[edev->vf_index];
938 vf_pe_array[0] = cpu_to_be16(vf_pe_num);
939 rc = pseries_send_allow_unfreeze(physfn_pdn,
941 pdn->last_allow_rc = rc;
949 static int pseries_notify_resume(struct eeh_dev *edev)
954 if (rtas_token("ibm,open-sriov-allow-unfreeze") == RTAS_UNKNOWN_SERVICE)
957 if (edev->pdev->is_physfn || edev->pdev->is_virtfn)
958 return pseries_call_allow_unfreeze(edev);
964 static struct eeh_ops pseries_eeh_ops = {
966 .init = pseries_eeh_init,
967 .probe = pseries_eeh_probe,
968 .set_option = pseries_eeh_set_option,
969 .get_state = pseries_eeh_get_state,
970 .reset = pseries_eeh_reset,
971 .get_log = pseries_eeh_get_log,
972 .configure_bridge = pseries_eeh_configure_bridge,
974 .read_config = pseries_eeh_read_config,
975 .write_config = pseries_eeh_write_config,
977 .restore_config = NULL, /* NB: configure_bridge() does this */
978 #ifdef CONFIG_PCI_IOV
979 .notify_resume = pseries_notify_resume
984 * eeh_pseries_init - Register platform dependent EEH operations
986 * EEH initialization on pseries platform. This function should be
987 * called before any EEH related functions.
989 static int __init eeh_pseries_init(void)
993 ret = eeh_ops_register(&pseries_eeh_ops);
995 pr_info("EEH: pSeries platform initialized\n");
997 pr_info("EEH: pSeries platform initialization failure (%d)\n",
1002 machine_early_initcall(pseries, eeh_pseries_init);