2 * This file contains sleep low-level functions for PowerBook G3.
3 * Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
4 * and Paul Mackerras (paulus@samba.org).
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
13 #include <asm/processor.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/cputable.h>
17 #include <asm/cache.h>
18 #include <asm/thread_info.h>
19 #include <asm/asm-offsets.h>
21 #include <asm/feature-fixups.h>
23 #define MAGIC 0x4c617273 /* 'Lars' */
26 * Structure for storing CPU registers on the stack.
32 #define SL_SPRG0 0x10 /* 4 sprg's */
44 #define SL_R12 0x70 /* r12 to r31 */
45 #define SL_SIZE (SL_R12 + 80)
50 #if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC) || \
51 (defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32))
53 /* This gets called by via-pmu.c late during the sleep process.
54 * The PMU was already send the sleep command and will shut us down
55 * soon. We need to save all that is needed and setup the wakeup
56 * vector that will be called by the ROM on wakeup
58 _GLOBAL(low_sleep_handler)
76 /* Get a stable timebase and save it */
93 stw r4,SL_SPRG0+12(r1)
103 stw r4,SL_DBAT1+4(r1)
107 stw r4,SL_DBAT2+4(r1)
111 stw r4,SL_DBAT3+4(r1)
115 stw r4,SL_IBAT0+4(r1)
119 stw r4,SL_IBAT1+4(r1)
123 stw r4,SL_IBAT2+4(r1)
127 stw r4,SL_IBAT3+4(r1)
129 /* Backup various CPU config stuffs */
132 /* The ROM can wake us up via 2 different vectors:
133 * - On wallstreet & lombard, we must write a magic
134 * value 'Lars' at address 4 and a pointer to a
135 * memory location containing the PC to resume from
137 * - On Core99, we must store the wakeup vector at
138 * address 0x80 and eventually it's parameters
139 * at address 0x84. I've have some trouble with those
140 * parameters however and I no longer use them.
142 lis r5,grackle_wake_up@ha
143 addi r5,r5,grackle_wake_up@l
153 /* Setup stuffs at 0x80-0x84 for Core99 */
154 lis r3,core99_wake_up@ha
155 addi r3,r3,core99_wake_up@l
159 /* Store a pointer to our backup storage into
162 lis r3,sleep_storage@ha
163 addi r3,r3,sleep_storage@l
168 /* Flush & disable all caches */
169 bl flush_disable_caches
171 /* Turn off data relocation. */
172 mfmsr r3 /* Save MSR in r7 */
173 rlwinm r3,r3,0,28,26 /* Turn off DR bit */
179 /* Flush any pending L2 data prefetches to work around HW bug */
182 lwz r0,0(r3) /* perform cache-inhibited load to ROM */
183 sync /* (caches are disabled at this point) */
184 END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
187 * Set the HID0 and MSR for sleep.
190 rlwinm r2,r2,0,10,7 /* clear doze, nap */
191 oris r2,r2,HID0_SLEEP@h
197 /* This loop puts us back to sleep in case we have a spurrious
198 * wakeup so that the host bridge properly stays asleep. The
199 * CPU will be turned off, either after a known time (about 1
200 * second) on wallstreet & lombard, or as soon as the CPU enters
201 * SLEEP mode on core99
211 * Here is the resume code.
216 * Core99 machines resume here
217 * r4 has the physical address of SL_PC(sp) (unused)
219 _GLOBAL(core99_wake_up)
220 /* Make sure HID0 no longer contains any sleep bit and that data cache
224 rlwinm r3,r3,0,11,7 /* clear SLEEP, NAP, DOZE bits */
225 rlwinm 3,r3,0,18,15 /* clear DCE, ICE */
232 ori r3,r3,MSR_EE|MSR_IP
233 xori r3,r3,MSR_EE|MSR_IP
240 /* Recover sleep storage */
241 lis r3,sleep_storage@ha
242 addi r3,r3,sleep_storage@l
246 /* Pass thru to older resume code ... */
248 * Here is the resume code for older machines.
249 * r1 has the physical address of SL_PC(sp).
254 /* Restore the kernel's segment registers before
255 * we do any r1 memory access as we are not sure they
256 * are in a sane state above the first 256Mb region
258 li r0,16 /* load up segment register values */
259 mtctr r0 /* for context 0 */
260 lis r3,0x2000 /* Ku = 1, VSID = 0 */
263 addi r3,r3,0x111 /* increment VSID */
264 addis r4,r4,0x1000 /* address of next segment */
271 /* Restore various CPU config stuffs */
272 bl __restore_cpu_setup
274 /* Make sure all FPRs have been initialized */
276 bl __init_fpu_registers
278 /* Invalidate & enable L1 cache, we don't care about
279 * whatever the ROM may have tried to write to memory
283 /* Restore the BATs, and SDR1. Then we can turn on the MMU. */
288 lwz r4,SL_SPRG0+4(r1)
290 lwz r4,SL_SPRG0+8(r1)
292 lwz r4,SL_SPRG0+12(r1)
297 lwz r4,SL_DBAT0+4(r1)
301 lwz r4,SL_DBAT1+4(r1)
305 lwz r4,SL_DBAT2+4(r1)
309 lwz r4,SL_DBAT3+4(r1)
313 lwz r4,SL_IBAT0+4(r1)
317 lwz r4,SL_IBAT1+4(r1)
321 lwz r4,SL_IBAT2+4(r1)
325 lwz r4,SL_IBAT3+4(r1)
328 BEGIN_MMU_FTR_SECTION
346 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
350 1: addic. r4,r4,-0x1000
355 /* restore the MSR and turn on the MMU */
359 /* get back the stack pointer */
370 /* Restore the callee-saved registers and return */
389 #endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
392 .balign L1_CACHE_BYTES
395 .balign L1_CACHE_BYTES, 0
397 #endif /* CONFIG_6xx */