2 * Copyright (C) 2006-2007 PA Semi, Inc
4 * Common functions for DMA access on PA Semi PWRficient
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/kernel.h>
21 #include <linux/export.h>
22 #include <linux/pci.h>
23 #include <linux/slab.h>
25 #include <linux/sched.h>
27 #include <asm/pasemi_dma.h>
34 static struct pasdma_status *dma_status;
36 static void __iomem *iob_regs;
37 static void __iomem *mac_regs[6];
38 static void __iomem *dma_regs;
40 static int base_hw_irq;
42 static int num_txch, num_rxch;
44 static struct pci_dev *dma_pdev;
46 /* Bitmaps to handle allocation of channels */
48 static DECLARE_BITMAP(txch_free, MAX_TXCH);
49 static DECLARE_BITMAP(rxch_free, MAX_RXCH);
50 static DECLARE_BITMAP(flags_free, MAX_FLAGS);
51 static DECLARE_BITMAP(fun_free, MAX_FUN);
53 /* pasemi_read_iob_reg - read IOB register
54 * @reg: Register to read (offset into PCI CFG space)
56 unsigned int pasemi_read_iob_reg(unsigned int reg)
58 return in_le32(iob_regs+reg);
60 EXPORT_SYMBOL(pasemi_read_iob_reg);
62 /* pasemi_write_iob_reg - write IOB register
63 * @reg: Register to write to (offset into PCI CFG space)
64 * @val: Value to write
66 void pasemi_write_iob_reg(unsigned int reg, unsigned int val)
68 out_le32(iob_regs+reg, val);
70 EXPORT_SYMBOL(pasemi_write_iob_reg);
72 /* pasemi_read_mac_reg - read MAC register
73 * @intf: MAC interface
74 * @reg: Register to read (offset into PCI CFG space)
76 unsigned int pasemi_read_mac_reg(int intf, unsigned int reg)
78 return in_le32(mac_regs[intf]+reg);
80 EXPORT_SYMBOL(pasemi_read_mac_reg);
82 /* pasemi_write_mac_reg - write MAC register
83 * @intf: MAC interface
84 * @reg: Register to write to (offset into PCI CFG space)
85 * @val: Value to write
87 void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val)
89 out_le32(mac_regs[intf]+reg, val);
91 EXPORT_SYMBOL(pasemi_write_mac_reg);
93 /* pasemi_read_dma_reg - read DMA register
94 * @reg: Register to read (offset into PCI CFG space)
96 unsigned int pasemi_read_dma_reg(unsigned int reg)
98 return in_le32(dma_regs+reg);
100 EXPORT_SYMBOL(pasemi_read_dma_reg);
102 /* pasemi_write_dma_reg - write DMA register
103 * @reg: Register to write to (offset into PCI CFG space)
104 * @val: Value to write
106 void pasemi_write_dma_reg(unsigned int reg, unsigned int val)
108 out_le32(dma_regs+reg, val);
110 EXPORT_SYMBOL(pasemi_write_dma_reg);
112 static int pasemi_alloc_tx_chan(enum pasemi_dmachan_type type)
117 switch (type & (TXCHAN_EVT0|TXCHAN_EVT1)) {
132 bit = find_next_bit(txch_free, MAX_TXCH, start);
135 if (!test_and_clear_bit(bit, txch_free))
141 static void pasemi_free_tx_chan(int chan)
143 BUG_ON(test_bit(chan, txch_free));
144 set_bit(chan, txch_free);
147 static int pasemi_alloc_rx_chan(void)
151 bit = find_first_bit(rxch_free, MAX_RXCH);
154 if (!test_and_clear_bit(bit, rxch_free))
160 static void pasemi_free_rx_chan(int chan)
162 BUG_ON(test_bit(chan, rxch_free));
163 set_bit(chan, rxch_free);
166 /* pasemi_dma_alloc_chan - Allocate a DMA channel
167 * @type: Type of channel to allocate
168 * @total_size: Total size of structure to allocate (to allow for more
169 * room behind the structure to be used by the client)
170 * @offset: Offset in bytes from start of the total structure to the beginning
171 * of struct pasemi_dmachan. Needed when struct pasemi_dmachan is
172 * not the first member of the client structure.
174 * pasemi_dma_alloc_chan allocates a DMA channel for use by a client. The
175 * type argument specifies whether it's a RX or TX channel, and in the case
176 * of TX channels which group it needs to belong to (if any).
178 * Returns a pointer to the total structure allocated on success, NULL
181 void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type,
182 int total_size, int offset)
185 struct pasemi_dmachan *chan;
188 BUG_ON(total_size < sizeof(struct pasemi_dmachan));
190 buf = kzalloc(total_size, GFP_KERNEL);
198 switch (type & (TXCHAN|RXCHAN)) {
200 chno = pasemi_alloc_rx_chan();
202 chan->irq = irq_create_mapping(NULL,
203 base_hw_irq + num_txch + chno);
204 chan->status = &dma_status->rx_sta[chno];
207 chno = pasemi_alloc_tx_chan(type);
209 chan->irq = irq_create_mapping(NULL, base_hw_irq + chno);
210 chan->status = &dma_status->tx_sta[chno];
214 chan->chan_type = type;
218 EXPORT_SYMBOL(pasemi_dma_alloc_chan);
220 /* pasemi_dma_free_chan - Free a previously allocated channel
221 * @chan: Channel to free
223 * Frees a previously allocated channel. It will also deallocate any
224 * descriptor ring associated with the channel, if allocated.
226 void pasemi_dma_free_chan(struct pasemi_dmachan *chan)
229 pasemi_dma_free_ring(chan);
231 switch (chan->chan_type & (RXCHAN|TXCHAN)) {
233 pasemi_free_rx_chan(chan->chno);
236 pasemi_free_tx_chan(chan->chno);
242 EXPORT_SYMBOL(pasemi_dma_free_chan);
244 /* pasemi_dma_alloc_ring - Allocate descriptor ring for a channel
245 * @chan: Channel for which to allocate
246 * @ring_size: Ring size in 64-bit (8-byte) words
248 * Allocate a descriptor ring for a channel. Returns 0 on success, errno
249 * on failure. The passed in struct pasemi_dmachan is updated with the
250 * virtual and DMA addresses of the ring.
252 int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size)
254 BUG_ON(chan->ring_virt);
256 chan->ring_size = ring_size;
258 chan->ring_virt = dma_zalloc_coherent(&dma_pdev->dev,
259 ring_size * sizeof(u64),
260 &chan->ring_dma, GFP_KERNEL);
262 if (!chan->ring_virt)
267 EXPORT_SYMBOL(pasemi_dma_alloc_ring);
269 /* pasemi_dma_free_ring - Free an allocated descriptor ring for a channel
270 * @chan: Channel for which to free the descriptor ring
272 * Frees a previously allocated descriptor ring for a channel.
274 void pasemi_dma_free_ring(struct pasemi_dmachan *chan)
276 BUG_ON(!chan->ring_virt);
278 dma_free_coherent(&dma_pdev->dev, chan->ring_size * sizeof(u64),
279 chan->ring_virt, chan->ring_dma);
280 chan->ring_virt = NULL;
284 EXPORT_SYMBOL(pasemi_dma_free_ring);
286 /* pasemi_dma_start_chan - Start a DMA channel
287 * @chan: Channel to start
288 * @cmdsta: Additional CCMDSTA/TCMDSTA bits to write
290 * Enables (starts) a DMA channel with optional additional arguments.
292 void pasemi_dma_start_chan(const struct pasemi_dmachan *chan, const u32 cmdsta)
294 if (chan->chan_type == RXCHAN)
295 pasemi_write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno),
296 cmdsta | PAS_DMA_RXCHAN_CCMDSTA_EN);
298 pasemi_write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno),
299 cmdsta | PAS_DMA_TXCHAN_TCMDSTA_EN);
301 EXPORT_SYMBOL(pasemi_dma_start_chan);
303 /* pasemi_dma_stop_chan - Stop a DMA channel
304 * @chan: Channel to stop
306 * Stops (disables) a DMA channel. This is done by setting the ST bit in the
307 * CMDSTA register and waiting on the ACT (active) bit to clear, then
308 * finally disabling the whole channel.
310 * This function will only try for a short while for the channel to stop, if
311 * it doesn't it will return failure.
313 * Returns 1 on success, 0 on failure.
315 #define MAX_RETRIES 5000
316 int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan)
321 if (chan->chan_type == RXCHAN) {
322 reg = PAS_DMA_RXCHAN_CCMDSTA(chan->chno);
323 pasemi_write_dma_reg(reg, PAS_DMA_RXCHAN_CCMDSTA_ST);
324 for (retries = 0; retries < MAX_RETRIES; retries++) {
325 sta = pasemi_read_dma_reg(reg);
326 if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)) {
327 pasemi_write_dma_reg(reg, 0);
333 reg = PAS_DMA_TXCHAN_TCMDSTA(chan->chno);
334 pasemi_write_dma_reg(reg, PAS_DMA_TXCHAN_TCMDSTA_ST);
335 for (retries = 0; retries < MAX_RETRIES; retries++) {
336 sta = pasemi_read_dma_reg(reg);
337 if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)) {
338 pasemi_write_dma_reg(reg, 0);
347 EXPORT_SYMBOL(pasemi_dma_stop_chan);
349 /* pasemi_dma_alloc_buf - Allocate a buffer to use for DMA
350 * @chan: Channel to allocate for
351 * @size: Size of buffer in bytes
352 * @handle: DMA handle
354 * Allocate a buffer to be used by the DMA engine for read/write,
355 * similar to dma_alloc_coherent().
357 * Returns the virtual address of the buffer, or NULL in case of failure.
359 void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size,
362 return dma_alloc_coherent(&dma_pdev->dev, size, handle, GFP_KERNEL);
364 EXPORT_SYMBOL(pasemi_dma_alloc_buf);
366 /* pasemi_dma_free_buf - Free a buffer used for DMA
367 * @chan: Channel the buffer was allocated for
368 * @size: Size of buffer in bytes
369 * @handle: DMA handle
371 * Frees a previously allocated buffer.
373 void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
376 dma_free_coherent(&dma_pdev->dev, size, handle, GFP_KERNEL);
378 EXPORT_SYMBOL(pasemi_dma_free_buf);
380 /* pasemi_dma_alloc_flag - Allocate a flag (event) for channel synchronization
382 * Allocates a flag for use with channel synchronization (event descriptors).
383 * Returns allocated flag (0-63), < 0 on error.
385 int pasemi_dma_alloc_flag(void)
390 bit = find_next_bit(flags_free, MAX_FLAGS, 0);
391 if (bit >= MAX_FLAGS)
393 if (!test_and_clear_bit(bit, flags_free))
398 EXPORT_SYMBOL(pasemi_dma_alloc_flag);
401 /* pasemi_dma_free_flag - Deallocates a flag (event)
402 * @flag: Flag number to deallocate
404 * Frees up a flag so it can be reused for other purposes.
406 void pasemi_dma_free_flag(int flag)
408 BUG_ON(test_bit(flag, flags_free));
409 BUG_ON(flag >= MAX_FLAGS);
410 set_bit(flag, flags_free);
412 EXPORT_SYMBOL(pasemi_dma_free_flag);
415 /* pasemi_dma_set_flag - Sets a flag (event) to 1
416 * @flag: Flag number to set active
418 * Sets the flag provided to 1.
420 void pasemi_dma_set_flag(int flag)
422 BUG_ON(flag >= MAX_FLAGS);
424 pasemi_write_dma_reg(PAS_DMA_TXF_SFLG0, 1 << flag);
426 pasemi_write_dma_reg(PAS_DMA_TXF_SFLG1, 1 << flag);
428 EXPORT_SYMBOL(pasemi_dma_set_flag);
430 /* pasemi_dma_clear_flag - Sets a flag (event) to 0
431 * @flag: Flag number to set inactive
433 * Sets the flag provided to 0.
435 void pasemi_dma_clear_flag(int flag)
437 BUG_ON(flag >= MAX_FLAGS);
439 pasemi_write_dma_reg(PAS_DMA_TXF_CFLG0, 1 << flag);
441 pasemi_write_dma_reg(PAS_DMA_TXF_CFLG1, 1 << flag);
443 EXPORT_SYMBOL(pasemi_dma_clear_flag);
445 /* pasemi_dma_alloc_fun - Allocate a function engine
447 * Allocates a function engine to use for crypto/checksum offload
448 * Returns allocated engine (0-8), < 0 on error.
450 int pasemi_dma_alloc_fun(void)
455 bit = find_next_bit(fun_free, MAX_FLAGS, 0);
456 if (bit >= MAX_FLAGS)
458 if (!test_and_clear_bit(bit, fun_free))
463 EXPORT_SYMBOL(pasemi_dma_alloc_fun);
466 /* pasemi_dma_free_fun - Deallocates a function engine
467 * @flag: Engine number to deallocate
469 * Frees up a function engine so it can be used for other purposes.
471 void pasemi_dma_free_fun(int fun)
473 BUG_ON(test_bit(fun, fun_free));
474 BUG_ON(fun >= MAX_FLAGS);
475 set_bit(fun, fun_free);
477 EXPORT_SYMBOL(pasemi_dma_free_fun);
480 static void *map_onedev(struct pci_dev *p, int index)
482 struct device_node *dn;
485 dn = pci_device_to_OF_node(p);
489 ret = of_iomap(dn, index);
495 /* This is hardcoded and ugly, but we have some firmware versions
496 * that don't provide the register space in the device tree. Luckily
497 * they are at well-known locations so we can just do the math here.
499 return ioremap(0xe0000000 + (p->devfn << 12), 0x2000);
502 /* pasemi_dma_init - Initialize the PA Semi DMA library
504 * This function initializes the DMA library. It must be called before
505 * any other function in the library.
507 * Returns 0 on success, errno on failure.
509 int pasemi_dma_init(void)
511 static DEFINE_SPINLOCK(init_lock);
512 struct pci_dev *iob_pdev;
513 struct pci_dev *pdev;
515 struct device_node *dn;
516 int i, intf, err = 0;
517 unsigned long timeout;
520 if (!machine_is(pasemi))
523 spin_lock(&init_lock);
525 /* Make sure we haven't already initialized */
529 iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
532 pr_warn("Can't find I/O Bridge\n");
536 iob_regs = map_onedev(iob_pdev, 0);
538 dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
541 pr_warn("Can't find DMA controller\n");
545 dma_regs = map_onedev(dma_pdev, 0);
546 base_hw_irq = virq_to_hw(dma_pdev->irq);
548 pci_read_config_dword(dma_pdev, PAS_DMA_CAP_TXCH, &tmp);
549 num_txch = (tmp & PAS_DMA_CAP_TXCH_TCHN_M) >> PAS_DMA_CAP_TXCH_TCHN_S;
551 pci_read_config_dword(dma_pdev, PAS_DMA_CAP_RXCH, &tmp);
552 num_rxch = (tmp & PAS_DMA_CAP_RXCH_RCHN_M) >> PAS_DMA_CAP_RXCH_RCHN_S;
555 for (pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa006, NULL);
557 pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa006, pdev))
558 mac_regs[intf++] = map_onedev(pdev, 0);
562 for (pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa005, NULL);
564 pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa005, pdev))
565 mac_regs[intf++] = map_onedev(pdev, 0);
569 dn = pci_device_to_OF_node(iob_pdev);
571 err = of_address_to_resource(dn, 1, &res);
573 /* Fallback for old firmware */
574 res.start = 0xfd800000;
575 res.end = res.start + 0x1000;
577 dma_status = ioremap_cache(res.start, resource_size(&res));
578 pci_dev_put(iob_pdev);
580 for (i = 0; i < MAX_TXCH; i++)
581 __set_bit(i, txch_free);
583 for (i = 0; i < MAX_RXCH; i++)
584 __set_bit(i, rxch_free);
586 timeout = jiffies + HZ;
587 pasemi_write_dma_reg(PAS_DMA_COM_RXCMD, 0);
588 while (pasemi_read_dma_reg(PAS_DMA_COM_RXSTA) & 1) {
589 if (time_after(jiffies, timeout)) {
590 pr_warn("Warning: Could not disable RX section\n");
595 timeout = jiffies + HZ;
596 pasemi_write_dma_reg(PAS_DMA_COM_TXCMD, 0);
597 while (pasemi_read_dma_reg(PAS_DMA_COM_TXSTA) & 1) {
598 if (time_after(jiffies, timeout)) {
599 pr_warn("Warning: Could not disable TX section\n");
604 /* setup resource allocations for the different DMA sections */
605 tmp = pasemi_read_dma_reg(PAS_DMA_COM_CFG);
606 pasemi_write_dma_reg(PAS_DMA_COM_CFG, tmp | 0x18000000);
608 /* enable tx section */
609 pasemi_write_dma_reg(PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN);
611 /* enable rx section */
612 pasemi_write_dma_reg(PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN);
614 for (i = 0; i < MAX_FLAGS; i++)
615 __set_bit(i, flags_free);
617 for (i = 0; i < MAX_FUN; i++)
618 __set_bit(i, fun_free);
620 /* clear all status flags */
621 pasemi_write_dma_reg(PAS_DMA_TXF_CFLG0, 0xffffffff);
622 pasemi_write_dma_reg(PAS_DMA_TXF_CFLG1, 0xffffffff);
624 pr_info("PA Semi PWRficient DMA library initialized "
625 "(%d tx, %d rx channels)\n", num_txch, num_rxch);
628 spin_unlock(&init_lock);
631 EXPORT_SYMBOL(pasemi_dma_init);