1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2006-2010, 2012-2013 Freescale Semiconductor, Inc.
6 * Author: Andy Fleming <afleming@freescale.com>
8 * Based on 83xx/mpc8360e_pb.c by:
9 * Li Yang <LeoLi@freescale.com>
10 * Yin Olivia <Hong-hua.Yin@freescale.com>
13 * MPC85xx MDS board specific routines.
16 #include <linux/stddef.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/reboot.h>
21 #include <linux/pci.h>
22 #include <linux/kdev_t.h>
23 #include <linux/major.h>
24 #include <linux/console.h>
25 #include <linux/delay.h>
26 #include <linux/seq_file.h>
27 #include <linux/initrd.h>
28 #include <linux/fsl_devices.h>
29 #include <linux/of_platform.h>
30 #include <linux/of_device.h>
31 #include <linux/phy.h>
32 #include <linux/memblock.h>
33 #include <linux/fsl/guts.h>
35 #include <linux/atomic.h>
38 #include <asm/machdep.h>
39 #include <asm/pci-bridge.h>
41 #include <mm/mmu_decl.h>
43 #include <sysdev/fsl_soc.h>
44 #include <sysdev/fsl_pci.h>
45 #include <soc/fsl/qe/qe.h>
47 #include <asm/swiotlb.h>
54 #define DBG(fmt...) udbg_printf(fmt)
59 #if IS_BUILTIN(CONFIG_PHYLIB)
61 #define MV88E1111_SCR 0x10
62 #define MV88E1111_SCR_125CLK 0x0010
63 static int mpc8568_fixup_125_clock(struct phy_device *phydev)
68 /* Workaround for the 125 CLK Toggle */
69 scr = phy_read(phydev, MV88E1111_SCR);
74 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
79 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
84 scr = phy_read(phydev, MV88E1111_SCR);
89 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
94 static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
100 err = phy_write(phydev,29, 0x0006);
105 temp = phy_read(phydev, 30);
110 temp = (temp & (~0x8000)) | 0x4000;
111 err = phy_write(phydev,30, temp);
116 err = phy_write(phydev,29, 0x000a);
121 temp = phy_read(phydev, 30);
126 temp = phy_read(phydev, 30);
133 err = phy_write(phydev,30,temp);
138 /* Disable automatic MDI/MDIX selection */
139 temp = phy_read(phydev, 16);
145 err = phy_write(phydev,16,temp);
152 /* ************************************************************************
154 * Setup the architecture
157 #ifdef CONFIG_QUICC_ENGINE
158 static void __init mpc85xx_mds_reset_ucc_phys(void)
160 struct device_node *np;
161 static u8 __iomem *bcsr_regs;
164 np = of_find_node_by_name(NULL, "bcsr");
168 bcsr_regs = of_iomap(np, 0);
173 if (machine_is(mpc8568_mds)) {
174 #define BCSR_UCC1_GETH_EN (0x1 << 7)
175 #define BCSR_UCC2_GETH_EN (0x1 << 7)
176 #define BCSR_UCC1_MODE_MSK (0x3 << 4)
177 #define BCSR_UCC2_MODE_MSK (0x3 << 0)
179 /* Turn off UCC1 & UCC2 */
180 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
181 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
183 /* Mode is RGMII, all bits clear */
184 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
187 /* Turn UCC1 & UCC2 on */
188 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
189 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
190 } else if (machine_is(mpc8569_mds)) {
191 #define BCSR7_UCC12_GETHnRST (0x1 << 2)
192 #define BCSR8_UEM_MARVELL_RST (0x1 << 1)
193 #define BCSR_UCC_RGMII (0x1 << 6)
194 #define BCSR_UCC_RTBI (0x1 << 5)
196 * U-Boot mangles interrupt polarity for Marvell PHYs,
197 * so reset built-in and UEM Marvell PHYs, this puts
198 * the PHYs into their normal state.
200 clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
201 setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
203 setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
204 clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
206 for_each_compatible_node(np, "network", "ucc_geth") {
207 const unsigned int *prop;
210 prop = of_get_property(np, "cell-index", NULL);
216 prop = of_get_property(np, "phy-connection-type", NULL);
220 if (strcmp("rtbi", (const char *)prop) == 0)
221 clrsetbits_8(&bcsr_regs[7 + ucc_num],
222 BCSR_UCC_RGMII, BCSR_UCC_RTBI);
224 } else if (machine_is(p1021_mds)) {
225 #define BCSR11_ENET_MICRST (0x1 << 5)
226 /* Reset Micrel PHY */
227 clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
228 setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
234 static void __init mpc85xx_mds_qe_init(void)
236 struct device_node *np;
238 mpc85xx_qe_par_io_init();
239 mpc85xx_mds_reset_ucc_phys();
241 if (machine_is(p1021_mds)) {
243 struct ccsr_guts __iomem *guts;
245 np = of_find_node_by_name(NULL, "global-utilities");
247 guts = of_iomap(np, 0);
249 pr_err("mpc85xx-rdb: could not map global utilities register\n");
251 /* P1021 has pins muxed for QE and other functions. To
252 * enable QE UEC mode, we need to set bit QE0 for UCC1
253 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
254 * and QE12 for QE MII management signals in PMUXCR
257 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
258 MPC85xx_PMUXCR_QE(3) |
259 MPC85xx_PMUXCR_QE(9) |
260 MPC85xx_PMUXCR_QE(12));
270 static void __init mpc85xx_mds_qe_init(void) { }
271 #endif /* CONFIG_QUICC_ENGINE */
273 static void __init mpc85xx_mds_setup_arch(void)
276 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
280 mpc85xx_mds_qe_init();
282 fsl_pci_assign_primary();
287 #if IS_BUILTIN(CONFIG_PHYLIB)
289 static int __init board_fixups(void)
292 char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
293 struct device_node *mdio;
297 for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
298 mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
300 of_address_to_resource(mdio, 0, &res);
301 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
302 (unsigned long long)res.start, 1);
304 phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
305 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
307 /* Register a workaround for errata */
308 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
309 (unsigned long long)res.start, 7);
310 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
318 machine_arch_initcall(mpc8568_mds, board_fixups);
319 machine_arch_initcall(mpc8569_mds, board_fixups);
323 static int __init mpc85xx_publish_devices(void)
325 return mpc85xx_common_publish_devices();
328 machine_arch_initcall(mpc8568_mds, mpc85xx_publish_devices);
329 machine_arch_initcall(mpc8569_mds, mpc85xx_publish_devices);
330 machine_arch_initcall(p1021_mds, mpc85xx_common_publish_devices);
332 static void __init mpc85xx_mds_pic_init(void)
334 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
335 MPIC_SINGLE_DEST_CPU,
336 0, 256, " OpenPIC ");
337 BUG_ON(mpic == NULL);
342 static int __init mpc85xx_mds_probe(void)
344 return of_machine_is_compatible("MPC85xxMDS");
347 define_machine(mpc8568_mds) {
348 .name = "MPC8568 MDS",
349 .probe = mpc85xx_mds_probe,
350 .setup_arch = mpc85xx_mds_setup_arch,
351 .init_IRQ = mpc85xx_mds_pic_init,
352 .get_irq = mpic_get_irq,
353 .calibrate_decr = generic_calibrate_decr,
354 .progress = udbg_progress,
356 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
357 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
361 static int __init mpc8569_mds_probe(void)
363 return of_machine_is_compatible("fsl,MPC8569EMDS");
366 define_machine(mpc8569_mds) {
367 .name = "MPC8569 MDS",
368 .probe = mpc8569_mds_probe,
369 .setup_arch = mpc85xx_mds_setup_arch,
370 .init_IRQ = mpc85xx_mds_pic_init,
371 .get_irq = mpic_get_irq,
372 .calibrate_decr = generic_calibrate_decr,
373 .progress = udbg_progress,
375 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
376 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
380 static int __init p1021_mds_probe(void)
382 return of_machine_is_compatible("fsl,P1021MDS");
386 define_machine(p1021_mds) {
388 .probe = p1021_mds_probe,
389 .setup_arch = mpc85xx_mds_setup_arch,
390 .init_IRQ = mpc85xx_mds_pic_init,
391 .get_irq = mpic_get_irq,
392 .calibrate_decr = generic_calibrate_decr,
393 .progress = udbg_progress,
395 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
396 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,