1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2008-2011 DENX Software Engineering GmbH
4 * Author: Heiko Schocher <hs@denx.de>
7 * Keymile 83xx platform specific routines.
10 #include <linux/stddef.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/errno.h>
14 #include <linux/reboot.h>
15 #include <linux/pci.h>
16 #include <linux/kdev_t.h>
17 #include <linux/major.h>
18 #include <linux/console.h>
19 #include <linux/delay.h>
20 #include <linux/seq_file.h>
21 #include <linux/root_dev.h>
22 #include <linux/initrd.h>
23 #include <linux/of_platform.h>
24 #include <linux/of_device.h>
26 #include <linux/atomic.h>
27 #include <linux/time.h>
29 #include <asm/machdep.h>
34 #include <sysdev/fsl_soc.h>
35 #include <sysdev/fsl_pci.h>
36 #include <soc/fsl/qe/qe.h>
37 #include <soc/fsl/qe/qe_ic.h>
41 #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
43 static void quirk_mpc8360e_qe_enet10(void)
46 * handle mpc8360E Erratum QE_ENET10:
47 * RGMII AC values do not meet the specification
49 uint svid = mfspr(SPRN_SVR);
50 struct device_node *np_par;
55 np_par = of_find_node_by_name(NULL, "par_io");
57 pr_warn("%s couldn;t find par_io node\n", __func__);
60 /* Map Parallel I/O ports registers */
61 ret = of_address_to_resource(np_par, 0, &res);
63 pr_warn("%s couldn;t map par_io registers\n", __func__);
67 base = ioremap(res.start, resource_size(&res));
70 * set output delay adjustments to default values according
71 * table 5 in Errata Rev. 5, 9/2011:
73 * write 0b01 to UCC1 bits 18:19
74 * write 0b01 to UCC2 option 1 bits 4:5
75 * write 0b01 to UCC2 option 2 bits 16:17
77 clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
80 * set output delay adjustments to default values according
81 * table 3-13 in Reference Manual Rev.3 05/2010:
83 * write 0b01 to UCC2 option 2 bits 16:17
84 * write 0b0101 to UCC1 bits 20:23
85 * write 0b0101 to UCC2 option 1 bits 24:27
87 clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
89 if (SVR_REV(svid) == 0x0021) {
91 * UCC2 option 1: write 0b1010 to bits 24:27
92 * at address IMMRBAR+0x14AC
94 clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
95 } else if (SVR_REV(svid) == 0x0020) {
97 * UCC1: write 0b11 to bits 18:19
98 * at address IMMRBAR+0x14A8
100 setbits32((base + 0xa8), 0x00003000);
103 * UCC2 option 1: write 0b11 to bits 4:5
104 * at address IMMRBAR+0x14A8
106 setbits32((base + 0xa8), 0x0c000000);
109 * UCC2 option 2: write 0b11 to bits 16:17
110 * at address IMMRBAR+0x14AC
112 setbits32((base + 0xac), 0x0000c000);
118 /* ************************************************************************
120 * Setup the architecture
123 static void __init mpc83xx_km_setup_arch(void)
125 #ifdef CONFIG_QUICC_ENGINE
126 struct device_node *np;
129 mpc83xx_setup_arch();
131 #ifdef CONFIG_QUICC_ENGINE
132 np = of_find_node_by_name(NULL, "par_io");
137 for_each_node_by_name(np, "spi")
138 par_io_of_config(np);
140 for_each_node_by_name(np, "ucc")
141 par_io_of_config(np);
143 /* Only apply this quirk when par_io is available */
144 np = of_find_compatible_node(NULL, "network", "ucc_geth");
146 quirk_mpc8360e_qe_enet10();
150 #endif /* CONFIG_QUICC_ENGINE */
153 machine_device_initcall(mpc83xx_km, mpc83xx_declare_of_platform_devices);
155 /* list of the supported boards */
156 static char *board[] __initdata = {
158 "Keymile,kmpbec8321",
163 * Called very early, MMU is off, device-tree isn't unflattened
165 static int __init mpc83xx_km_probe(void)
170 if (of_machine_is_compatible(board[i]))
174 return (board[i] != NULL);
177 define_machine(mpc83xx_km) {
178 .name = "mpc83xx-km-platform",
179 .probe = mpc83xx_km_probe,
180 .setup_arch = mpc83xx_km_setup_arch,
181 .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
182 .get_irq = ipic_get_irq,
183 .restart = mpc83xx_restart,
184 .time_init = mpc83xx_time_init,
185 .calibrate_decr = generic_calibrate_decr,
186 .progress = udbg_progress,