arch/powerpc/perf/power10-pmu.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Performance counter support for POWER10 processors.
   4  *
   5  * Copyright 2020 Madhavan Srinivasan, IBM Corporation.
   6  * Copyright 2020 Athira Rajeev, IBM Corporation.
   7  */
   8
   9 #define pr_fmt(fmt)     "power10-pmu: " fmt
  10
  11 #include "isa207-common.h"
  12
  13 /*
  14  * Raw event encoding for Power10:
  15  *
  16  *        60        56        52        48        44        40        36        32
  17  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
  18  *   | | [ ]   [ src_match ] [  src_mask ]   | [ ] [ l2l3_sel ]  [  thresh_ctl   ]
  19  *   | |  |                                  |  |                         |
  20  *   | |  *- IFM (Linux)                     |  |        thresh start/stop -*
  21  *   | *- BHRB (Linux)                       |  src_sel
  22  *   *- EBB (Linux)                          *invert_bit
  23  *
  24  *        28        24        20        16        12         8         4         0
  25  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
  26  *   [   ] [  sample ]   [ ] [ ]   [ pmc ]   [unit ]   [ ] |  m   [    pmcxsel    ]
  27  *     |        |        |    |                        |   |  |
  28  *     |        |        |    |                        |   |  *- mark
  29  *     |        |        |    *- L1/L2/L3 cache_sel    |   |*-radix_scope_qual
  30  *     |        |        sdar_mode                     |
  31  *     |        *- sampling mode for marked events     *- combine
  32  *     |
  33  *     *- thresh_sel
  34  *
  35  * Below uses IBM bit numbering.
  36  *
  37  * MMCR1[x:y] = unit    (PMCxUNIT)
  38  * MMCR1[24]   = pmc1combine[0]
  39  * MMCR1[25]   = pmc1combine[1]
  40  * MMCR1[26]   = pmc2combine[0]
  41  * MMCR1[27]   = pmc2combine[1]
  42  * MMCR1[28]   = pmc3combine[0]
  43  * MMCR1[29]   = pmc3combine[1]
  44  * MMCR1[30]   = pmc4combine[0]
  45  * MMCR1[31]   = pmc4combine[1]
  46  *
  47  * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
  48  *      MMCR1[20:27] = thresh_ctl
  49  * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
  50  *      MMCR1[20:27] = thresh_ctl
  51  * else
  52  *      MMCRA[48:55] = thresh_ctl   (THRESH START/END)
  53  *
  54  * if thresh_sel:
  55  *      MMCRA[45:47] = thresh_sel
  56  *
  57  * if l2l3_sel:
  58  * MMCR2[56:60] = l2l3_sel[0:4]
  59  *
  60  * MMCR1[16] = cache_sel[0]
  61  * MMCR1[17] = cache_sel[1]
  62  * MMCR1[18] = radix_scope_qual
  63  *
  64  * if mark:
  65  *      MMCRA[63]    = 1                (SAMPLE_ENABLE)
  66  *      MMCRA[57:59] = sample[0:2]      (RAND_SAMP_ELIG)
  67  *      MMCRA[61:62] = sample[3:4]      (RAND_SAMP_MODE)
  68  *
  69  * if EBB and BHRB:
  70  *      MMCRA[32:33] = IFM
  71  *
  72  * MMCRA[SDAR_MODE]  = sdar_mode[0:1]
  73  */
  74
  75 /*
  76  * Some power10 event codes.
  77  */
  78 #define EVENT(_name, _code)     enum{_name = _code}
  79
  80 #include "power10-events-list.h"
  81
  82 #undef EVENT
  83
  84 /* MMCRA IFM bits - POWER10 */
  85 #define POWER10_MMCRA_IFM1              0x0000000040000000UL
  86 #define POWER10_MMCRA_IFM2              0x0000000080000000UL
  87 #define POWER10_MMCRA_IFM3              0x00000000C0000000UL
  88 #define POWER10_MMCRA_BHRB_MASK         0x00000000C0000000UL
  89
  90 extern u64 PERF_REG_EXTENDED_MASK;
  91
  92 /* Table of alternatives, sorted by column 0 */
  93 static const unsigned int power10_event_alternatives[][MAX_ALT] = {
  94         { PM_CYC_ALT,                   PM_CYC },
  95         { PM_INST_CMPL_ALT,             PM_INST_CMPL },
  96 };
  97
  98 static int power10_get_alternatives(u64 event, unsigned int flags, u64 alt[])
  99 {
 100         int num_alt = 0;
 101
 102         num_alt = isa207_get_alternatives(event, alt,
 103                                           ARRAY_SIZE(power10_event_alternatives), flags,
 104                                           power10_event_alternatives);
 105
 106         return num_alt;
 107 }
 108
 109 static int power10_check_attr_config(struct perf_event *ev)
 110 {
 111         u64 val;
 112         u64 event = ev->attr.config;
 113
 114         val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
 115         if (val == 0x10 || isa3XX_check_attr_config(ev))
 116                 return -EINVAL;
 117
 118         return 0;
 119 }
 120
 121 GENERIC_EVENT_ATTR(cpu-cycles,                  PM_CYC);
 122 GENERIC_EVENT_ATTR(instructions,                PM_INST_CMPL);
 123 GENERIC_EVENT_ATTR(branch-instructions,         PM_BR_CMPL);
 124 GENERIC_EVENT_ATTR(branch-misses,               PM_BR_MPRED_CMPL);
 125 GENERIC_EVENT_ATTR(cache-references,            PM_LD_REF_L1);
 126 GENERIC_EVENT_ATTR(cache-misses,                PM_LD_MISS_L1);
 127 GENERIC_EVENT_ATTR(mem-loads,                   MEM_LOADS);
 128 GENERIC_EVENT_ATTR(mem-stores,                  MEM_STORES);
 129 GENERIC_EVENT_ATTR(branch-instructions,         PM_BR_FIN);
 130 GENERIC_EVENT_ATTR(branch-misses,               PM_MPRED_BR_FIN);
 131 GENERIC_EVENT_ATTR(cache-misses,                PM_LD_DEMAND_MISS_L1_FIN);
 132
 133 CACHE_EVENT_ATTR(L1-dcache-load-misses,         PM_LD_MISS_L1);
 134 CACHE_EVENT_ATTR(L1-dcache-loads,               PM_LD_REF_L1);
 135 CACHE_EVENT_ATTR(L1-dcache-prefetches,          PM_LD_PREFETCH_CACHE_LINE_MISS);
 136 CACHE_EVENT_ATTR(L1-dcache-store-misses,        PM_ST_MISS_L1);
 137 CACHE_EVENT_ATTR(L1-icache-load-misses,         PM_L1_ICACHE_MISS);
 138 CACHE_EVENT_ATTR(L1-icache-loads,               PM_INST_FROM_L1);
 139 CACHE_EVENT_ATTR(L1-icache-prefetches,          PM_IC_PREF_REQ);
 140 CACHE_EVENT_ATTR(LLC-load-misses,               PM_DATA_FROM_L3MISS);
 141 CACHE_EVENT_ATTR(LLC-loads,                     PM_DATA_FROM_L3);
 142 CACHE_EVENT_ATTR(LLC-prefetches,                PM_L3_PF_MISS_L3);
 143 CACHE_EVENT_ATTR(LLC-store-misses,              PM_L2_ST_MISS);
 144 CACHE_EVENT_ATTR(LLC-stores,                    PM_L2_ST);
 145 CACHE_EVENT_ATTR(branch-load-misses,            PM_BR_MPRED_CMPL);
 146 CACHE_EVENT_ATTR(branch-loads,                  PM_BR_CMPL);
 147 CACHE_EVENT_ATTR(dTLB-load-misses,              PM_DTLB_MISS);
 148 CACHE_EVENT_ATTR(iTLB-load-misses,              PM_ITLB_MISS);
 149
 150 static struct attribute *power10_events_attr_dd1[] = {
 151         GENERIC_EVENT_PTR(PM_CYC),
 152         GENERIC_EVENT_PTR(PM_INST_CMPL),
 153         GENERIC_EVENT_PTR(PM_BR_CMPL),
 154         GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
 155         GENERIC_EVENT_PTR(PM_LD_REF_L1),
 156         GENERIC_EVENT_PTR(PM_LD_MISS_L1),
 157         GENERIC_EVENT_PTR(MEM_LOADS),
 158         GENERIC_EVENT_PTR(MEM_STORES),
 159         CACHE_EVENT_PTR(PM_LD_MISS_L1),
 160         CACHE_EVENT_PTR(PM_LD_REF_L1),
 161         CACHE_EVENT_PTR(PM_LD_PREFETCH_CACHE_LINE_MISS),
 162         CACHE_EVENT_PTR(PM_ST_MISS_L1),
 163         CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
 164         CACHE_EVENT_PTR(PM_INST_FROM_L1),
 165         CACHE_EVENT_PTR(PM_IC_PREF_REQ),
 166         CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
 167         CACHE_EVENT_PTR(PM_DATA_FROM_L3),
 168         CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
 169         CACHE_EVENT_PTR(PM_BR_CMPL),
 170         CACHE_EVENT_PTR(PM_DTLB_MISS),
 171         CACHE_EVENT_PTR(PM_ITLB_MISS),
 172         NULL
 173 };
 174
 175 static struct attribute *power10_events_attr[] = {
 176         GENERIC_EVENT_PTR(PM_CYC),
 177         GENERIC_EVENT_PTR(PM_INST_CMPL),
 178         GENERIC_EVENT_PTR(PM_BR_FIN),
 179         GENERIC_EVENT_PTR(PM_MPRED_BR_FIN),
 180         GENERIC_EVENT_PTR(PM_LD_REF_L1),
 181         GENERIC_EVENT_PTR(PM_LD_DEMAND_MISS_L1_FIN),
 182         GENERIC_EVENT_PTR(MEM_LOADS),
 183         GENERIC_EVENT_PTR(MEM_STORES),
 184         CACHE_EVENT_PTR(PM_LD_MISS_L1),
 185         CACHE_EVENT_PTR(PM_LD_REF_L1),
 186         CACHE_EVENT_PTR(PM_LD_PREFETCH_CACHE_LINE_MISS),
 187         CACHE_EVENT_PTR(PM_ST_MISS_L1),
 188         CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
 189         CACHE_EVENT_PTR(PM_INST_FROM_L1),
 190         CACHE_EVENT_PTR(PM_IC_PREF_REQ),
 191         CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
 192         CACHE_EVENT_PTR(PM_DATA_FROM_L3),
 193         CACHE_EVENT_PTR(PM_L3_PF_MISS_L3),
 194         CACHE_EVENT_PTR(PM_L2_ST_MISS),
 195         CACHE_EVENT_PTR(PM_L2_ST),
 196         CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
 197         CACHE_EVENT_PTR(PM_BR_CMPL),
 198         CACHE_EVENT_PTR(PM_DTLB_MISS),
 199         CACHE_EVENT_PTR(PM_ITLB_MISS),
 200         NULL
 201 };
 202
 203 static const struct attribute_group power10_pmu_events_group_dd1 = {
 204         .name = "events",
 205         .attrs = power10_events_attr_dd1,
 206 };
 207
 208 static const struct attribute_group power10_pmu_events_group = {
 209         .name = "events",
 210         .attrs = power10_events_attr,
 211 };
 212
 213 PMU_FORMAT_ATTR(event,          "config:0-59");
 214 PMU_FORMAT_ATTR(pmcxsel,        "config:0-7");
 215 PMU_FORMAT_ATTR(mark,           "config:8");
 216 PMU_FORMAT_ATTR(combine,        "config:10-11");
 217 PMU_FORMAT_ATTR(unit,           "config:12-15");
 218 PMU_FORMAT_ATTR(pmc,            "config:16-19");
 219 PMU_FORMAT_ATTR(cache_sel,      "config:20-21");
 220 PMU_FORMAT_ATTR(sdar_mode,      "config:22-23");
 221 PMU_FORMAT_ATTR(sample_mode,    "config:24-28");
 222 PMU_FORMAT_ATTR(thresh_sel,     "config:29-31");
 223 PMU_FORMAT_ATTR(thresh_stop,    "config:32-35");
 224 PMU_FORMAT_ATTR(thresh_start,   "config:36-39");
 225 PMU_FORMAT_ATTR(l2l3_sel,       "config:40-44");
 226 PMU_FORMAT_ATTR(src_sel,        "config:45-46");
 227 PMU_FORMAT_ATTR(invert_bit,     "config:47");
 228 PMU_FORMAT_ATTR(src_mask,       "config:48-53");
 229 PMU_FORMAT_ATTR(src_match,      "config:54-59");
 230 PMU_FORMAT_ATTR(radix_scope,    "config:9");
 231 PMU_FORMAT_ATTR(thresh_cmp,     "config1:0-17");
 232
 233 static struct attribute *power10_pmu_format_attr[] = {
 234         &format_attr_event.attr,
 235         &format_attr_pmcxsel.attr,
 236         &format_attr_mark.attr,
 237         &format_attr_combine.attr,
 238         &format_attr_unit.attr,
 239         &format_attr_pmc.attr,
 240         &format_attr_cache_sel.attr,
 241         &format_attr_sdar_mode.attr,
 242         &format_attr_sample_mode.attr,
 243         &format_attr_thresh_sel.attr,
 244         &format_attr_thresh_stop.attr,
 245         &format_attr_thresh_start.attr,
 246         &format_attr_l2l3_sel.attr,
 247         &format_attr_src_sel.attr,
 248         &format_attr_invert_bit.attr,
 249         &format_attr_src_mask.attr,
 250         &format_attr_src_match.attr,
 251         &format_attr_radix_scope.attr,
 252         &format_attr_thresh_cmp.attr,
 253         NULL,
 254 };
 255
 256 static const struct attribute_group power10_pmu_format_group = {
 257         .name = "format",
 258         .attrs = power10_pmu_format_attr,
 259 };
 260
 261 static const struct attribute_group *power10_pmu_attr_groups_dd1[] = {
 262         &power10_pmu_format_group,
 263         &power10_pmu_events_group_dd1,
 264         NULL,
 265 };
 266
 267 static const struct attribute_group *power10_pmu_attr_groups[] = {
 268         &power10_pmu_format_group,
 269         &power10_pmu_events_group,
 270         NULL,
 271 };
 272
 273 static int power10_generic_events_dd1[] = {
 274         [PERF_COUNT_HW_CPU_CYCLES] =                    PM_CYC,
 275         [PERF_COUNT_HW_INSTRUCTIONS] =                  PM_INST_CMPL,
 276         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PM_BR_CMPL,
 277         [PERF_COUNT_HW_BRANCH_MISSES] =                 PM_BR_MPRED_CMPL,
 278         [PERF_COUNT_HW_CACHE_REFERENCES] =              PM_LD_REF_L1,
 279         [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1,
 280 };
 281
 282 static int power10_generic_events[] = {
 283         [PERF_COUNT_HW_CPU_CYCLES] =                    PM_CYC,
 284         [PERF_COUNT_HW_INSTRUCTIONS] =                  PM_INST_CMPL,
 285         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PM_BR_FIN,
 286         [PERF_COUNT_HW_BRANCH_MISSES] =                 PM_MPRED_BR_FIN,
 287         [PERF_COUNT_HW_CACHE_REFERENCES] =              PM_LD_REF_L1,
 288         [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_DEMAND_MISS_L1_FIN,
 289 };
 290
 291 static u64 power10_bhrb_filter_map(u64 branch_sample_type)
 292 {
 293         u64 pmu_bhrb_filter = 0;
 294
 295         /* BHRB and regular PMU events share the same privilege state
 296          * filter configuration. BHRB is always recorded along with a
 297          * regular PMU event. As the privilege state filter is handled
 298          * in the basic PMC configuration of the accompanying regular
 299          * PMU event, we ignore any separate BHRB specific request.
 300          */
 301
 302         /* No branch filter requested */
 303         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
 304                 return pmu_bhrb_filter;
 305
 306         /* Invalid branch filter options - HW does not support */
 307         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
 308                 return -1;
 309
 310         if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) {
 311                 pmu_bhrb_filter |= POWER10_MMCRA_IFM2;
 312                 return pmu_bhrb_filter;
 313         }
 314
 315         if (branch_sample_type & PERF_SAMPLE_BRANCH_COND) {
 316                 pmu_bhrb_filter |= POWER10_MMCRA_IFM3;
 317                 return pmu_bhrb_filter;
 318         }
 319
 320         if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
 321                 return -1;
 322
 323         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
 324                 pmu_bhrb_filter |= POWER10_MMCRA_IFM1;
 325                 return pmu_bhrb_filter;
 326         }
 327
 328         /* Every thing else is unsupported */
 329         return -1;
 330 }
 331
 332 static void power10_config_bhrb(u64 pmu_bhrb_filter)
 333 {
 334         pmu_bhrb_filter &= POWER10_MMCRA_BHRB_MASK;
 335
 336         /* Enable BHRB filter in PMU */
 337         mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
 338 }
 339
 340 #define C(x)    PERF_COUNT_HW_CACHE_##x
 341
 342 /*
 343  * Table of generalized cache-related events.
 344  * 0 means not supported, -1 means nonsensical, other values
 345  * are event codes.
 346  */
 347 static u64 power10_cache_events_dd1[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 348         [C(L1D)] = {
 349                 [C(OP_READ)] = {
 350                         [C(RESULT_ACCESS)] = PM_LD_REF_L1,
 351                         [C(RESULT_MISS)] = PM_LD_MISS_L1,
 352                 },
 353                 [C(OP_WRITE)] = {
 354                         [C(RESULT_ACCESS)] = 0,
 355                         [C(RESULT_MISS)] = PM_ST_MISS_L1,
 356                 },
 357                 [C(OP_PREFETCH)] = {
 358                         [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS,
 359                         [C(RESULT_MISS)] = 0,
 360                 },
 361         },
 362         [C(L1I)] = {
 363                 [C(OP_READ)] = {
 364                         [C(RESULT_ACCESS)] = PM_INST_FROM_L1,
 365                         [C(RESULT_MISS)] = PM_L1_ICACHE_MISS,
 366                 },
 367                 [C(OP_WRITE)] = {
 368                         [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS,
 369                         [C(RESULT_MISS)] = -1,
 370                 },
 371                 [C(OP_PREFETCH)] = {
 372                         [C(RESULT_ACCESS)] = PM_IC_PREF_REQ,
 373                         [C(RESULT_MISS)] = 0,
 374                 },
 375         },
 376         [C(LL)] = {
 377                 [C(OP_READ)] = {
 378                         [C(RESULT_ACCESS)] = PM_DATA_FROM_L3,
 379                         [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS,
 380                 },
 381                 [C(OP_WRITE)] = {
 382                         [C(RESULT_ACCESS)] = -1,
 383                         [C(RESULT_MISS)] = -1,
 384                 },
 385                 [C(OP_PREFETCH)] = {
 386                         [C(RESULT_ACCESS)] = -1,
 387                         [C(RESULT_MISS)] = 0,
 388                 },
 389         },
 390          [C(DTLB)] = {
 391                 [C(OP_READ)] = {
 392                         [C(RESULT_ACCESS)] = 0,
 393                         [C(RESULT_MISS)] = PM_DTLB_MISS,
 394                 },
 395                 [C(OP_WRITE)] = {
 396                         [C(RESULT_ACCESS)] = -1,
 397                         [C(RESULT_MISS)] = -1,
 398                 },
 399                 [C(OP_PREFETCH)] = {
 400                         [C(RESULT_ACCESS)] = -1,
 401                         [C(RESULT_MISS)] = -1,
 402                 },
 403         },
 404         [C(ITLB)] = {
 405                 [C(OP_READ)] = {
 406                         [C(RESULT_ACCESS)] = 0,
 407                         [C(RESULT_MISS)] = PM_ITLB_MISS,
 408                 },
 409                 [C(OP_WRITE)] = {
 410                         [C(RESULT_ACCESS)] = -1,
 411                         [C(RESULT_MISS)] = -1,
 412                 },
 413                 [C(OP_PREFETCH)] = {
 414                         [C(RESULT_ACCESS)] = -1,
 415                         [C(RESULT_MISS)] = -1,
 416                 },
 417         },
 418         [C(BPU)] = {
 419                 [C(OP_READ)] = {
 420                         [C(RESULT_ACCESS)] = PM_BR_CMPL,
 421                         [C(RESULT_MISS)] = PM_BR_MPRED_CMPL,
 422                 },
 423                 [C(OP_WRITE)] = {
 424                         [C(RESULT_ACCESS)] = -1,
 425                         [C(RESULT_MISS)] = -1,
 426                 },
 427                 [C(OP_PREFETCH)] = {
 428                         [C(RESULT_ACCESS)] = -1,
 429                         [C(RESULT_MISS)] = -1,
 430                 },
 431         },
 432         [C(NODE)] = {
 433                 [C(OP_READ)] = {
 434                         [C(RESULT_ACCESS)] = -1,
 435                         [C(RESULT_MISS)] = -1,
 436                 },
 437                 [C(OP_WRITE)] = {
 438                         [C(RESULT_ACCESS)] = -1,
 439                         [C(RESULT_MISS)] = -1,
 440                 },
 441                 [C(OP_PREFETCH)] = {
 442                         [C(RESULT_ACCESS)] = -1,
 443                         [C(RESULT_MISS)] = -1,
 444                 },
 445         },
 446 };
 447
 448 static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 449         [C(L1D)] = {
 450                 [C(OP_READ)] = {
 451                         [C(RESULT_ACCESS)] = PM_LD_REF_L1,
 452                         [C(RESULT_MISS)] = PM_LD_MISS_L1,
 453                 },
 454                 [C(OP_WRITE)] = {
 455                         [C(RESULT_ACCESS)] = 0,
 456                         [C(RESULT_MISS)] = PM_ST_MISS_L1,
 457                 },
 458                 [C(OP_PREFETCH)] = {
 459                         [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS,
 460                         [C(RESULT_MISS)] = 0,
 461                 },
 462         },
 463         [C(L1I)] = {
 464                 [C(OP_READ)] = {
 465                         [C(RESULT_ACCESS)] = PM_INST_FROM_L1,
 466                         [C(RESULT_MISS)] = PM_L1_ICACHE_MISS,
 467                 },
 468                 [C(OP_WRITE)] = {
 469                         [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS,
 470                         [C(RESULT_MISS)] = -1,
 471                 },
 472                 [C(OP_PREFETCH)] = {
 473                         [C(RESULT_ACCESS)] = PM_IC_PREF_REQ,
 474                         [C(RESULT_MISS)] = 0,
 475                 },
 476         },
 477         [C(LL)] = {
 478                 [C(OP_READ)] = {
 479                         [C(RESULT_ACCESS)] = PM_DATA_FROM_L3,
 480                         [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS,
 481                 },
 482                 [C(OP_WRITE)] = {
 483                         [C(RESULT_ACCESS)] = PM_L2_ST,
 484                         [C(RESULT_MISS)] = PM_L2_ST_MISS,
 485                 },
 486                 [C(OP_PREFETCH)] = {
 487                         [C(RESULT_ACCESS)] = PM_L3_PF_MISS_L3,
 488                         [C(RESULT_MISS)] = 0,
 489                 },
 490         },
 491          [C(DTLB)] = {
 492                 [C(OP_READ)] = {
 493                         [C(RESULT_ACCESS)] = 0,
 494                         [C(RESULT_MISS)] = PM_DTLB_MISS,
 495                 },
 496                 [C(OP_WRITE)] = {
 497                         [C(RESULT_ACCESS)] = -1,
 498                         [C(RESULT_MISS)] = -1,
 499                 },
 500                 [C(OP_PREFETCH)] = {
 501                         [C(RESULT_ACCESS)] = -1,
 502                         [C(RESULT_MISS)] = -1,
 503                 },
 504         },
 505         [C(ITLB)] = {
 506                 [C(OP_READ)] = {
 507                         [C(RESULT_ACCESS)] = 0,
 508                         [C(RESULT_MISS)] = PM_ITLB_MISS,
 509                 },
 510                 [C(OP_WRITE)] = {
 511                         [C(RESULT_ACCESS)] = -1,
 512                         [C(RESULT_MISS)] = -1,
 513                 },
 514                 [C(OP_PREFETCH)] = {
 515                         [C(RESULT_ACCESS)] = -1,
 516                         [C(RESULT_MISS)] = -1,
 517                 },
 518         },
 519         [C(BPU)] = {
 520                 [C(OP_READ)] = {
 521                         [C(RESULT_ACCESS)] = PM_BR_CMPL,
 522                         [C(RESULT_MISS)] = PM_BR_MPRED_CMPL,
 523                 },
 524                 [C(OP_WRITE)] = {
 525                         [C(RESULT_ACCESS)] = -1,
 526                         [C(RESULT_MISS)] = -1,
 527                 },
 528                 [C(OP_PREFETCH)] = {
 529                         [C(RESULT_ACCESS)] = -1,
 530                         [C(RESULT_MISS)] = -1,
 531                 },
 532         },
 533         [C(NODE)] = {
 534                 [C(OP_READ)] = {
 535                         [C(RESULT_ACCESS)] = -1,
 536                         [C(RESULT_MISS)] = -1,
 537                 },
 538                 [C(OP_WRITE)] = {
 539                         [C(RESULT_ACCESS)] = -1,
 540                         [C(RESULT_MISS)] = -1,
 541                 },
 542                 [C(OP_PREFETCH)] = {
 543                         [C(RESULT_ACCESS)] = -1,
 544                         [C(RESULT_MISS)] = -1,
 545                 },
 546         },
 547 };
 548
 549 #undef C
 550
 551 /*
 552  * Set the MMCR0[CC56RUN] bit to enable counting for
 553  * PMC5 and PMC6 regardless of the state of CTRL[RUN],
 554  * so that we can use counters 5 and 6 as PM_INST_CMPL and
 555  * PM_CYC.
 556  */
 557 static int power10_compute_mmcr(u64 event[], int n_ev,
 558                                 unsigned int hwc[], struct mmcr_regs *mmcr,
 559                                 struct perf_event *pevents[], u32 flags)
 560 {
 561         int ret;
 562
 563         ret = isa207_compute_mmcr(event, n_ev, hwc, mmcr, pevents, flags);
 564         if (!ret)
 565                 mmcr->mmcr0 |= MMCR0_C56RUN;
 566         return ret;
 567 }
 568
 569 static struct power_pmu power10_pmu = {
 570         .name                   = "POWER10",
 571         .n_counter              = MAX_PMU_COUNTERS,
 572         .add_fields             = ISA207_ADD_FIELDS,
 573         .test_adder             = ISA207_TEST_ADDER,
 574         .group_constraint_mask  = CNST_CACHE_PMC4_MASK,
 575         .group_constraint_val   = CNST_CACHE_PMC4_VAL,
 576         .compute_mmcr           = power10_compute_mmcr,
 577         .config_bhrb            = power10_config_bhrb,
 578         .bhrb_filter_map        = power10_bhrb_filter_map,
 579         .get_constraint         = isa207_get_constraint,
 580         .get_alternatives       = power10_get_alternatives,
 581         .get_mem_data_src       = isa207_get_mem_data_src,
 582         .get_mem_weight         = isa207_get_mem_weight,
 583         .disable_pmc            = isa207_disable_pmc,
 584         .flags                  = PPMU_HAS_SIER | PPMU_ARCH_207S |
 585                                   PPMU_ARCH_31 | PPMU_HAS_ATTR_CONFIG1,
 586         .n_generic              = ARRAY_SIZE(power10_generic_events),
 587         .generic_events         = power10_generic_events,
 588         .cache_events           = &power10_cache_events,
 589         .attr_groups            = power10_pmu_attr_groups,
 590         .bhrb_nr                = 32,
 591         .capabilities           = PERF_PMU_CAP_EXTENDED_REGS,
 592         .check_attr_config      = power10_check_attr_config,
 593 };
 594
 595 int __init init_power10_pmu(void)
 596 {
 597         unsigned int pvr;
 598         int rc;
 599
 600         /* Comes from cpu_specs[] */
 601         if (!cur_cpu_spec->oprofile_cpu_type ||
 602             strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power10"))
 603                 return -ENODEV;
 604
 605         pvr = mfspr(SPRN_PVR);
 606         /* Add the ppmu flag for power10 DD1 */
 607         if ((PVR_CFG(pvr) == 1))
 608                 power10_pmu.flags |= PPMU_P10_DD1;
 609
 610         /* Set the PERF_REG_EXTENDED_MASK here */
 611         PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_31;
 612
 613         if ((PVR_CFG(pvr) == 1)) {
 614                 power10_pmu.generic_events = power10_generic_events_dd1;
 615                 power10_pmu.attr_groups = power10_pmu_attr_groups_dd1;
 616                 power10_pmu.cache_events = &power10_cache_events_dd1;
 617         }
 618
 619         rc = register_power_pmu(&power10_pmu);
 620         if (rc)
 621                 return rc;
 622
 623         /* Tell userspace that EBB is supported */
 624         cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
 625
 626         return 0;
 627 }