2 * In-Memory Collection (IMC) Performance Monitor counter support.
4 * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
5 * (C) 2017 Anju T Sudhakar, IBM Corporation.
6 * (C) 2017 Hemant K Shaw, IBM Corporation.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or later version.
13 #include <linux/perf_event.h>
14 #include <linux/slab.h>
16 #include <asm/imc-pmu.h>
17 #include <asm/cputhreads.h>
19 #include <linux/string.h>
21 /* Nest IMC data structures and variables */
24 * Used to avoid races in counting the nest-pmu units during hotplug
25 * register and unregister
27 static DEFINE_MUTEX(nest_init_lock);
28 static DEFINE_PER_CPU(struct imc_pmu_ref *, local_nest_imc_refc);
29 static struct imc_pmu **per_nest_pmu_arr;
30 static cpumask_t nest_imc_cpumask;
31 static struct imc_pmu_ref *nest_imc_refc;
34 /* Core IMC data structures and variables */
36 static cpumask_t core_imc_cpumask;
37 static struct imc_pmu_ref *core_imc_refc;
38 static struct imc_pmu *core_imc_pmu;
40 /* Thread IMC data structures and variables */
42 static DEFINE_PER_CPU(u64 *, thread_imc_mem);
43 static struct imc_pmu *thread_imc_pmu;
44 static int thread_imc_mem_size;
46 static struct imc_pmu *imc_event_to_pmu(struct perf_event *event)
48 return container_of(event->pmu, struct imc_pmu, pmu);
51 PMU_FORMAT_ATTR(event, "config:0-40");
52 PMU_FORMAT_ATTR(offset, "config:0-31");
53 PMU_FORMAT_ATTR(rvalue, "config:32");
54 PMU_FORMAT_ATTR(mode, "config:33-40");
55 static struct attribute *imc_format_attrs[] = {
56 &format_attr_event.attr,
57 &format_attr_offset.attr,
58 &format_attr_rvalue.attr,
59 &format_attr_mode.attr,
63 static struct attribute_group imc_format_group = {
65 .attrs = imc_format_attrs,
68 /* Get the cpumask printed to a buffer "buf" */
69 static ssize_t imc_pmu_cpumask_get_attr(struct device *dev,
70 struct device_attribute *attr,
73 struct pmu *pmu = dev_get_drvdata(dev);
74 struct imc_pmu *imc_pmu = container_of(pmu, struct imc_pmu, pmu);
75 cpumask_t *active_mask;
77 switch(imc_pmu->domain){
79 active_mask = &nest_imc_cpumask;
82 active_mask = &core_imc_cpumask;
88 return cpumap_print_to_pagebuf(true, buf, active_mask);
91 static DEVICE_ATTR(cpumask, S_IRUGO, imc_pmu_cpumask_get_attr, NULL);
93 static struct attribute *imc_pmu_cpumask_attrs[] = {
94 &dev_attr_cpumask.attr,
98 static struct attribute_group imc_pmu_cpumask_attr_group = {
99 .attrs = imc_pmu_cpumask_attrs,
102 /* device_str_attr_create : Populate event "name" and string "str" in attribute */
103 static struct attribute *device_str_attr_create(const char *name, const char *str)
105 struct perf_pmu_events_attr *attr;
107 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
110 sysfs_attr_init(&attr->attr.attr);
112 attr->event_str = str;
113 attr->attr.attr.name = name;
114 attr->attr.attr.mode = 0444;
115 attr->attr.show = perf_event_sysfs_show;
117 return &attr->attr.attr;
120 static int imc_parse_event(struct device_node *np, const char *scale,
121 const char *unit, const char *prefix,
122 u32 base, struct imc_events *event)
127 if (of_property_read_u32(np, "reg", ®))
129 /* Add the base_reg value to the "reg" */
130 event->value = base + reg;
132 if (of_property_read_string(np, "event-name", &s))
135 event->name = kasprintf(GFP_KERNEL, "%s%s", prefix, s);
139 if (of_property_read_string(np, "scale", &s))
143 event->scale = kstrdup(s, GFP_KERNEL);
148 if (of_property_read_string(np, "unit", &s))
152 event->unit = kstrdup(s, GFP_KERNEL);
166 * imc_free_events: Function to cleanup the events list, having
169 static void imc_free_events(struct imc_events *events, int nr_entries)
173 /* Nothing to clean, return */
176 for (i = 0; i < nr_entries; i++) {
177 kfree(events[i].unit);
178 kfree(events[i].scale);
179 kfree(events[i].name);
186 * update_events_in_group: Update the "events" information in an attr_group
187 * and assign the attr_group to the pmu "pmu".
189 static int update_events_in_group(struct device_node *node, struct imc_pmu *pmu)
191 struct attribute_group *attr_group;
192 struct attribute **attrs, *dev_str;
193 struct device_node *np, *pmu_events;
194 u32 handle, base_reg;
195 int i = 0, j = 0, ct, ret;
196 const char *prefix, *g_scale, *g_unit;
197 const char *ev_val_str, *ev_scale_str, *ev_unit_str;
199 if (!of_property_read_u32(node, "events", &handle))
200 pmu_events = of_find_node_by_phandle(handle);
204 /* Did not find any node with a given phandle */
208 /* Get a count of number of child nodes */
209 ct = of_get_child_count(pmu_events);
211 /* Get the event prefix */
212 if (of_property_read_string(node, "events-prefix", &prefix))
215 /* Get a global unit and scale data if available */
216 if (of_property_read_string(node, "scale", &g_scale))
219 if (of_property_read_string(node, "unit", &g_unit))
222 /* "reg" property gives out the base offset of the counters data */
223 of_property_read_u32(node, "reg", &base_reg);
225 /* Allocate memory for the events */
226 pmu->events = kcalloc(ct, sizeof(struct imc_events), GFP_KERNEL);
231 /* Parse the events and update the struct */
232 for_each_child_of_node(pmu_events, np) {
233 ret = imc_parse_event(np, g_scale, g_unit, prefix, base_reg, &pmu->events[ct]);
238 /* Allocate memory for attribute group */
239 attr_group = kzalloc(sizeof(*attr_group), GFP_KERNEL);
241 imc_free_events(pmu->events, ct);
246 * Allocate memory for attributes.
247 * Since we have count of events for this pmu, we also allocate
248 * memory for the scale and unit attribute for now.
249 * "ct" has the total event structs added from the events-parent node.
250 * So allocate three times the "ct" (this includes event, event_scale and
253 attrs = kcalloc(((ct * 3) + 1), sizeof(struct attribute *), GFP_KERNEL);
256 imc_free_events(pmu->events, ct);
260 attr_group->name = "events";
261 attr_group->attrs = attrs;
263 ev_val_str = kasprintf(GFP_KERNEL, "event=0x%x", pmu->events[i].value);
264 dev_str = device_str_attr_create(pmu->events[i].name, ev_val_str);
268 attrs[j++] = dev_str;
269 if (pmu->events[i].scale) {
270 ev_scale_str = kasprintf(GFP_KERNEL, "%s.scale", pmu->events[i].name);
271 dev_str = device_str_attr_create(ev_scale_str, pmu->events[i].scale);
275 attrs[j++] = dev_str;
278 if (pmu->events[i].unit) {
279 ev_unit_str = kasprintf(GFP_KERNEL, "%s.unit", pmu->events[i].name);
280 dev_str = device_str_attr_create(ev_unit_str, pmu->events[i].unit);
284 attrs[j++] = dev_str;
288 /* Save the event attribute */
289 pmu->attr_groups[IMC_EVENT_ATTR] = attr_group;
294 /* get_nest_pmu_ref: Return the imc_pmu_ref struct for the given node */
295 static struct imc_pmu_ref *get_nest_pmu_ref(int cpu)
297 return per_cpu(local_nest_imc_refc, cpu);
300 static void nest_change_cpu_context(int old_cpu, int new_cpu)
302 struct imc_pmu **pn = per_nest_pmu_arr;
304 if (old_cpu < 0 || new_cpu < 0)
308 perf_pmu_migrate_context(&(*pn)->pmu, old_cpu, new_cpu);
313 static int ppc_nest_imc_cpu_offline(unsigned int cpu)
315 int nid, target = -1;
316 const struct cpumask *l_cpumask;
317 struct imc_pmu_ref *ref;
320 * Check in the designated list for this cpu. Dont bother
321 * if not one of them.
323 if (!cpumask_test_and_clear_cpu(cpu, &nest_imc_cpumask))
327 * Check whether nest_imc is registered. We could end up here if the
328 * cpuhotplug callback registration fails. i.e, callback invokes the
329 * offline path for all successfully registered nodes. At this stage,
330 * nest_imc pmu will not be registered and we should return here.
332 * We return with a zero since this is not an offline failure. And
333 * cpuhp_setup_state() returns the actual failure reason to the caller,
334 * which in turn will call the cleanup routine.
340 * Now that this cpu is one of the designated,
341 * find a next cpu a) which is online and b) in same chip.
343 nid = cpu_to_node(cpu);
344 l_cpumask = cpumask_of_node(nid);
345 target = cpumask_any_but(l_cpumask, cpu);
348 * Update the cpumask with the target cpu and
349 * migrate the context if needed
351 if (target >= 0 && target < nr_cpu_ids) {
352 cpumask_set_cpu(target, &nest_imc_cpumask);
353 nest_change_cpu_context(cpu, target);
355 opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
356 get_hard_smp_processor_id(cpu));
358 * If this is the last cpu in this chip then, skip the reference
359 * count mutex lock and make the reference count on this chip zero.
361 ref = get_nest_pmu_ref(cpu);
370 static int ppc_nest_imc_cpu_online(unsigned int cpu)
372 const struct cpumask *l_cpumask;
373 static struct cpumask tmp_mask;
376 /* Get the cpumask of this node */
377 l_cpumask = cpumask_of_node(cpu_to_node(cpu));
380 * If this is not the first online CPU on this node, then
383 if (cpumask_and(&tmp_mask, l_cpumask, &nest_imc_cpumask))
387 * If this is the first online cpu on this node
388 * disable the nest counters by making an OPAL call.
390 res = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
391 get_hard_smp_processor_id(cpu));
395 /* Make this CPU the designated target for counter collection */
396 cpumask_set_cpu(cpu, &nest_imc_cpumask);
400 static int nest_pmu_cpumask_init(void)
402 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE,
403 "perf/powerpc/imc:online",
404 ppc_nest_imc_cpu_online,
405 ppc_nest_imc_cpu_offline);
408 static void nest_imc_counters_release(struct perf_event *event)
411 struct imc_pmu_ref *ref;
416 node_id = cpu_to_node(event->cpu);
419 * See if we need to disable the nest PMU.
420 * If no events are currently in use, then we have to take a
421 * mutex to ensure that we don't race with another task doing
422 * enable or disable the nest counters.
424 ref = get_nest_pmu_ref(event->cpu);
428 /* Take the mutex lock for this node and then decrement the reference count */
429 mutex_lock(&ref->lock);
430 if (ref->refc == 0) {
432 * The scenario where this is true is, when perf session is
433 * started, followed by offlining of all cpus in a given node.
435 * In the cpuhotplug offline path, ppc_nest_imc_cpu_offline()
436 * function set the ref->count to zero, if the cpu which is
437 * about to offline is the last cpu in a given node and make
438 * an OPAL call to disable the engine in that node.
441 mutex_unlock(&ref->lock);
445 if (ref->refc == 0) {
446 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
447 get_hard_smp_processor_id(event->cpu));
449 mutex_unlock(&ref->lock);
450 pr_err("nest-imc: Unable to stop the counters for core %d\n", node_id);
453 } else if (ref->refc < 0) {
454 WARN(1, "nest-imc: Invalid event reference count\n");
457 mutex_unlock(&ref->lock);
460 static int nest_imc_event_init(struct perf_event *event)
462 int chip_id, rc, node_id;
463 u32 l_config, config = event->attr.config;
464 struct imc_mem_info *pcni;
466 struct imc_pmu_ref *ref;
469 if (event->attr.type != event->pmu->type)
472 /* Sampling not supported */
473 if (event->hw.sample_period)
476 /* unsupported modes and filters */
477 if (event->attr.exclude_user ||
478 event->attr.exclude_kernel ||
479 event->attr.exclude_hv ||
480 event->attr.exclude_idle ||
481 event->attr.exclude_host ||
482 event->attr.exclude_guest)
488 pmu = imc_event_to_pmu(event);
490 /* Sanity check for config (event offset) */
491 if ((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size)
495 * Nest HW counter memory resides in a per-chip reserve-memory (HOMER).
496 * Get the base memory addresss for this cpu.
498 chip_id = cpu_to_chip_id(event->cpu);
499 pcni = pmu->mem_info;
501 if (pcni->id == chip_id) {
512 * Add the event offset to the base address.
514 l_config = config & IMC_EVENT_OFFSET_MASK;
515 event->hw.event_base = (u64)pcni->vbase + l_config;
516 node_id = cpu_to_node(event->cpu);
519 * Get the imc_pmu_ref struct for this node.
520 * Take the mutex lock and then increment the count of nest pmu events
523 ref = get_nest_pmu_ref(event->cpu);
527 mutex_lock(&ref->lock);
528 if (ref->refc == 0) {
529 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_NEST,
530 get_hard_smp_processor_id(event->cpu));
532 mutex_unlock(&ref->lock);
533 pr_err("nest-imc: Unable to start the counters for node %d\n",
539 mutex_unlock(&ref->lock);
541 event->destroy = nest_imc_counters_release;
546 * core_imc_mem_init : Initializes memory for the current core.
548 * Uses alloc_pages_node() and uses the returned address as an argument to
549 * an opal call to configure the pdbar. The address sent as an argument is
550 * converted to physical address before the opal call is made. This is the
551 * base address at which the core imc counters are populated.
553 static int core_imc_mem_init(int cpu, int size)
555 int nid, rc = 0, core_id = (cpu / threads_per_core);
556 struct imc_mem_info *mem_info;
559 * alloc_pages_node() will allocate memory for core in the
562 nid = cpu_to_node(cpu);
563 mem_info = &core_imc_pmu->mem_info[core_id];
564 mem_info->id = core_id;
566 /* We need only vbase for core counters */
567 mem_info->vbase = page_address(alloc_pages_node(nid,
568 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
569 __GFP_NOWARN, get_order(size)));
570 if (!mem_info->vbase)
574 core_imc_refc[core_id].id = core_id;
575 mutex_init(&core_imc_refc[core_id].lock);
577 rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_CORE,
578 __pa((void *)mem_info->vbase),
579 get_hard_smp_processor_id(cpu));
581 free_pages((u64)mem_info->vbase, get_order(size));
582 mem_info->vbase = NULL;
588 static bool is_core_imc_mem_inited(int cpu)
590 struct imc_mem_info *mem_info;
591 int core_id = (cpu / threads_per_core);
593 mem_info = &core_imc_pmu->mem_info[core_id];
594 if (!mem_info->vbase)
600 static int ppc_core_imc_cpu_online(unsigned int cpu)
602 const struct cpumask *l_cpumask;
603 static struct cpumask tmp_mask;
606 /* Get the cpumask for this core */
607 l_cpumask = cpu_sibling_mask(cpu);
609 /* If a cpu for this core is already set, then, don't do anything */
610 if (cpumask_and(&tmp_mask, l_cpumask, &core_imc_cpumask))
613 if (!is_core_imc_mem_inited(cpu)) {
614 ret = core_imc_mem_init(cpu, core_imc_pmu->counter_mem_size);
616 pr_info("core_imc memory allocation for cpu %d failed\n", cpu);
621 /* set the cpu in the mask */
622 cpumask_set_cpu(cpu, &core_imc_cpumask);
626 static int ppc_core_imc_cpu_offline(unsigned int cpu)
628 unsigned int core_id;
630 struct imc_pmu_ref *ref;
633 * clear this cpu out of the mask, if not present in the mask,
634 * don't bother doing anything.
636 if (!cpumask_test_and_clear_cpu(cpu, &core_imc_cpumask))
640 * Check whether core_imc is registered. We could end up here
641 * if the cpuhotplug callback registration fails. i.e, callback
642 * invokes the offline path for all sucessfully registered cpus.
643 * At this stage, core_imc pmu will not be registered and we
644 * should return here.
646 * We return with a zero since this is not an offline failure.
647 * And cpuhp_setup_state() returns the actual failure reason
648 * to the caller, which inturn will call the cleanup routine.
650 if (!core_imc_pmu->pmu.event_init)
653 /* Find any online cpu in that core except the current "cpu" */
654 ncpu = cpumask_any_but(cpu_sibling_mask(cpu), cpu);
656 if (ncpu >= 0 && ncpu < nr_cpu_ids) {
657 cpumask_set_cpu(ncpu, &core_imc_cpumask);
658 perf_pmu_migrate_context(&core_imc_pmu->pmu, cpu, ncpu);
661 * If this is the last cpu in this core then, skip taking refernce
662 * count mutex lock for this core and directly zero "refc" for
665 opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
666 get_hard_smp_processor_id(cpu));
667 core_id = cpu / threads_per_core;
668 ref = &core_imc_refc[core_id];
677 static int core_imc_pmu_cpumask_init(void)
679 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,
680 "perf/powerpc/imc_core:online",
681 ppc_core_imc_cpu_online,
682 ppc_core_imc_cpu_offline);
685 static void core_imc_counters_release(struct perf_event *event)
688 struct imc_pmu_ref *ref;
693 * See if we need to disable the IMC PMU.
694 * If no events are currently in use, then we have to take a
695 * mutex to ensure that we don't race with another task doing
696 * enable or disable the core counters.
698 core_id = event->cpu / threads_per_core;
700 /* Take the mutex lock and decrement the refernce count for this core */
701 ref = &core_imc_refc[core_id];
705 mutex_lock(&ref->lock);
706 if (ref->refc == 0) {
708 * The scenario where this is true is, when perf session is
709 * started, followed by offlining of all cpus in a given core.
711 * In the cpuhotplug offline path, ppc_core_imc_cpu_offline()
712 * function set the ref->count to zero, if the cpu which is
713 * about to offline is the last cpu in a given core and make
714 * an OPAL call to disable the engine in that core.
717 mutex_unlock(&ref->lock);
721 if (ref->refc == 0) {
722 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
723 get_hard_smp_processor_id(event->cpu));
725 mutex_unlock(&ref->lock);
726 pr_err("IMC: Unable to stop the counters for core %d\n", core_id);
729 } else if (ref->refc < 0) {
730 WARN(1, "core-imc: Invalid event reference count\n");
733 mutex_unlock(&ref->lock);
736 static int core_imc_event_init(struct perf_event *event)
739 u64 config = event->attr.config;
740 struct imc_mem_info *pcmi;
742 struct imc_pmu_ref *ref;
744 if (event->attr.type != event->pmu->type)
747 /* Sampling not supported */
748 if (event->hw.sample_period)
751 /* unsupported modes and filters */
752 if (event->attr.exclude_user ||
753 event->attr.exclude_kernel ||
754 event->attr.exclude_hv ||
755 event->attr.exclude_idle ||
756 event->attr.exclude_host ||
757 event->attr.exclude_guest)
764 pmu = imc_event_to_pmu(event);
766 /* Sanity check for config (event offset) */
767 if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
770 if (!is_core_imc_mem_inited(event->cpu))
773 core_id = event->cpu / threads_per_core;
774 pcmi = &core_imc_pmu->mem_info[core_id];
778 /* Get the core_imc mutex for this core */
779 ref = &core_imc_refc[core_id];
784 * Core pmu units are enabled only when it is used.
785 * See if this is triggered for the first time.
786 * If yes, take the mutex lock and enable the core counters.
787 * If not, just increment the count in core_imc_refc struct.
789 mutex_lock(&ref->lock);
790 if (ref->refc == 0) {
791 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
792 get_hard_smp_processor_id(event->cpu));
794 mutex_unlock(&ref->lock);
795 pr_err("core-imc: Unable to start the counters for core %d\n",
801 mutex_unlock(&ref->lock);
803 event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK);
804 event->destroy = core_imc_counters_release;
809 * Allocates a page of memory for each of the online cpus, and write the
810 * physical base address of that page to the LDBAR for that cpu.
812 * LDBAR Register Layout:
814 * 0 4 8 12 16 20 24 28
815 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
816 * | | [ ] [ Counter Address [8:50]
821 * 32 36 40 44 48 52 56 60
822 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
823 * Counter Address [8:50] ]
826 static int thread_imc_mem_alloc(int cpu_id, int size)
828 u64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, cpu_id);
829 int nid = cpu_to_node(cpu_id);
833 * This case could happen only once at start, since we dont
834 * free the memory in cpu offline path.
836 local_mem = page_address(alloc_pages_node(nid,
837 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
838 __GFP_NOWARN, get_order(size)));
842 per_cpu(thread_imc_mem, cpu_id) = local_mem;
845 ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE;
847 mtspr(SPRN_LDBAR, ldbar_value);
851 static int ppc_thread_imc_cpu_online(unsigned int cpu)
853 return thread_imc_mem_alloc(cpu, thread_imc_mem_size);
856 static int ppc_thread_imc_cpu_offline(unsigned int cpu)
858 mtspr(SPRN_LDBAR, 0);
862 static int thread_imc_cpu_init(void)
864 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,
865 "perf/powerpc/imc_thread:online",
866 ppc_thread_imc_cpu_online,
867 ppc_thread_imc_cpu_offline);
870 static int thread_imc_event_init(struct perf_event *event)
872 u32 config = event->attr.config;
873 struct task_struct *target;
876 if (event->attr.type != event->pmu->type)
879 /* Sampling not supported */
880 if (event->hw.sample_period)
884 pmu = imc_event_to_pmu(event);
886 /* Sanity check for config offset */
887 if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
890 target = event->hw.target;
894 event->pmu->task_ctx_nr = perf_sw_context;
898 static bool is_thread_imc_pmu(struct perf_event *event)
900 if (!strncmp(event->pmu->name, "thread_imc", strlen("thread_imc")))
906 static u64 * get_event_base_addr(struct perf_event *event)
910 if (is_thread_imc_pmu(event)) {
911 addr = (u64)per_cpu(thread_imc_mem, smp_processor_id());
912 return (u64 *)(addr + (event->attr.config & IMC_EVENT_OFFSET_MASK));
915 return (u64 *)event->hw.event_base;
918 static void thread_imc_pmu_start_txn(struct pmu *pmu,
919 unsigned int txn_flags)
921 if (txn_flags & ~PERF_PMU_TXN_ADD)
923 perf_pmu_disable(pmu);
926 static void thread_imc_pmu_cancel_txn(struct pmu *pmu)
928 perf_pmu_enable(pmu);
931 static int thread_imc_pmu_commit_txn(struct pmu *pmu)
933 perf_pmu_enable(pmu);
937 static u64 imc_read_counter(struct perf_event *event)
942 * In-Memory Collection (IMC) counters are free flowing counters.
943 * So we take a snapshot of the counter value on enable and save it
944 * to calculate the delta at later stage to present the event counter
947 addr = get_event_base_addr(event);
948 data = be64_to_cpu(READ_ONCE(*addr));
949 local64_set(&event->hw.prev_count, data);
954 static void imc_event_update(struct perf_event *event)
956 u64 counter_prev, counter_new, final_count;
958 counter_prev = local64_read(&event->hw.prev_count);
959 counter_new = imc_read_counter(event);
960 final_count = counter_new - counter_prev;
962 /* Update the delta to the event count */
963 local64_add(final_count, &event->count);
966 static void imc_event_start(struct perf_event *event, int flags)
969 * In Memory Counters are free flowing counters. HW or the microcode
970 * keeps adding to the counter offset in memory. To get event
971 * counter value, we snapshot the value here and we calculate
972 * delta at later point.
974 imc_read_counter(event);
977 static void imc_event_stop(struct perf_event *event, int flags)
980 * Take a snapshot and calculate the delta and update
981 * the event counter values.
983 imc_event_update(event);
986 static int imc_event_add(struct perf_event *event, int flags)
988 if (flags & PERF_EF_START)
989 imc_event_start(event, flags);
994 static int thread_imc_event_add(struct perf_event *event, int flags)
997 struct imc_pmu_ref *ref;
999 if (flags & PERF_EF_START)
1000 imc_event_start(event, flags);
1002 if (!is_core_imc_mem_inited(smp_processor_id()))
1005 core_id = smp_processor_id() / threads_per_core;
1007 * imc pmus are enabled only when it is used.
1008 * See if this is triggered for the first time.
1009 * If yes, take the mutex lock and enable the counters.
1010 * If not, just increment the count in ref count struct.
1012 ref = &core_imc_refc[core_id];
1016 mutex_lock(&ref->lock);
1017 if (ref->refc == 0) {
1018 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
1019 get_hard_smp_processor_id(smp_processor_id()))) {
1020 mutex_unlock(&ref->lock);
1021 pr_err("thread-imc: Unable to start the counter\
1022 for core %d\n", core_id);
1027 mutex_unlock(&ref->lock);
1031 static void thread_imc_event_del(struct perf_event *event, int flags)
1035 struct imc_pmu_ref *ref;
1038 * Take a snapshot and calculate the delta and update
1039 * the event counter values.
1041 imc_event_update(event);
1043 core_id = smp_processor_id() / threads_per_core;
1044 ref = &core_imc_refc[core_id];
1046 mutex_lock(&ref->lock);
1048 if (ref->refc == 0) {
1049 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
1050 get_hard_smp_processor_id(smp_processor_id()))) {
1051 mutex_unlock(&ref->lock);
1052 pr_err("thread-imc: Unable to stop the counters\
1053 for core %d\n", core_id);
1056 } else if (ref->refc < 0) {
1059 mutex_unlock(&ref->lock);
1062 /* update_pmu_ops : Populate the appropriate operations for "pmu" */
1063 static int update_pmu_ops(struct imc_pmu *pmu)
1065 pmu->pmu.task_ctx_nr = perf_invalid_context;
1066 pmu->pmu.add = imc_event_add;
1067 pmu->pmu.del = imc_event_stop;
1068 pmu->pmu.start = imc_event_start;
1069 pmu->pmu.stop = imc_event_stop;
1070 pmu->pmu.read = imc_event_update;
1071 pmu->pmu.attr_groups = pmu->attr_groups;
1072 pmu->attr_groups[IMC_FORMAT_ATTR] = &imc_format_group;
1074 switch (pmu->domain) {
1075 case IMC_DOMAIN_NEST:
1076 pmu->pmu.event_init = nest_imc_event_init;
1077 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1079 case IMC_DOMAIN_CORE:
1080 pmu->pmu.event_init = core_imc_event_init;
1081 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1083 case IMC_DOMAIN_THREAD:
1084 pmu->pmu.event_init = thread_imc_event_init;
1085 pmu->pmu.add = thread_imc_event_add;
1086 pmu->pmu.del = thread_imc_event_del;
1087 pmu->pmu.start_txn = thread_imc_pmu_start_txn;
1088 pmu->pmu.cancel_txn = thread_imc_pmu_cancel_txn;
1089 pmu->pmu.commit_txn = thread_imc_pmu_commit_txn;
1098 /* init_nest_pmu_ref: Initialize the imc_pmu_ref struct for all the nodes */
1099 static int init_nest_pmu_ref(void)
1103 nest_imc_refc = kcalloc(num_possible_nodes(), sizeof(*nest_imc_refc),
1110 for_each_node(nid) {
1112 * Mutex lock to avoid races while tracking the number of
1113 * sessions using the chip's nest pmu units.
1115 mutex_init(&nest_imc_refc[i].lock);
1118 * Loop to init the "id" with the node_id. Variable "i" initialized to
1119 * 0 and will be used as index to the array. "i" will not go off the
1120 * end of the array since the "for_each_node" loops for "N_POSSIBLE"
1123 nest_imc_refc[i++].id = nid;
1127 * Loop to init the per_cpu "local_nest_imc_refc" with the proper
1128 * "nest_imc_refc" index. This makes get_nest_pmu_ref() alot simple.
1130 for_each_possible_cpu(cpu) {
1131 nid = cpu_to_node(cpu);
1132 for (i = 0; i < num_possible_nodes(); i++) {
1133 if (nest_imc_refc[i].id == nid) {
1134 per_cpu(local_nest_imc_refc, cpu) = &nest_imc_refc[i];
1142 static void cleanup_all_core_imc_memory(void)
1144 int i, nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1145 struct imc_mem_info *ptr = core_imc_pmu->mem_info;
1146 int size = core_imc_pmu->counter_mem_size;
1148 /* mem_info will never be NULL */
1149 for (i = 0; i < nr_cores; i++) {
1151 free_pages((u64)ptr[i].vbase, get_order(size));
1155 kfree(core_imc_refc);
1158 static void thread_imc_ldbar_disable(void *dummy)
1161 * By Zeroing LDBAR, we disable thread-imc
1164 mtspr(SPRN_LDBAR, 0);
1167 void thread_imc_disable(void)
1169 on_each_cpu(thread_imc_ldbar_disable, NULL, 1);
1172 static void cleanup_all_thread_imc_memory(void)
1174 int i, order = get_order(thread_imc_mem_size);
1176 for_each_online_cpu(i) {
1177 if (per_cpu(thread_imc_mem, i))
1178 free_pages((u64)per_cpu(thread_imc_mem, i), order);
1183 /* Function to free the attr_groups which are dynamically allocated */
1184 static void imc_common_mem_free(struct imc_pmu *pmu_ptr)
1186 if (pmu_ptr->attr_groups[IMC_EVENT_ATTR])
1187 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs);
1188 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]);
1192 * Common function to unregister cpu hotplug callback and
1194 * TODO: Need to handle pmu unregistering, which will be
1195 * done in followup series.
1197 static void imc_common_cpuhp_mem_free(struct imc_pmu *pmu_ptr)
1199 if (pmu_ptr->domain == IMC_DOMAIN_NEST) {
1200 mutex_lock(&nest_init_lock);
1201 if (nest_pmus == 1) {
1202 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE);
1203 kfree(nest_imc_refc);
1204 kfree(per_nest_pmu_arr);
1205 per_nest_pmu_arr = NULL;
1210 mutex_unlock(&nest_init_lock);
1213 /* Free core_imc memory */
1214 if (pmu_ptr->domain == IMC_DOMAIN_CORE) {
1215 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE);
1216 cleanup_all_core_imc_memory();
1219 /* Free thread_imc memory */
1220 if (pmu_ptr->domain == IMC_DOMAIN_THREAD) {
1221 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE);
1222 cleanup_all_thread_imc_memory();
1227 * Function to unregister thread-imc if core-imc
1228 * is not registered.
1230 void unregister_thread_imc(void)
1232 imc_common_cpuhp_mem_free(thread_imc_pmu);
1233 imc_common_mem_free(thread_imc_pmu);
1234 perf_pmu_unregister(&thread_imc_pmu->pmu);
1238 * imc_mem_init : Function to support memory allocation for core imc.
1240 static int imc_mem_init(struct imc_pmu *pmu_ptr, struct device_node *parent,
1244 int nr_cores, cpu, res = -ENOMEM;
1246 if (of_property_read_string(parent, "name", &s))
1249 switch (pmu_ptr->domain) {
1250 case IMC_DOMAIN_NEST:
1251 /* Update the pmu name */
1252 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s_imc", "nest_", s);
1253 if (!pmu_ptr->pmu.name)
1256 /* Needed for hotplug/migration */
1257 if (!per_nest_pmu_arr) {
1258 per_nest_pmu_arr = kcalloc(get_max_nest_dev() + 1,
1259 sizeof(struct imc_pmu *),
1261 if (!per_nest_pmu_arr)
1264 per_nest_pmu_arr[pmu_index] = pmu_ptr;
1266 case IMC_DOMAIN_CORE:
1267 /* Update the pmu name */
1268 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1269 if (!pmu_ptr->pmu.name)
1272 nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1273 pmu_ptr->mem_info = kcalloc(nr_cores, sizeof(struct imc_mem_info),
1276 if (!pmu_ptr->mem_info)
1279 core_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1282 if (!core_imc_refc) {
1283 kfree(pmu_ptr->mem_info);
1287 core_imc_pmu = pmu_ptr;
1289 case IMC_DOMAIN_THREAD:
1290 /* Update the pmu name */
1291 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1292 if (!pmu_ptr->pmu.name)
1295 thread_imc_mem_size = pmu_ptr->counter_mem_size;
1296 for_each_online_cpu(cpu) {
1297 res = thread_imc_mem_alloc(cpu, pmu_ptr->counter_mem_size);
1299 cleanup_all_thread_imc_memory();
1304 thread_imc_pmu = pmu_ptr;
1316 * init_imc_pmu : Setup and register the IMC pmu device.
1318 * @parent: Device tree unit node
1319 * @pmu_ptr: memory allocated for this pmu
1320 * @pmu_idx: Count of nest pmc registered
1322 * init_imc_pmu() setup pmu cpumask and registers for a cpu hotplug callback.
1323 * Handles failure cases and accordingly frees memory.
1325 int init_imc_pmu(struct device_node *parent, struct imc_pmu *pmu_ptr, int pmu_idx)
1329 ret = imc_mem_init(pmu_ptr, parent, pmu_idx);
1333 switch (pmu_ptr->domain) {
1334 case IMC_DOMAIN_NEST:
1336 * Nest imc pmu need only one cpu per chip, we initialize the
1337 * cpumask for the first nest imc pmu and use the same for the
1338 * rest. To handle the cpuhotplug callback unregister, we track
1339 * the number of nest pmus in "nest_pmus".
1341 mutex_lock(&nest_init_lock);
1342 if (nest_pmus == 0) {
1343 ret = init_nest_pmu_ref();
1345 mutex_unlock(&nest_init_lock);
1346 kfree(per_nest_pmu_arr);
1347 per_nest_pmu_arr = NULL;
1350 /* Register for cpu hotplug notification. */
1351 ret = nest_pmu_cpumask_init();
1353 mutex_unlock(&nest_init_lock);
1354 kfree(nest_imc_refc);
1355 kfree(per_nest_pmu_arr);
1356 per_nest_pmu_arr = NULL;
1361 mutex_unlock(&nest_init_lock);
1363 case IMC_DOMAIN_CORE:
1364 ret = core_imc_pmu_cpumask_init();
1366 cleanup_all_core_imc_memory();
1371 case IMC_DOMAIN_THREAD:
1372 ret = thread_imc_cpu_init();
1374 cleanup_all_thread_imc_memory();
1380 return -EINVAL; /* Unknown domain */
1383 ret = update_events_in_group(parent, pmu_ptr);
1385 goto err_free_cpuhp_mem;
1387 ret = update_pmu_ops(pmu_ptr);
1389 goto err_free_cpuhp_mem;
1391 ret = perf_pmu_register(&pmu_ptr->pmu, pmu_ptr->pmu.name, -1);
1393 goto err_free_cpuhp_mem;
1395 pr_debug("%s performance monitor hardware support registered\n",
1401 imc_common_cpuhp_mem_free(pmu_ptr);
1403 imc_common_mem_free(pmu_ptr);