2 * In-Memory Collection (IMC) Performance Monitor counter support.
4 * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
5 * (C) 2017 Anju T Sudhakar, IBM Corporation.
6 * (C) 2017 Hemant K Shaw, IBM Corporation.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or later version.
13 #include <linux/perf_event.h>
14 #include <linux/slab.h>
16 #include <asm/imc-pmu.h>
17 #include <asm/cputhreads.h>
19 #include <linux/string.h>
21 /* Nest IMC data structures and variables */
24 * Used to avoid races in counting the nest-pmu units during hotplug
25 * register and unregister
27 static DEFINE_MUTEX(nest_init_lock);
28 static DEFINE_PER_CPU(struct imc_pmu_ref *, local_nest_imc_refc);
29 static struct imc_pmu **per_nest_pmu_arr;
30 static cpumask_t nest_imc_cpumask;
31 struct imc_pmu_ref *nest_imc_refc;
34 /* Core IMC data structures and variables */
36 static cpumask_t core_imc_cpumask;
37 struct imc_pmu_ref *core_imc_refc;
38 static struct imc_pmu *core_imc_pmu;
40 /* Thread IMC data structures and variables */
42 static DEFINE_PER_CPU(u64 *, thread_imc_mem);
43 static struct imc_pmu *thread_imc_pmu;
44 static int thread_imc_mem_size;
46 struct imc_pmu *imc_event_to_pmu(struct perf_event *event)
48 return container_of(event->pmu, struct imc_pmu, pmu);
51 PMU_FORMAT_ATTR(event, "config:0-40");
52 PMU_FORMAT_ATTR(offset, "config:0-31");
53 PMU_FORMAT_ATTR(rvalue, "config:32");
54 PMU_FORMAT_ATTR(mode, "config:33-40");
55 static struct attribute *imc_format_attrs[] = {
56 &format_attr_event.attr,
57 &format_attr_offset.attr,
58 &format_attr_rvalue.attr,
59 &format_attr_mode.attr,
63 static struct attribute_group imc_format_group = {
65 .attrs = imc_format_attrs,
68 /* Get the cpumask printed to a buffer "buf" */
69 static ssize_t imc_pmu_cpumask_get_attr(struct device *dev,
70 struct device_attribute *attr,
73 struct pmu *pmu = dev_get_drvdata(dev);
74 struct imc_pmu *imc_pmu = container_of(pmu, struct imc_pmu, pmu);
75 cpumask_t *active_mask;
77 switch(imc_pmu->domain){
79 active_mask = &nest_imc_cpumask;
82 active_mask = &core_imc_cpumask;
88 return cpumap_print_to_pagebuf(true, buf, active_mask);
91 static DEVICE_ATTR(cpumask, S_IRUGO, imc_pmu_cpumask_get_attr, NULL);
93 static struct attribute *imc_pmu_cpumask_attrs[] = {
94 &dev_attr_cpumask.attr,
98 static struct attribute_group imc_pmu_cpumask_attr_group = {
99 .attrs = imc_pmu_cpumask_attrs,
102 /* device_str_attr_create : Populate event "name" and string "str" in attribute */
103 static struct attribute *device_str_attr_create(const char *name, const char *str)
105 struct perf_pmu_events_attr *attr;
107 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
110 sysfs_attr_init(&attr->attr.attr);
112 attr->event_str = str;
113 attr->attr.attr.name = name;
114 attr->attr.attr.mode = 0444;
115 attr->attr.show = perf_event_sysfs_show;
117 return &attr->attr.attr;
120 struct imc_events *imc_parse_event(struct device_node *np, const char *scale,
121 const char *unit, const char *prefix, u32 base)
123 struct imc_events *event;
127 event = kzalloc(sizeof(struct imc_events), GFP_KERNEL);
131 if (of_property_read_u32(np, "reg", ®))
133 /* Add the base_reg value to the "reg" */
134 event->value = base + reg;
136 if (of_property_read_string(np, "event-name", &s))
139 event->name = kasprintf(GFP_KERNEL, "%s%s", prefix, s);
143 if (of_property_read_string(np, "scale", &s))
147 event->scale = kstrdup(s, GFP_KERNEL);
152 if (of_property_read_string(np, "unit", &s))
156 event->unit = kstrdup(s, GFP_KERNEL);
172 * update_events_in_group: Update the "events" information in an attr_group
173 * and assign the attr_group to the pmu "pmu".
175 static int update_events_in_group(struct device_node *node, struct imc_pmu *pmu)
177 struct attribute_group *attr_group;
178 struct attribute **attrs, *dev_str;
179 struct device_node *np, *pmu_events;
180 struct imc_events *ev;
181 u32 handle, base_reg;
183 const char *prefix, *g_scale, *g_unit;
184 const char *ev_val_str, *ev_scale_str, *ev_unit_str;
186 if (!of_property_read_u32(node, "events", &handle))
187 pmu_events = of_find_node_by_phandle(handle);
191 /* Did not find any node with a given phandle */
195 /* Get a count of number of child nodes */
196 ct = of_get_child_count(pmu_events);
198 /* Get the event prefix */
199 if (of_property_read_string(node, "events-prefix", &prefix))
202 /* Get a global unit and scale data if available */
203 if (of_property_read_string(node, "scale", &g_scale))
206 if (of_property_read_string(node, "unit", &g_unit))
209 /* "reg" property gives out the base offset of the counters data */
210 of_property_read_u32(node, "reg", &base_reg);
212 /* Allocate memory for the events */
213 pmu->events = kcalloc(ct, sizeof(struct imc_events), GFP_KERNEL);
218 /* Parse the events and update the struct */
219 for_each_child_of_node(pmu_events, np) {
220 ev = imc_parse_event(np, g_scale, g_unit, prefix, base_reg);
222 pmu->events[ct++] = ev;
225 /* Allocate memory for attribute group */
226 attr_group = kzalloc(sizeof(*attr_group), GFP_KERNEL);
231 * Allocate memory for attributes.
232 * Since we have count of events for this pmu, we also allocate
233 * memory for the scale and unit attribute for now.
234 * "ct" has the total event structs added from the events-parent node.
235 * So allocate three times the "ct" (this includes event, event_scale and
238 attrs = kcalloc(((ct * 3) + 1), sizeof(struct attribute *), GFP_KERNEL);
245 attr_group->name = "events";
246 attr_group->attrs = attrs;
248 ev_val_str = kasprintf(GFP_KERNEL, "event=0x%x", pmu->events[i]->value);
249 dev_str = device_str_attr_create(pmu->events[i]->name, ev_val_str);
253 attrs[j++] = dev_str;
254 if (pmu->events[i]->scale) {
255 ev_scale_str = kasprintf(GFP_KERNEL, "%s.scale",pmu->events[i]->name);
256 dev_str = device_str_attr_create(ev_scale_str, pmu->events[i]->scale);
260 attrs[j++] = dev_str;
263 if (pmu->events[i]->unit) {
264 ev_unit_str = kasprintf(GFP_KERNEL, "%s.unit",pmu->events[i]->name);
265 dev_str = device_str_attr_create(ev_unit_str, pmu->events[i]->unit);
269 attrs[j++] = dev_str;
273 /* Save the event attribute */
274 pmu->attr_groups[IMC_EVENT_ATTR] = attr_group;
280 /* get_nest_pmu_ref: Return the imc_pmu_ref struct for the given node */
281 static struct imc_pmu_ref *get_nest_pmu_ref(int cpu)
283 return per_cpu(local_nest_imc_refc, cpu);
286 static void nest_change_cpu_context(int old_cpu, int new_cpu)
288 struct imc_pmu **pn = per_nest_pmu_arr;
290 if (old_cpu < 0 || new_cpu < 0)
294 perf_pmu_migrate_context(&(*pn)->pmu, old_cpu, new_cpu);
299 static int ppc_nest_imc_cpu_offline(unsigned int cpu)
301 int nid, target = -1;
302 const struct cpumask *l_cpumask;
303 struct imc_pmu_ref *ref;
306 * Check in the designated list for this cpu. Dont bother
307 * if not one of them.
309 if (!cpumask_test_and_clear_cpu(cpu, &nest_imc_cpumask))
313 * Now that this cpu is one of the designated,
314 * find a next cpu a) which is online and b) in same chip.
316 nid = cpu_to_node(cpu);
317 l_cpumask = cpumask_of_node(nid);
318 target = cpumask_any_but(l_cpumask, cpu);
321 * Update the cpumask with the target cpu and
322 * migrate the context if needed
324 if (target >= 0 && target < nr_cpu_ids) {
325 cpumask_set_cpu(target, &nest_imc_cpumask);
326 nest_change_cpu_context(cpu, target);
328 opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
329 get_hard_smp_processor_id(cpu));
331 * If this is the last cpu in this chip then, skip the reference
332 * count mutex lock and make the reference count on this chip zero.
334 ref = get_nest_pmu_ref(cpu);
343 static int ppc_nest_imc_cpu_online(unsigned int cpu)
345 const struct cpumask *l_cpumask;
346 static struct cpumask tmp_mask;
349 /* Get the cpumask of this node */
350 l_cpumask = cpumask_of_node(cpu_to_node(cpu));
353 * If this is not the first online CPU on this node, then
356 if (cpumask_and(&tmp_mask, l_cpumask, &nest_imc_cpumask))
360 * If this is the first online cpu on this node
361 * disable the nest counters by making an OPAL call.
363 res = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
364 get_hard_smp_processor_id(cpu));
368 /* Make this CPU the designated target for counter collection */
369 cpumask_set_cpu(cpu, &nest_imc_cpumask);
373 static int nest_pmu_cpumask_init(void)
375 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE,
376 "perf/powerpc/imc:online",
377 ppc_nest_imc_cpu_online,
378 ppc_nest_imc_cpu_offline);
381 static void nest_imc_counters_release(struct perf_event *event)
384 struct imc_pmu_ref *ref;
389 node_id = cpu_to_node(event->cpu);
392 * See if we need to disable the nest PMU.
393 * If no events are currently in use, then we have to take a
394 * mutex to ensure that we don't race with another task doing
395 * enable or disable the nest counters.
397 ref = get_nest_pmu_ref(event->cpu);
401 /* Take the mutex lock for this node and then decrement the reference count */
402 mutex_lock(&ref->lock);
403 if (ref->refc == 0) {
405 * The scenario where this is true is, when perf session is
406 * started, followed by offlining of all cpus in a given node.
408 * In the cpuhotplug offline path, ppc_nest_imc_cpu_offline()
409 * function set the ref->count to zero, if the cpu which is
410 * about to offline is the last cpu in a given node and make
411 * an OPAL call to disable the engine in that node.
414 mutex_unlock(&ref->lock);
418 if (ref->refc == 0) {
419 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
420 get_hard_smp_processor_id(event->cpu));
422 mutex_unlock(&ref->lock);
423 pr_err("nest-imc: Unable to stop the counters for core %d\n", node_id);
426 } else if (ref->refc < 0) {
427 WARN(1, "nest-imc: Invalid event reference count\n");
430 mutex_unlock(&ref->lock);
433 static int nest_imc_event_init(struct perf_event *event)
435 int chip_id, rc, node_id;
436 u32 l_config, config = event->attr.config;
437 struct imc_mem_info *pcni;
439 struct imc_pmu_ref *ref;
442 if (event->attr.type != event->pmu->type)
445 /* Sampling not supported */
446 if (event->hw.sample_period)
449 /* unsupported modes and filters */
450 if (event->attr.exclude_user ||
451 event->attr.exclude_kernel ||
452 event->attr.exclude_hv ||
453 event->attr.exclude_idle ||
454 event->attr.exclude_host ||
455 event->attr.exclude_guest)
461 pmu = imc_event_to_pmu(event);
463 /* Sanity check for config (event offset) */
464 if ((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size)
468 * Nest HW counter memory resides in a per-chip reserve-memory (HOMER).
469 * Get the base memory addresss for this cpu.
471 chip_id = cpu_to_chip_id(event->cpu);
472 pcni = pmu->mem_info;
474 if (pcni->id == chip_id) {
485 * Add the event offset to the base address.
487 l_config = config & IMC_EVENT_OFFSET_MASK;
488 event->hw.event_base = (u64)pcni->vbase + l_config;
489 node_id = cpu_to_node(event->cpu);
492 * Get the imc_pmu_ref struct for this node.
493 * Take the mutex lock and then increment the count of nest pmu events
496 ref = get_nest_pmu_ref(event->cpu);
500 mutex_lock(&ref->lock);
501 if (ref->refc == 0) {
502 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_NEST,
503 get_hard_smp_processor_id(event->cpu));
505 mutex_unlock(&ref->lock);
506 pr_err("nest-imc: Unable to start the counters for node %d\n",
512 mutex_unlock(&ref->lock);
514 event->destroy = nest_imc_counters_release;
519 * core_imc_mem_init : Initializes memory for the current core.
521 * Uses alloc_pages_node() and uses the returned address as an argument to
522 * an opal call to configure the pdbar. The address sent as an argument is
523 * converted to physical address before the opal call is made. This is the
524 * base address at which the core imc counters are populated.
526 static int core_imc_mem_init(int cpu, int size)
528 int nid, rc = 0, core_id = (cpu / threads_per_core);
529 struct imc_mem_info *mem_info;
532 * alloc_pages_node() will allocate memory for core in the
535 nid = cpu_to_node(cpu);
536 mem_info = &core_imc_pmu->mem_info[core_id];
537 mem_info->id = core_id;
539 /* We need only vbase for core counters */
540 mem_info->vbase = page_address(alloc_pages_node(nid,
541 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
542 __GFP_NOWARN, get_order(size)));
543 if (!mem_info->vbase)
547 core_imc_refc[core_id].id = core_id;
548 mutex_init(&core_imc_refc[core_id].lock);
550 rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_CORE,
551 __pa((void *)mem_info->vbase),
552 get_hard_smp_processor_id(cpu));
554 free_pages((u64)mem_info->vbase, get_order(size));
555 mem_info->vbase = NULL;
561 static bool is_core_imc_mem_inited(int cpu)
563 struct imc_mem_info *mem_info;
564 int core_id = (cpu / threads_per_core);
566 mem_info = &core_imc_pmu->mem_info[core_id];
567 if (!mem_info->vbase)
573 static int ppc_core_imc_cpu_online(unsigned int cpu)
575 const struct cpumask *l_cpumask;
576 static struct cpumask tmp_mask;
579 /* Get the cpumask for this core */
580 l_cpumask = cpu_sibling_mask(cpu);
582 /* If a cpu for this core is already set, then, don't do anything */
583 if (cpumask_and(&tmp_mask, l_cpumask, &core_imc_cpumask))
586 if (!is_core_imc_mem_inited(cpu)) {
587 ret = core_imc_mem_init(cpu, core_imc_pmu->counter_mem_size);
589 pr_info("core_imc memory allocation for cpu %d failed\n", cpu);
594 /* set the cpu in the mask */
595 cpumask_set_cpu(cpu, &core_imc_cpumask);
599 static int ppc_core_imc_cpu_offline(unsigned int cpu)
601 unsigned int ncpu, core_id;
602 struct imc_pmu_ref *ref;
605 * clear this cpu out of the mask, if not present in the mask,
606 * don't bother doing anything.
608 if (!cpumask_test_and_clear_cpu(cpu, &core_imc_cpumask))
612 * Check whether core_imc is registered. We could end up here
613 * if the cpuhotplug callback registration fails. i.e, callback
614 * invokes the offline path for all sucessfully registered cpus.
615 * At this stage, core_imc pmu will not be registered and we
616 * should return here.
618 * We return with a zero since this is not an offline failure.
619 * And cpuhp_setup_state() returns the actual failure reason
620 * to the caller, which inturn will call the cleanup routine.
622 if (!core_imc_pmu->pmu.event_init)
625 /* Find any online cpu in that core except the current "cpu" */
626 ncpu = cpumask_any_but(cpu_sibling_mask(cpu), cpu);
628 if (ncpu >= 0 && ncpu < nr_cpu_ids) {
629 cpumask_set_cpu(ncpu, &core_imc_cpumask);
630 perf_pmu_migrate_context(&core_imc_pmu->pmu, cpu, ncpu);
633 * If this is the last cpu in this core then, skip taking refernce
634 * count mutex lock for this core and directly zero "refc" for
637 opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
638 get_hard_smp_processor_id(cpu));
639 core_id = cpu / threads_per_core;
640 ref = &core_imc_refc[core_id];
649 static int core_imc_pmu_cpumask_init(void)
651 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,
652 "perf/powerpc/imc_core:online",
653 ppc_core_imc_cpu_online,
654 ppc_core_imc_cpu_offline);
657 static void core_imc_counters_release(struct perf_event *event)
660 struct imc_pmu_ref *ref;
665 * See if we need to disable the IMC PMU.
666 * If no events are currently in use, then we have to take a
667 * mutex to ensure that we don't race with another task doing
668 * enable or disable the core counters.
670 core_id = event->cpu / threads_per_core;
672 /* Take the mutex lock and decrement the refernce count for this core */
673 ref = &core_imc_refc[core_id];
677 mutex_lock(&ref->lock);
678 if (ref->refc == 0) {
680 * The scenario where this is true is, when perf session is
681 * started, followed by offlining of all cpus in a given core.
683 * In the cpuhotplug offline path, ppc_core_imc_cpu_offline()
684 * function set the ref->count to zero, if the cpu which is
685 * about to offline is the last cpu in a given core and make
686 * an OPAL call to disable the engine in that core.
689 mutex_unlock(&ref->lock);
693 if (ref->refc == 0) {
694 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
695 get_hard_smp_processor_id(event->cpu));
697 mutex_unlock(&ref->lock);
698 pr_err("IMC: Unable to stop the counters for core %d\n", core_id);
701 } else if (ref->refc < 0) {
702 WARN(1, "core-imc: Invalid event reference count\n");
705 mutex_unlock(&ref->lock);
708 static int core_imc_event_init(struct perf_event *event)
711 u64 config = event->attr.config;
712 struct imc_mem_info *pcmi;
714 struct imc_pmu_ref *ref;
716 if (event->attr.type != event->pmu->type)
719 /* Sampling not supported */
720 if (event->hw.sample_period)
723 /* unsupported modes and filters */
724 if (event->attr.exclude_user ||
725 event->attr.exclude_kernel ||
726 event->attr.exclude_hv ||
727 event->attr.exclude_idle ||
728 event->attr.exclude_host ||
729 event->attr.exclude_guest)
736 pmu = imc_event_to_pmu(event);
738 /* Sanity check for config (event offset) */
739 if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
742 if (!is_core_imc_mem_inited(event->cpu))
745 core_id = event->cpu / threads_per_core;
746 pcmi = &core_imc_pmu->mem_info[core_id];
750 /* Get the core_imc mutex for this core */
751 ref = &core_imc_refc[core_id];
756 * Core pmu units are enabled only when it is used.
757 * See if this is triggered for the first time.
758 * If yes, take the mutex lock and enable the core counters.
759 * If not, just increment the count in core_imc_refc struct.
761 mutex_lock(&ref->lock);
762 if (ref->refc == 0) {
763 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
764 get_hard_smp_processor_id(event->cpu));
766 mutex_unlock(&ref->lock);
767 pr_err("core-imc: Unable to start the counters for core %d\n",
773 mutex_unlock(&ref->lock);
775 event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK);
776 event->destroy = core_imc_counters_release;
781 * Allocates a page of memory for each of the online cpus, and write the
782 * physical base address of that page to the LDBAR for that cpu.
784 * LDBAR Register Layout:
786 * 0 4 8 12 16 20 24 28
787 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
788 * | | [ ] [ Counter Address [8:50]
793 * 32 36 40 44 48 52 56 60
794 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
795 * Counter Address [8:50] ]
798 static int thread_imc_mem_alloc(int cpu_id, int size)
800 u64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, cpu_id);
801 int nid = cpu_to_node(cpu_id);
805 * This case could happen only once at start, since we dont
806 * free the memory in cpu offline path.
808 local_mem = page_address(alloc_pages_node(nid,
809 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
810 __GFP_NOWARN, get_order(size)));
814 per_cpu(thread_imc_mem, cpu_id) = local_mem;
817 ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE;
819 mtspr(SPRN_LDBAR, ldbar_value);
823 static int ppc_thread_imc_cpu_online(unsigned int cpu)
825 return thread_imc_mem_alloc(cpu, thread_imc_mem_size);
828 static int ppc_thread_imc_cpu_offline(unsigned int cpu)
830 mtspr(SPRN_LDBAR, 0);
834 static int thread_imc_cpu_init(void)
836 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,
837 "perf/powerpc/imc_thread:online",
838 ppc_thread_imc_cpu_online,
839 ppc_thread_imc_cpu_offline);
842 void thread_imc_pmu_sched_task(struct perf_event_context *ctx,
846 struct imc_pmu_ref *ref;
848 if (!is_core_imc_mem_inited(smp_processor_id()))
851 core_id = smp_processor_id() / threads_per_core;
853 * imc pmus are enabled only when it is used.
854 * See if this is triggered for the first time.
855 * If yes, take the mutex lock and enable the counters.
856 * If not, just increment the count in ref count struct.
858 ref = &core_imc_refc[core_id];
863 mutex_lock(&ref->lock);
864 if (ref->refc == 0) {
865 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
866 get_hard_smp_processor_id(smp_processor_id()))) {
867 mutex_unlock(&ref->lock);
868 pr_err("thread-imc: Unable to start the counter\
869 for core %d\n", core_id);
874 mutex_unlock(&ref->lock);
876 mutex_lock(&ref->lock);
878 if (ref->refc == 0) {
879 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
880 get_hard_smp_processor_id(smp_processor_id()))) {
881 mutex_unlock(&ref->lock);
882 pr_err("thread-imc: Unable to stop the counters\
883 for core %d\n", core_id);
886 } else if (ref->refc < 0) {
889 mutex_unlock(&ref->lock);
895 static int thread_imc_event_init(struct perf_event *event)
897 u32 config = event->attr.config;
898 struct task_struct *target;
901 if (event->attr.type != event->pmu->type)
904 /* Sampling not supported */
905 if (event->hw.sample_period)
909 pmu = imc_event_to_pmu(event);
911 /* Sanity check for config offset */
912 if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
915 target = event->hw.target;
919 event->pmu->task_ctx_nr = perf_sw_context;
923 static bool is_thread_imc_pmu(struct perf_event *event)
925 if (!strncmp(event->pmu->name, "thread_imc", strlen("thread_imc")))
931 static u64 * get_event_base_addr(struct perf_event *event)
935 if (is_thread_imc_pmu(event)) {
936 addr = (u64)per_cpu(thread_imc_mem, smp_processor_id());
937 return (u64 *)(addr + (event->attr.config & IMC_EVENT_OFFSET_MASK));
940 return (u64 *)event->hw.event_base;
943 static void thread_imc_pmu_start_txn(struct pmu *pmu,
944 unsigned int txn_flags)
946 if (txn_flags & ~PERF_PMU_TXN_ADD)
948 perf_pmu_disable(pmu);
951 static void thread_imc_pmu_cancel_txn(struct pmu *pmu)
953 perf_pmu_enable(pmu);
956 static int thread_imc_pmu_commit_txn(struct pmu *pmu)
958 perf_pmu_enable(pmu);
962 static u64 imc_read_counter(struct perf_event *event)
967 * In-Memory Collection (IMC) counters are free flowing counters.
968 * So we take a snapshot of the counter value on enable and save it
969 * to calculate the delta at later stage to present the event counter
972 addr = get_event_base_addr(event);
973 data = be64_to_cpu(READ_ONCE(*addr));
974 local64_set(&event->hw.prev_count, data);
979 static void imc_event_update(struct perf_event *event)
981 u64 counter_prev, counter_new, final_count;
983 counter_prev = local64_read(&event->hw.prev_count);
984 counter_new = imc_read_counter(event);
985 final_count = counter_new - counter_prev;
987 /* Update the delta to the event count */
988 local64_add(final_count, &event->count);
991 static void imc_event_start(struct perf_event *event, int flags)
994 * In Memory Counters are free flowing counters. HW or the microcode
995 * keeps adding to the counter offset in memory. To get event
996 * counter value, we snapshot the value here and we calculate
997 * delta at later point.
999 imc_read_counter(event);
1002 static void imc_event_stop(struct perf_event *event, int flags)
1005 * Take a snapshot and calculate the delta and update
1006 * the event counter values.
1008 imc_event_update(event);
1011 static int imc_event_add(struct perf_event *event, int flags)
1013 if (flags & PERF_EF_START)
1014 imc_event_start(event, flags);
1019 static int thread_imc_event_add(struct perf_event *event, int flags)
1021 if (flags & PERF_EF_START)
1022 imc_event_start(event, flags);
1024 /* Enable the sched_task to start the engine */
1025 perf_sched_cb_inc(event->ctx->pmu);
1029 static void thread_imc_event_del(struct perf_event *event, int flags)
1032 * Take a snapshot and calculate the delta and update
1033 * the event counter values.
1035 imc_event_update(event);
1036 perf_sched_cb_dec(event->ctx->pmu);
1039 /* update_pmu_ops : Populate the appropriate operations for "pmu" */
1040 static int update_pmu_ops(struct imc_pmu *pmu)
1042 pmu->pmu.task_ctx_nr = perf_invalid_context;
1043 pmu->pmu.add = imc_event_add;
1044 pmu->pmu.del = imc_event_stop;
1045 pmu->pmu.start = imc_event_start;
1046 pmu->pmu.stop = imc_event_stop;
1047 pmu->pmu.read = imc_event_update;
1048 pmu->pmu.attr_groups = pmu->attr_groups;
1049 pmu->attr_groups[IMC_FORMAT_ATTR] = &imc_format_group;
1051 switch (pmu->domain) {
1052 case IMC_DOMAIN_NEST:
1053 pmu->pmu.event_init = nest_imc_event_init;
1054 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1056 case IMC_DOMAIN_CORE:
1057 pmu->pmu.event_init = core_imc_event_init;
1058 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1060 case IMC_DOMAIN_THREAD:
1061 pmu->pmu.event_init = thread_imc_event_init;
1062 pmu->pmu.sched_task = thread_imc_pmu_sched_task;
1063 pmu->pmu.add = thread_imc_event_add;
1064 pmu->pmu.del = thread_imc_event_del;
1065 pmu->pmu.start_txn = thread_imc_pmu_start_txn;
1066 pmu->pmu.cancel_txn = thread_imc_pmu_cancel_txn;
1067 pmu->pmu.commit_txn = thread_imc_pmu_commit_txn;
1076 /* init_nest_pmu_ref: Initialize the imc_pmu_ref struct for all the nodes */
1077 static int init_nest_pmu_ref(void)
1081 nest_imc_refc = kcalloc(num_possible_nodes(), sizeof(*nest_imc_refc),
1088 for_each_node(nid) {
1090 * Mutex lock to avoid races while tracking the number of
1091 * sessions using the chip's nest pmu units.
1093 mutex_init(&nest_imc_refc[i].lock);
1096 * Loop to init the "id" with the node_id. Variable "i" initialized to
1097 * 0 and will be used as index to the array. "i" will not go off the
1098 * end of the array since the "for_each_node" loops for "N_POSSIBLE"
1101 nest_imc_refc[i++].id = nid;
1105 * Loop to init the per_cpu "local_nest_imc_refc" with the proper
1106 * "nest_imc_refc" index. This makes get_nest_pmu_ref() alot simple.
1108 for_each_possible_cpu(cpu) {
1109 nid = cpu_to_node(cpu);
1110 for (i = 0; i < num_possible_nodes(); i++) {
1111 if (nest_imc_refc[i].id == nid) {
1112 per_cpu(local_nest_imc_refc, cpu) = &nest_imc_refc[i];
1120 static void cleanup_all_core_imc_memory(void)
1122 int i, nr_cores = DIV_ROUND_UP(num_present_cpus(), threads_per_core);
1123 struct imc_mem_info *ptr = core_imc_pmu->mem_info;
1124 int size = core_imc_pmu->counter_mem_size;
1126 /* mem_info will never be NULL */
1127 for (i = 0; i < nr_cores; i++) {
1129 free_pages((u64)ptr->vbase, get_order(size));
1133 kfree(core_imc_refc);
1136 static void thread_imc_ldbar_disable(void *dummy)
1139 * By Zeroing LDBAR, we disable thread-imc
1142 mtspr(SPRN_LDBAR, 0);
1145 void thread_imc_disable(void)
1147 on_each_cpu(thread_imc_ldbar_disable, NULL, 1);
1150 static void cleanup_all_thread_imc_memory(void)
1152 int i, order = get_order(thread_imc_mem_size);
1154 for_each_online_cpu(i) {
1155 if (per_cpu(thread_imc_mem, i))
1156 free_pages((u64)per_cpu(thread_imc_mem, i), order);
1162 * Common function to unregister cpu hotplug callback and
1164 * TODO: Need to handle pmu unregistering, which will be
1165 * done in followup series.
1167 static void imc_common_cpuhp_mem_free(struct imc_pmu *pmu_ptr)
1169 if (pmu_ptr->domain == IMC_DOMAIN_NEST) {
1170 mutex_lock(&nest_init_lock);
1171 if (nest_pmus == 1) {
1172 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE);
1173 kfree(nest_imc_refc);
1178 mutex_unlock(&nest_init_lock);
1181 /* Free core_imc memory */
1182 if (pmu_ptr->domain == IMC_DOMAIN_CORE) {
1183 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE);
1184 cleanup_all_core_imc_memory();
1187 /* Free thread_imc memory */
1188 if (pmu_ptr->domain == IMC_DOMAIN_THREAD) {
1189 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE);
1190 cleanup_all_thread_imc_memory();
1193 /* Only free the attr_groups which are dynamically allocated */
1194 if (pmu_ptr->attr_groups[IMC_EVENT_ATTR])
1195 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs);
1196 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]);
1198 kfree(per_nest_pmu_arr);
1204 * imc_mem_init : Function to support memory allocation for core imc.
1206 static int imc_mem_init(struct imc_pmu *pmu_ptr, struct device_node *parent,
1210 int nr_cores, cpu, res;
1212 if (of_property_read_string(parent, "name", &s))
1215 switch (pmu_ptr->domain) {
1216 case IMC_DOMAIN_NEST:
1217 /* Update the pmu name */
1218 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s_imc", "nest_", s);
1219 if (!pmu_ptr->pmu.name)
1222 /* Needed for hotplug/migration */
1223 if (!per_nest_pmu_arr) {
1224 per_nest_pmu_arr = kcalloc(get_max_nest_dev() + 1,
1225 sizeof(struct imc_pmu *),
1227 if (!per_nest_pmu_arr)
1230 per_nest_pmu_arr[pmu_index] = pmu_ptr;
1232 case IMC_DOMAIN_CORE:
1233 /* Update the pmu name */
1234 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1235 if (!pmu_ptr->pmu.name)
1238 nr_cores = DIV_ROUND_UP(num_present_cpus(), threads_per_core);
1239 pmu_ptr->mem_info = kcalloc(nr_cores, sizeof(struct imc_mem_info),
1242 if (!pmu_ptr->mem_info)
1245 core_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1251 core_imc_pmu = pmu_ptr;
1253 case IMC_DOMAIN_THREAD:
1254 /* Update the pmu name */
1255 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1256 if (!pmu_ptr->pmu.name)
1259 thread_imc_mem_size = pmu_ptr->counter_mem_size;
1260 for_each_online_cpu(cpu) {
1261 res = thread_imc_mem_alloc(cpu, pmu_ptr->counter_mem_size);
1266 thread_imc_pmu = pmu_ptr;
1276 * init_imc_pmu : Setup and register the IMC pmu device.
1278 * @parent: Device tree unit node
1279 * @pmu_ptr: memory allocated for this pmu
1280 * @pmu_idx: Count of nest pmc registered
1282 * init_imc_pmu() setup pmu cpumask and registers for a cpu hotplug callback.
1283 * Handles failure cases and accordingly frees memory.
1285 int init_imc_pmu(struct device_node *parent, struct imc_pmu *pmu_ptr, int pmu_idx)
1289 ret = imc_mem_init(pmu_ptr, parent, pmu_idx);
1293 switch (pmu_ptr->domain) {
1294 case IMC_DOMAIN_NEST:
1296 * Nest imc pmu need only one cpu per chip, we initialize the
1297 * cpumask for the first nest imc pmu and use the same for the
1298 * rest. To handle the cpuhotplug callback unregister, we track
1299 * the number of nest pmus in "nest_pmus".
1301 mutex_lock(&nest_init_lock);
1302 if (nest_pmus == 0) {
1303 ret = init_nest_pmu_ref();
1305 mutex_unlock(&nest_init_lock);
1308 /* Register for cpu hotplug notification. */
1309 ret = nest_pmu_cpumask_init();
1311 mutex_unlock(&nest_init_lock);
1316 mutex_unlock(&nest_init_lock);
1318 case IMC_DOMAIN_CORE:
1319 ret = core_imc_pmu_cpumask_init();
1321 cleanup_all_core_imc_memory();
1326 case IMC_DOMAIN_THREAD:
1327 ret = thread_imc_cpu_init();
1329 cleanup_all_thread_imc_memory();
1335 return -1; /* Unknown domain */
1338 ret = update_events_in_group(parent, pmu_ptr);
1342 ret = update_pmu_ops(pmu_ptr);
1346 ret = perf_pmu_register(&pmu_ptr->pmu, pmu_ptr->pmu.name, -1);
1350 pr_info("%s performance monitor hardware support registered\n",
1356 imc_common_cpuhp_mem_free(pmu_ptr);