1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Performance event support - powerpc architecture code
5 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/perf_event.h>
11 #include <linux/percpu.h>
12 #include <linux/hardirq.h>
13 #include <linux/uaccess.h>
16 #include <asm/machdep.h>
17 #include <asm/firmware.h>
18 #include <asm/ptrace.h>
19 #include <asm/code-patching.h>
25 #define BHRB_MAX_ENTRIES 32
26 #define BHRB_TARGET 0x0000000000000002
27 #define BHRB_PREDICTION 0x0000000000000001
28 #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL
30 struct cpu_hw_events {
37 struct perf_event *event[MAX_HWEVENTS];
38 u64 events[MAX_HWEVENTS];
39 unsigned int flags[MAX_HWEVENTS];
41 * The order of the MMCR array is:
42 * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2
43 * - 32-bit, MMCR0, MMCR1, MMCR2
45 unsigned long mmcr[4];
46 struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
47 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
48 u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
49 unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
50 unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
52 unsigned int txn_flags;
56 u64 bhrb_filter; /* BHRB HW branch filter */
57 unsigned int bhrb_users;
59 struct perf_branch_stack bhrb_stack;
60 struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES];
64 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
66 static struct power_pmu *ppmu;
69 * Normally, to ignore kernel events we set the FCS (freeze counters
70 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
71 * hypervisor bit set in the MSR, or if we are running on a processor
72 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
73 * then we need to use the FCHV bit to ignore kernel events.
75 static unsigned int freeze_events_kernel = MMCR0_FCS;
78 * 32-bit doesn't have MMCRA but does have an MMCR2,
79 * and a few other names are different.
84 #define MMCR0_PMCjCE MMCR0_PMCnCE
90 #define MMCR0_PMCC_U6 0
92 #define SPRN_MMCRA SPRN_MMCR2
93 #define MMCRA_SAMPLE_ENABLE 0
95 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
99 static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp) { }
100 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
104 static inline void perf_read_regs(struct pt_regs *regs)
108 static inline int perf_intr_is_nmi(struct pt_regs *regs)
113 static inline int siar_valid(struct pt_regs *regs)
118 static bool is_ebb_event(struct perf_event *event) { return false; }
119 static int ebb_event_check(struct perf_event *event) { return 0; }
120 static void ebb_event_add(struct perf_event *event) { }
121 static void ebb_switch_out(unsigned long mmcr0) { }
122 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
124 return cpuhw->mmcr[0];
127 static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
128 static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
129 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {}
130 static inline void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw) {}
131 static void pmao_restore_workaround(bool ebb) { }
132 #endif /* CONFIG_PPC32 */
134 bool is_sier_available(void)
136 if (ppmu->flags & PPMU_HAS_SIER)
142 static bool regs_use_siar(struct pt_regs *regs)
145 * When we take a performance monitor exception the regs are setup
146 * using perf_read_regs() which overloads some fields, in particular
147 * regs->result to tell us whether to use SIAR.
149 * However if the regs are from another exception, eg. a syscall, then
150 * they have not been setup using perf_read_regs() and so regs->result
151 * is something random.
153 return ((TRAP(regs) == 0xf00) && regs->result);
157 * Things that are specific to 64-bit implementations.
161 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
163 unsigned long mmcra = regs->dsisr;
165 if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) {
166 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
168 return 4 * (slot - 1);
175 * The user wants a data address recorded.
176 * If we're not doing instruction sampling, give them the SDAR
177 * (sampled data address). If we are doing instruction sampling, then
178 * only give them the SDAR if it corresponds to the instruction
179 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the
180 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER.
182 static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp)
184 unsigned long mmcra = regs->dsisr;
187 if (ppmu->flags & PPMU_HAS_SIER)
188 sdar_valid = regs->dar & SIER_SDAR_VALID;
190 unsigned long sdsync;
192 if (ppmu->flags & PPMU_SIAR_VALID)
193 sdsync = POWER7P_MMCRA_SDAR_VALID;
194 else if (ppmu->flags & PPMU_ALT_SIPR)
195 sdsync = POWER6_MMCRA_SDSYNC;
196 else if (ppmu->flags & PPMU_NO_SIAR)
197 sdsync = MMCRA_SAMPLE_ENABLE;
199 sdsync = MMCRA_SDSYNC;
201 sdar_valid = mmcra & sdsync;
204 if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid)
205 *addrp = mfspr(SPRN_SDAR);
207 if (is_kernel_addr(mfspr(SPRN_SDAR)) && perf_allow_kernel(&event->attr) != 0)
211 static bool regs_sihv(struct pt_regs *regs)
213 unsigned long sihv = MMCRA_SIHV;
215 if (ppmu->flags & PPMU_HAS_SIER)
216 return !!(regs->dar & SIER_SIHV);
218 if (ppmu->flags & PPMU_ALT_SIPR)
219 sihv = POWER6_MMCRA_SIHV;
221 return !!(regs->dsisr & sihv);
224 static bool regs_sipr(struct pt_regs *regs)
226 unsigned long sipr = MMCRA_SIPR;
228 if (ppmu->flags & PPMU_HAS_SIER)
229 return !!(regs->dar & SIER_SIPR);
231 if (ppmu->flags & PPMU_ALT_SIPR)
232 sipr = POWER6_MMCRA_SIPR;
234 return !!(regs->dsisr & sipr);
237 static inline u32 perf_flags_from_msr(struct pt_regs *regs)
239 if (regs->msr & MSR_PR)
240 return PERF_RECORD_MISC_USER;
241 if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV)
242 return PERF_RECORD_MISC_HYPERVISOR;
243 return PERF_RECORD_MISC_KERNEL;
246 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
248 bool use_siar = regs_use_siar(regs);
251 return perf_flags_from_msr(regs);
254 * If we don't have flags in MMCRA, rather than using
255 * the MSR, we intuit the flags from the address in
256 * SIAR which should give slightly more reliable
259 if (ppmu->flags & PPMU_NO_SIPR) {
260 unsigned long siar = mfspr(SPRN_SIAR);
261 if (is_kernel_addr(siar))
262 return PERF_RECORD_MISC_KERNEL;
263 return PERF_RECORD_MISC_USER;
266 /* PR has priority over HV, so order below is important */
268 return PERF_RECORD_MISC_USER;
270 if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV))
271 return PERF_RECORD_MISC_HYPERVISOR;
273 return PERF_RECORD_MISC_KERNEL;
277 * Overload regs->dsisr to store MMCRA so we only need to read it once
279 * Overload regs->dar to store SIER if we have it.
280 * Overload regs->result to specify whether we should use the MSR (result
281 * is zero) or the SIAR (result is non zero).
283 static inline void perf_read_regs(struct pt_regs *regs)
285 unsigned long mmcra = mfspr(SPRN_MMCRA);
286 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
291 if (ppmu->flags & PPMU_HAS_SIER)
292 regs->dar = mfspr(SPRN_SIER);
295 * If this isn't a PMU exception (eg a software event) the SIAR is
296 * not valid. Use pt_regs.
298 * If it is a marked event use the SIAR.
300 * If the PMU doesn't update the SIAR for non marked events use
303 * If the PMU has HV/PR flags then check to see if they
304 * place the exception in userspace. If so, use pt_regs. In
305 * continuous sampling mode the SIAR and the PMU exception are
306 * not synchronised, so they may be many instructions apart.
307 * This can result in confusing backtraces. We still want
308 * hypervisor samples as well as samples in the kernel with
309 * interrupts off hence the userspace check.
311 if (TRAP(regs) != 0xf00)
313 else if ((ppmu->flags & PPMU_NO_SIAR))
317 else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))
319 else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs))
324 regs->result = use_siar;
328 * If interrupts were soft-disabled when a PMU interrupt occurs, treat
331 static inline int perf_intr_is_nmi(struct pt_regs *regs)
333 return (regs->softe & IRQS_DISABLED);
337 * On processors like P7+ that have the SIAR-Valid bit, marked instructions
338 * must be sampled only if the SIAR-valid bit is set.
340 * For unmarked instructions and for processors that don't have the SIAR-Valid
341 * bit, assume that SIAR is valid.
343 static inline int siar_valid(struct pt_regs *regs)
345 unsigned long mmcra = regs->dsisr;
346 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
349 if (ppmu->flags & PPMU_HAS_SIER)
350 return regs->dar & SIER_SIAR_VALID;
352 if (ppmu->flags & PPMU_SIAR_VALID)
353 return mmcra & POWER7P_MMCRA_SIAR_VALID;
360 /* Reset all possible BHRB entries */
361 static void power_pmu_bhrb_reset(void)
363 asm volatile(PPC_CLRBHRB);
366 static void power_pmu_bhrb_enable(struct perf_event *event)
368 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
373 /* Clear BHRB if we changed task context to avoid data leaks */
374 if (event->ctx->task && cpuhw->bhrb_context != event->ctx) {
375 power_pmu_bhrb_reset();
376 cpuhw->bhrb_context = event->ctx;
379 perf_sched_cb_inc(event->ctx->pmu);
382 static void power_pmu_bhrb_disable(struct perf_event *event)
384 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
389 WARN_ON_ONCE(!cpuhw->bhrb_users);
391 perf_sched_cb_dec(event->ctx->pmu);
393 if (!cpuhw->disabled && !cpuhw->bhrb_users) {
394 /* BHRB cannot be turned off when other
395 * events are active on the PMU.
398 /* avoid stale pointer */
399 cpuhw->bhrb_context = NULL;
403 /* Called from ctxsw to prevent one process's branch entries to
404 * mingle with the other process's entries during context switch.
406 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
412 power_pmu_bhrb_reset();
414 /* Calculate the to address for a branch */
415 static __u64 power_pmu_bhrb_to(u64 addr)
420 if (is_kernel_addr(addr)) {
421 if (probe_kernel_read(&instr, (void *)addr, sizeof(instr)))
424 return branch_target(&instr);
427 /* Userspace: need copy instruction here then translate it */
428 if (probe_user_read(&instr, (unsigned int __user *)addr, sizeof(instr)))
431 target = branch_target(&instr);
432 if ((!target) || (instr & BRANCH_ABSOLUTE))
435 /* Translate relative branch target from kernel to user address */
436 return target - (unsigned long)&instr + addr;
439 /* Processing BHRB entries */
440 static void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw)
444 int r_index, u_index, pred;
448 while (r_index < ppmu->bhrb_nr) {
449 /* Assembly read function */
450 val = read_bhrb(r_index++);
452 /* Terminal marker: End of valid BHRB entries */
455 addr = val & BHRB_EA;
456 pred = val & BHRB_PREDICTION;
463 * BHRB rolling buffer could very much contain the kernel
464 * addresses at this point. Check the privileges before
465 * exporting it to userspace (avoid exposure of regions
466 * where we could have speculative execution)
468 if (is_kernel_addr(addr) && perf_allow_kernel(&event->attr) != 0)
471 /* Branches are read most recent first (ie. mfbhrb 0 is
472 * the most recent branch).
473 * There are two types of valid entries:
474 * 1) a target entry which is the to address of a
475 * computed goto like a blr,bctr,btar. The next
476 * entry read from the bhrb will be branch
477 * corresponding to this target (ie. the actual
478 * blr/bctr/btar instruction).
479 * 2) a from address which is an actual branch. If a
480 * target entry proceeds this, then this is the
481 * matching branch for that target. If this is not
482 * following a target entry, then this is a branch
483 * where the target is given as an immediate field
484 * in the instruction (ie. an i or b form branch).
485 * In this case we need to read the instruction from
486 * memory to determine the target/to address.
489 if (val & BHRB_TARGET) {
490 /* Target branches use two entries
491 * (ie. computed gotos/XL form)
493 cpuhw->bhrb_entries[u_index].to = addr;
494 cpuhw->bhrb_entries[u_index].mispred = pred;
495 cpuhw->bhrb_entries[u_index].predicted = ~pred;
497 /* Get from address in next entry */
498 val = read_bhrb(r_index++);
499 addr = val & BHRB_EA;
500 if (val & BHRB_TARGET) {
501 /* Shouldn't have two targets in a
502 row.. Reset index and try again */
506 cpuhw->bhrb_entries[u_index].from = addr;
508 /* Branches to immediate field
510 cpuhw->bhrb_entries[u_index].from = addr;
511 cpuhw->bhrb_entries[u_index].to =
512 power_pmu_bhrb_to(addr);
513 cpuhw->bhrb_entries[u_index].mispred = pred;
514 cpuhw->bhrb_entries[u_index].predicted = ~pred;
520 cpuhw->bhrb_stack.nr = u_index;
521 cpuhw->bhrb_stack.hw_idx = -1ULL;
525 static bool is_ebb_event(struct perf_event *event)
528 * This could be a per-PMU callback, but we'd rather avoid the cost. We
529 * check that the PMU supports EBB, meaning those that don't can still
530 * use bit 63 of the event code for something else if they wish.
532 return (ppmu->flags & PPMU_ARCH_207S) &&
533 ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1);
536 static int ebb_event_check(struct perf_event *event)
538 struct perf_event *leader = event->group_leader;
540 /* Event and group leader must agree on EBB */
541 if (is_ebb_event(leader) != is_ebb_event(event))
544 if (is_ebb_event(event)) {
545 if (!(event->attach_state & PERF_ATTACH_TASK))
548 if (!leader->attr.pinned || !leader->attr.exclusive)
551 if (event->attr.freq ||
552 event->attr.inherit ||
553 event->attr.sample_type ||
554 event->attr.sample_period ||
555 event->attr.enable_on_exec)
562 static void ebb_event_add(struct perf_event *event)
564 if (!is_ebb_event(event) || current->thread.used_ebb)
568 * IFF this is the first time we've added an EBB event, set
569 * PMXE in the user MMCR0 so we can detect when it's cleared by
570 * userspace. We need this so that we can context switch while
571 * userspace is in the EBB handler (where PMXE is 0).
573 current->thread.used_ebb = 1;
574 current->thread.mmcr0 |= MMCR0_PMXE;
577 static void ebb_switch_out(unsigned long mmcr0)
579 if (!(mmcr0 & MMCR0_EBE))
582 current->thread.siar = mfspr(SPRN_SIAR);
583 current->thread.sier = mfspr(SPRN_SIER);
584 current->thread.sdar = mfspr(SPRN_SDAR);
585 current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;
586 current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
589 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
591 unsigned long mmcr0 = cpuhw->mmcr[0];
596 /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */
597 mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6;
600 * Add any bits from the user MMCR0, FC or PMAO. This is compatible
601 * with pmao_restore_workaround() because we may add PMAO but we never
604 mmcr0 |= current->thread.mmcr0;
607 * Be careful not to set PMXE if userspace had it cleared. This is also
608 * compatible with pmao_restore_workaround() because it has already
609 * cleared PMXE and we leave PMAO alone.
611 if (!(current->thread.mmcr0 & MMCR0_PMXE))
612 mmcr0 &= ~MMCR0_PMXE;
614 mtspr(SPRN_SIAR, current->thread.siar);
615 mtspr(SPRN_SIER, current->thread.sier);
616 mtspr(SPRN_SDAR, current->thread.sdar);
619 * Merge the kernel & user values of MMCR2. The semantics we implement
620 * are that the user MMCR2 can set bits, ie. cause counters to freeze,
621 * but not clear bits. If a task wants to be able to clear bits, ie.
622 * unfreeze counters, it should not set exclude_xxx in its events and
623 * instead manage the MMCR2 entirely by itself.
625 mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2);
630 static void pmao_restore_workaround(bool ebb)
634 if (!cpu_has_feature(CPU_FTR_PMAO_BUG))
638 * On POWER8E there is a hardware defect which affects the PMU context
639 * switch logic, ie. power_pmu_disable/enable().
641 * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0
642 * by the hardware. Sometime later the actual PMU exception is
645 * If we context switch, or simply disable/enable, the PMU prior to the
646 * exception arriving, the exception will be lost when we clear PMAO.
648 * When we reenable the PMU, we will write the saved MMCR0 with PMAO
649 * set, and this _should_ generate an exception. However because of the
650 * defect no exception is generated when we write PMAO, and we get
651 * stuck with no counters counting but no exception delivered.
653 * The workaround is to detect this case and tweak the hardware to
654 * create another pending PMU exception.
656 * We do that by setting up PMC6 (cycles) for an imminent overflow and
657 * enabling the PMU. That causes a new exception to be generated in the
658 * chip, but we don't take it yet because we have interrupts hard
659 * disabled. We then write back the PMU state as we want it to be seen
660 * by the exception handler. When we reenable interrupts the exception
661 * handler will be called and see the correct state.
663 * The logic is the same for EBB, except that the exception is gated by
664 * us having interrupts hard disabled as well as the fact that we are
665 * not in userspace. The exception is finally delivered when we return
669 /* Only if PMAO is set and PMAO_SYNC is clear */
670 if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO)
673 /* If we're doing EBB, only if BESCR[GE] is set */
674 if (ebb && !(current->thread.bescr & BESCR_GE))
678 * We are already soft-disabled in power_pmu_enable(). We need to hard
679 * disable to actually prevent the PMU exception from firing.
684 * This is a bit gross, but we know we're on POWER8E and have 6 PMCs.
685 * Using read/write_pmc() in a for loop adds 12 function calls and
686 * almost doubles our code size.
688 pmcs[0] = mfspr(SPRN_PMC1);
689 pmcs[1] = mfspr(SPRN_PMC2);
690 pmcs[2] = mfspr(SPRN_PMC3);
691 pmcs[3] = mfspr(SPRN_PMC4);
692 pmcs[4] = mfspr(SPRN_PMC5);
693 pmcs[5] = mfspr(SPRN_PMC6);
695 /* Ensure all freeze bits are unset */
696 mtspr(SPRN_MMCR2, 0);
698 /* Set up PMC6 to overflow in one cycle */
699 mtspr(SPRN_PMC6, 0x7FFFFFFE);
701 /* Enable exceptions and unfreeze PMC6 */
702 mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO);
704 /* Now we need to refreeze and restore the PMCs */
705 mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO);
707 mtspr(SPRN_PMC1, pmcs[0]);
708 mtspr(SPRN_PMC2, pmcs[1]);
709 mtspr(SPRN_PMC3, pmcs[2]);
710 mtspr(SPRN_PMC4, pmcs[3]);
711 mtspr(SPRN_PMC5, pmcs[4]);
712 mtspr(SPRN_PMC6, pmcs[5]);
715 #endif /* CONFIG_PPC64 */
717 static void perf_event_interrupt(struct pt_regs *regs);
720 * Read one performance monitor counter (PMC).
722 static unsigned long read_pmc(int idx)
728 val = mfspr(SPRN_PMC1);
731 val = mfspr(SPRN_PMC2);
734 val = mfspr(SPRN_PMC3);
737 val = mfspr(SPRN_PMC4);
740 val = mfspr(SPRN_PMC5);
743 val = mfspr(SPRN_PMC6);
747 val = mfspr(SPRN_PMC7);
750 val = mfspr(SPRN_PMC8);
752 #endif /* CONFIG_PPC64 */
754 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
763 static void write_pmc(int idx, unsigned long val)
767 mtspr(SPRN_PMC1, val);
770 mtspr(SPRN_PMC2, val);
773 mtspr(SPRN_PMC3, val);
776 mtspr(SPRN_PMC4, val);
779 mtspr(SPRN_PMC5, val);
782 mtspr(SPRN_PMC6, val);
786 mtspr(SPRN_PMC7, val);
789 mtspr(SPRN_PMC8, val);
791 #endif /* CONFIG_PPC64 */
793 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
797 /* Called from sysrq_handle_showregs() */
798 void perf_event_print_debug(void)
800 unsigned long sdar, sier, flags;
801 u32 pmcs[MAX_HWEVENTS];
805 pr_info("Performance monitor hardware not registered.\n");
809 if (!ppmu->n_counter)
812 local_irq_save(flags);
814 pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d",
815 smp_processor_id(), ppmu->name, ppmu->n_counter);
817 for (i = 0; i < ppmu->n_counter; i++)
818 pmcs[i] = read_pmc(i + 1);
820 for (; i < MAX_HWEVENTS; i++)
821 pmcs[i] = 0xdeadbeef;
823 pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n",
824 pmcs[0], pmcs[1], pmcs[2], pmcs[3]);
826 if (ppmu->n_counter > 4)
827 pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n",
828 pmcs[4], pmcs[5], pmcs[6], pmcs[7]);
830 pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n",
831 mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA));
835 sdar = mfspr(SPRN_SDAR);
837 if (ppmu->flags & PPMU_HAS_SIER)
838 sier = mfspr(SPRN_SIER);
840 if (ppmu->flags & PPMU_ARCH_207S) {
841 pr_info("MMCR2: %016lx EBBHR: %016lx\n",
842 mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR));
843 pr_info("EBBRR: %016lx BESCR: %016lx\n",
844 mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR));
847 pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n",
848 mfspr(SPRN_SIAR), sdar, sier);
850 local_irq_restore(flags);
854 * Check if a set of events can all go on the PMU at once.
855 * If they can't, this will look at alternative codes for the events
856 * and see if any combination of alternative codes is feasible.
857 * The feasible set is returned in event_id[].
859 static int power_check_constraints(struct cpu_hw_events *cpuhw,
860 u64 event_id[], unsigned int cflags[],
863 unsigned long mask, value, nv;
864 unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS];
865 int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS];
867 unsigned long addf = ppmu->add_fields;
868 unsigned long tadd = ppmu->test_adder;
869 unsigned long grp_mask = ppmu->group_constraint_mask;
870 unsigned long grp_val = ppmu->group_constraint_val;
872 if (n_ev > ppmu->n_counter)
875 /* First see if the events will go on as-is */
876 for (i = 0; i < n_ev; ++i) {
877 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
878 && !ppmu->limited_pmc_event(event_id[i])) {
879 ppmu->get_alternatives(event_id[i], cflags[i],
880 cpuhw->alternatives[i]);
881 event_id[i] = cpuhw->alternatives[i][0];
883 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
884 &cpuhw->avalues[i][0]))
888 for (i = 0; i < n_ev; ++i) {
889 nv = (value | cpuhw->avalues[i][0]) +
890 (value & cpuhw->avalues[i][0] & addf);
892 if (((((nv + tadd) ^ value) & mask) & (~grp_mask)) != 0)
895 if (((((nv + tadd) ^ cpuhw->avalues[i][0]) & cpuhw->amasks[i][0])
900 mask |= cpuhw->amasks[i][0];
903 if ((value & mask & grp_mask) != (mask & grp_val))
906 return 0; /* all OK */
909 /* doesn't work, gather alternatives... */
910 if (!ppmu->get_alternatives)
912 for (i = 0; i < n_ev; ++i) {
914 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i],
915 cpuhw->alternatives[i]);
916 for (j = 1; j < n_alt[i]; ++j)
917 ppmu->get_constraint(cpuhw->alternatives[i][j],
918 &cpuhw->amasks[i][j],
919 &cpuhw->avalues[i][j]);
922 /* enumerate all possibilities and see if any will work */
925 value = mask = nv = 0;
928 /* we're backtracking, restore context */
934 * See if any alternative k for event_id i,
935 * where k > j, will satisfy the constraints.
937 while (++j < n_alt[i]) {
938 nv = (value | cpuhw->avalues[i][j]) +
939 (value & cpuhw->avalues[i][j] & addf);
940 if ((((nv + tadd) ^ value) & mask) == 0 &&
941 (((nv + tadd) ^ cpuhw->avalues[i][j])
942 & cpuhw->amasks[i][j]) == 0)
947 * No feasible alternative, backtrack
948 * to event_id i-1 and continue enumerating its
949 * alternatives from where we got up to.
955 * Found a feasible alternative for event_id i,
956 * remember where we got up to with this event_id,
957 * go on to the next event_id, and start with
958 * the first alternative for it.
964 mask |= cpuhw->amasks[i][j];
970 /* OK, we have a feasible combination, tell the caller the solution */
971 for (i = 0; i < n_ev; ++i)
972 event_id[i] = cpuhw->alternatives[i][choice[i]];
977 * Check if newly-added events have consistent settings for
978 * exclude_{user,kernel,hv} with each other and any previously
981 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
982 int n_prev, int n_new)
984 int eu = 0, ek = 0, eh = 0;
986 struct perf_event *event;
989 * If the PMU we're on supports per event exclude settings then we
990 * don't need to do any of this logic. NB. This assumes no PMU has both
991 * per event exclude and limited PMCs.
993 if (ppmu->flags & PPMU_ARCH_207S)
1001 for (i = 0; i < n; ++i) {
1002 if (cflags[i] & PPMU_LIMITED_PMC_OK) {
1003 cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
1008 eu = event->attr.exclude_user;
1009 ek = event->attr.exclude_kernel;
1010 eh = event->attr.exclude_hv;
1012 } else if (event->attr.exclude_user != eu ||
1013 event->attr.exclude_kernel != ek ||
1014 event->attr.exclude_hv != eh) {
1020 for (i = 0; i < n; ++i)
1021 if (cflags[i] & PPMU_LIMITED_PMC_OK)
1022 cflags[i] |= PPMU_LIMITED_PMC_REQD;
1027 static u64 check_and_compute_delta(u64 prev, u64 val)
1029 u64 delta = (val - prev) & 0xfffffffful;
1032 * POWER7 can roll back counter values, if the new value is smaller
1033 * than the previous value it will cause the delta and the counter to
1034 * have bogus values unless we rolled a counter over. If a coutner is
1035 * rolled back, it will be smaller, but within 256, which is the maximum
1036 * number of events to rollback at once. If we detect a rollback
1037 * return 0. This can lead to a small lack of precision in the
1040 if (prev > val && (prev - val) < 256)
1046 static void power_pmu_read(struct perf_event *event)
1048 s64 val, delta, prev;
1050 if (event->hw.state & PERF_HES_STOPPED)
1056 if (is_ebb_event(event)) {
1057 val = read_pmc(event->hw.idx);
1058 local64_set(&event->hw.prev_count, val);
1063 * Performance monitor interrupts come even when interrupts
1064 * are soft-disabled, as long as interrupts are hard-enabled.
1065 * Therefore we treat them like NMIs.
1068 prev = local64_read(&event->hw.prev_count);
1070 val = read_pmc(event->hw.idx);
1071 delta = check_and_compute_delta(prev, val);
1074 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
1076 local64_add(delta, &event->count);
1079 * A number of places program the PMC with (0x80000000 - period_left).
1080 * We never want period_left to be less than 1 because we will program
1081 * the PMC with a value >= 0x800000000 and an edge detected PMC will
1082 * roll around to 0 before taking an exception. We have seen this
1085 * To fix this, clamp the minimum value of period_left to 1.
1088 prev = local64_read(&event->hw.period_left);
1092 } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev);
1096 * On some machines, PMC5 and PMC6 can't be written, don't respect
1097 * the freeze conditions, and don't generate interrupts. This tells
1098 * us if `event' is using such a PMC.
1100 static int is_limited_pmc(int pmcnum)
1102 return (ppmu->flags & PPMU_LIMITED_PMC5_6)
1103 && (pmcnum == 5 || pmcnum == 6);
1106 static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
1107 unsigned long pmc5, unsigned long pmc6)
1109 struct perf_event *event;
1110 u64 val, prev, delta;
1113 for (i = 0; i < cpuhw->n_limited; ++i) {
1114 event = cpuhw->limited_counter[i];
1117 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1118 prev = local64_read(&event->hw.prev_count);
1120 delta = check_and_compute_delta(prev, val);
1122 local64_add(delta, &event->count);
1126 static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
1127 unsigned long pmc5, unsigned long pmc6)
1129 struct perf_event *event;
1133 for (i = 0; i < cpuhw->n_limited; ++i) {
1134 event = cpuhw->limited_counter[i];
1135 event->hw.idx = cpuhw->limited_hwidx[i];
1136 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1137 prev = local64_read(&event->hw.prev_count);
1138 if (check_and_compute_delta(prev, val))
1139 local64_set(&event->hw.prev_count, val);
1140 perf_event_update_userpage(event);
1145 * Since limited events don't respect the freeze conditions, we
1146 * have to read them immediately after freezing or unfreezing the
1147 * other events. We try to keep the values from the limited
1148 * events as consistent as possible by keeping the delay (in
1149 * cycles and instructions) between freezing/unfreezing and reading
1150 * the limited events as small and consistent as possible.
1151 * Therefore, if any limited events are in use, we read them
1152 * both, and always in the same order, to minimize variability,
1153 * and do it inside the same asm that writes MMCR0.
1155 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
1157 unsigned long pmc5, pmc6;
1159 if (!cpuhw->n_limited) {
1160 mtspr(SPRN_MMCR0, mmcr0);
1165 * Write MMCR0, then read PMC5 and PMC6 immediately.
1166 * To ensure we don't get a performance monitor interrupt
1167 * between writing MMCR0 and freezing/thawing the limited
1168 * events, we first write MMCR0 with the event overflow
1169 * interrupt enable bits turned off.
1171 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
1172 : "=&r" (pmc5), "=&r" (pmc6)
1173 : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
1175 "i" (SPRN_PMC5), "i" (SPRN_PMC6));
1177 if (mmcr0 & MMCR0_FC)
1178 freeze_limited_counters(cpuhw, pmc5, pmc6);
1180 thaw_limited_counters(cpuhw, pmc5, pmc6);
1183 * Write the full MMCR0 including the event overflow interrupt
1184 * enable bits, if necessary.
1186 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
1187 mtspr(SPRN_MMCR0, mmcr0);
1191 * Disable all events to prevent PMU interrupts and to allow
1192 * events to be added or removed.
1194 static void power_pmu_disable(struct pmu *pmu)
1196 struct cpu_hw_events *cpuhw;
1197 unsigned long flags, mmcr0, val;
1201 local_irq_save(flags);
1202 cpuhw = this_cpu_ptr(&cpu_hw_events);
1204 if (!cpuhw->disabled) {
1206 * Check if we ever enabled the PMU on this cpu.
1208 if (!cpuhw->pmcs_enabled) {
1210 cpuhw->pmcs_enabled = 1;
1214 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56
1216 val = mmcr0 = mfspr(SPRN_MMCR0);
1218 val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
1222 * The barrier is to make sure the mtspr has been
1223 * executed and the PMU has frozen the events etc.
1226 write_mmcr0(cpuhw, val);
1231 * Disable instruction sampling if it was enabled
1233 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1235 cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1240 cpuhw->disabled = 1;
1243 ebb_switch_out(mmcr0);
1247 * These are readable by userspace, may contain kernel
1248 * addresses and are not switched by context switch, so clear
1249 * them now to avoid leaking anything to userspace in general
1250 * including to another process.
1252 if (ppmu->flags & PPMU_ARCH_207S) {
1253 mtspr(SPRN_SDAR, 0);
1254 mtspr(SPRN_SIAR, 0);
1259 local_irq_restore(flags);
1263 * Re-enable all events if disable == 0.
1264 * If we were previously disabled and events were added, then
1265 * put the new config on the PMU.
1267 static void power_pmu_enable(struct pmu *pmu)
1269 struct perf_event *event;
1270 struct cpu_hw_events *cpuhw;
1271 unsigned long flags;
1273 unsigned long val, mmcr0;
1275 unsigned int hwc_index[MAX_HWEVENTS];
1282 local_irq_save(flags);
1284 cpuhw = this_cpu_ptr(&cpu_hw_events);
1285 if (!cpuhw->disabled)
1288 if (cpuhw->n_events == 0) {
1289 ppc_set_pmu_inuse(0);
1293 cpuhw->disabled = 0;
1296 * EBB requires an exclusive group and all events must have the EBB
1297 * flag set, or not set, so we can just check a single event. Also we
1298 * know we have at least one event.
1300 ebb = is_ebb_event(cpuhw->event[0]);
1303 * If we didn't change anything, or only removed events,
1304 * no need to recalculate MMCR* settings and reset the PMCs.
1305 * Just reenable the PMU with the current MMCR* settings
1306 * (possibly updated for removal of events).
1308 if (!cpuhw->n_added) {
1309 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1310 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1315 * Clear all MMCR settings and recompute them for the new set of events.
1317 memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr));
1319 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
1320 cpuhw->mmcr, cpuhw->event)) {
1321 /* shouldn't ever get here */
1322 printk(KERN_ERR "oops compute_mmcr failed\n");
1326 if (!(ppmu->flags & PPMU_ARCH_207S)) {
1328 * Add in MMCR0 freeze bits corresponding to the attr.exclude_*
1329 * bits for the first event. We have already checked that all
1330 * events have the same value for these bits as the first event.
1332 event = cpuhw->event[0];
1333 if (event->attr.exclude_user)
1334 cpuhw->mmcr[0] |= MMCR0_FCP;
1335 if (event->attr.exclude_kernel)
1336 cpuhw->mmcr[0] |= freeze_events_kernel;
1337 if (event->attr.exclude_hv)
1338 cpuhw->mmcr[0] |= MMCR0_FCHV;
1342 * Write the new configuration to MMCR* with the freeze
1343 * bit set and set the hardware events to their initial values.
1344 * Then unfreeze the events.
1346 ppc_set_pmu_inuse(1);
1347 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1348 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1349 mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
1351 if (ppmu->flags & PPMU_ARCH_207S)
1352 mtspr(SPRN_MMCR2, cpuhw->mmcr[3]);
1355 * Read off any pre-existing events that need to move
1358 for (i = 0; i < cpuhw->n_events; ++i) {
1359 event = cpuhw->event[i];
1360 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
1361 power_pmu_read(event);
1362 write_pmc(event->hw.idx, 0);
1368 * Initialize the PMCs for all the new and moved events.
1370 cpuhw->n_limited = n_lim = 0;
1371 for (i = 0; i < cpuhw->n_events; ++i) {
1372 event = cpuhw->event[i];
1375 idx = hwc_index[i] + 1;
1376 if (is_limited_pmc(idx)) {
1377 cpuhw->limited_counter[n_lim] = event;
1378 cpuhw->limited_hwidx[n_lim] = idx;
1384 val = local64_read(&event->hw.prev_count);
1387 if (event->hw.sample_period) {
1388 left = local64_read(&event->hw.period_left);
1389 if (left < 0x80000000L)
1390 val = 0x80000000L - left;
1392 local64_set(&event->hw.prev_count, val);
1395 event->hw.idx = idx;
1396 if (event->hw.state & PERF_HES_STOPPED)
1398 write_pmc(idx, val);
1400 perf_event_update_userpage(event);
1402 cpuhw->n_limited = n_lim;
1403 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
1406 pmao_restore_workaround(ebb);
1408 mmcr0 = ebb_switch_in(ebb, cpuhw);
1411 if (cpuhw->bhrb_users)
1412 ppmu->config_bhrb(cpuhw->bhrb_filter);
1414 write_mmcr0(cpuhw, mmcr0);
1417 * Enable instruction sampling if necessary
1419 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1421 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
1426 local_irq_restore(flags);
1429 static int collect_events(struct perf_event *group, int max_count,
1430 struct perf_event *ctrs[], u64 *events,
1431 unsigned int *flags)
1434 struct perf_event *event;
1436 if (group->pmu->task_ctx_nr == perf_hw_context) {
1440 flags[n] = group->hw.event_base;
1441 events[n++] = group->hw.config;
1443 for_each_sibling_event(event, group) {
1444 if (event->pmu->task_ctx_nr == perf_hw_context &&
1445 event->state != PERF_EVENT_STATE_OFF) {
1449 flags[n] = event->hw.event_base;
1450 events[n++] = event->hw.config;
1457 * Add an event to the PMU.
1458 * If all events are not already frozen, then we disable and
1459 * re-enable the PMU in order to get hw_perf_enable to do the
1460 * actual work of reconfiguring the PMU.
1462 static int power_pmu_add(struct perf_event *event, int ef_flags)
1464 struct cpu_hw_events *cpuhw;
1465 unsigned long flags;
1469 local_irq_save(flags);
1470 perf_pmu_disable(event->pmu);
1473 * Add the event to the list (if there is room)
1474 * and check whether the total set is still feasible.
1476 cpuhw = this_cpu_ptr(&cpu_hw_events);
1477 n0 = cpuhw->n_events;
1478 if (n0 >= ppmu->n_counter)
1480 cpuhw->event[n0] = event;
1481 cpuhw->events[n0] = event->hw.config;
1482 cpuhw->flags[n0] = event->hw.event_base;
1485 * This event may have been disabled/stopped in record_and_restart()
1486 * because we exceeded the ->event_limit. If re-starting the event,
1487 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user
1488 * notification is re-enabled.
1490 if (!(ef_flags & PERF_EF_START))
1491 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
1493 event->hw.state = 0;
1496 * If group events scheduling transaction was started,
1497 * skip the schedulability test here, it will be performed
1498 * at commit time(->commit_txn) as a whole
1500 if (cpuhw->txn_flags & PERF_PMU_TXN_ADD)
1503 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
1505 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
1507 event->hw.config = cpuhw->events[n0];
1510 ebb_event_add(event);
1517 if (has_branch_stack(event)) {
1518 power_pmu_bhrb_enable(event);
1519 cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1520 event->attr.branch_sample_type);
1523 perf_pmu_enable(event->pmu);
1524 local_irq_restore(flags);
1529 * Remove an event from the PMU.
1531 static void power_pmu_del(struct perf_event *event, int ef_flags)
1533 struct cpu_hw_events *cpuhw;
1535 unsigned long flags;
1537 local_irq_save(flags);
1538 perf_pmu_disable(event->pmu);
1540 power_pmu_read(event);
1542 cpuhw = this_cpu_ptr(&cpu_hw_events);
1543 for (i = 0; i < cpuhw->n_events; ++i) {
1544 if (event == cpuhw->event[i]) {
1545 while (++i < cpuhw->n_events) {
1546 cpuhw->event[i-1] = cpuhw->event[i];
1547 cpuhw->events[i-1] = cpuhw->events[i];
1548 cpuhw->flags[i-1] = cpuhw->flags[i];
1551 ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr);
1552 if (event->hw.idx) {
1553 write_pmc(event->hw.idx, 0);
1556 perf_event_update_userpage(event);
1560 for (i = 0; i < cpuhw->n_limited; ++i)
1561 if (event == cpuhw->limited_counter[i])
1563 if (i < cpuhw->n_limited) {
1564 while (++i < cpuhw->n_limited) {
1565 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
1566 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
1570 if (cpuhw->n_events == 0) {
1571 /* disable exceptions if no events are running */
1572 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
1575 if (has_branch_stack(event))
1576 power_pmu_bhrb_disable(event);
1578 perf_pmu_enable(event->pmu);
1579 local_irq_restore(flags);
1583 * POWER-PMU does not support disabling individual counters, hence
1584 * program their cycle counter to their max value and ignore the interrupts.
1587 static void power_pmu_start(struct perf_event *event, int ef_flags)
1589 unsigned long flags;
1593 if (!event->hw.idx || !event->hw.sample_period)
1596 if (!(event->hw.state & PERF_HES_STOPPED))
1599 if (ef_flags & PERF_EF_RELOAD)
1600 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1602 local_irq_save(flags);
1603 perf_pmu_disable(event->pmu);
1605 event->hw.state = 0;
1606 left = local64_read(&event->hw.period_left);
1609 if (left < 0x80000000L)
1610 val = 0x80000000L - left;
1612 write_pmc(event->hw.idx, val);
1614 perf_event_update_userpage(event);
1615 perf_pmu_enable(event->pmu);
1616 local_irq_restore(flags);
1619 static void power_pmu_stop(struct perf_event *event, int ef_flags)
1621 unsigned long flags;
1623 if (!event->hw.idx || !event->hw.sample_period)
1626 if (event->hw.state & PERF_HES_STOPPED)
1629 local_irq_save(flags);
1630 perf_pmu_disable(event->pmu);
1632 power_pmu_read(event);
1633 event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
1634 write_pmc(event->hw.idx, 0);
1636 perf_event_update_userpage(event);
1637 perf_pmu_enable(event->pmu);
1638 local_irq_restore(flags);
1642 * Start group events scheduling transaction
1643 * Set the flag to make pmu::enable() not perform the
1644 * schedulability test, it will be performed at commit time
1646 * We only support PERF_PMU_TXN_ADD transactions. Save the
1647 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1650 static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1652 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1654 WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */
1656 cpuhw->txn_flags = txn_flags;
1657 if (txn_flags & ~PERF_PMU_TXN_ADD)
1660 perf_pmu_disable(pmu);
1661 cpuhw->n_txn_start = cpuhw->n_events;
1665 * Stop group events scheduling transaction
1666 * Clear the flag and pmu::enable() will perform the
1667 * schedulability test.
1669 static void power_pmu_cancel_txn(struct pmu *pmu)
1671 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1672 unsigned int txn_flags;
1674 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1676 txn_flags = cpuhw->txn_flags;
1677 cpuhw->txn_flags = 0;
1678 if (txn_flags & ~PERF_PMU_TXN_ADD)
1681 perf_pmu_enable(pmu);
1685 * Commit group events scheduling transaction
1686 * Perform the group schedulability test as a whole
1687 * Return 0 if success
1689 static int power_pmu_commit_txn(struct pmu *pmu)
1691 struct cpu_hw_events *cpuhw;
1697 cpuhw = this_cpu_ptr(&cpu_hw_events);
1698 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1700 if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) {
1701 cpuhw->txn_flags = 0;
1705 n = cpuhw->n_events;
1706 if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
1708 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n);
1712 for (i = cpuhw->n_txn_start; i < n; ++i)
1713 cpuhw->event[i]->hw.config = cpuhw->events[i];
1715 cpuhw->txn_flags = 0;
1716 perf_pmu_enable(pmu);
1721 * Return 1 if we might be able to put event on a limited PMC,
1723 * An event can only go on a limited PMC if it counts something
1724 * that a limited PMC can count, doesn't require interrupts, and
1725 * doesn't exclude any processor mode.
1727 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev,
1731 u64 alt[MAX_EVENT_ALTERNATIVES];
1733 if (event->attr.exclude_user
1734 || event->attr.exclude_kernel
1735 || event->attr.exclude_hv
1736 || event->attr.sample_period)
1739 if (ppmu->limited_pmc_event(ev))
1743 * The requested event_id isn't on a limited PMC already;
1744 * see if any alternative code goes on a limited PMC.
1746 if (!ppmu->get_alternatives)
1749 flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
1750 n = ppmu->get_alternatives(ev, flags, alt);
1756 * Find an alternative event_id that goes on a normal PMC, if possible,
1757 * and return the event_id code, or 0 if there is no such alternative.
1758 * (Note: event_id code 0 is "don't count" on all machines.)
1760 static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
1762 u64 alt[MAX_EVENT_ALTERNATIVES];
1765 flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
1766 n = ppmu->get_alternatives(ev, flags, alt);
1772 /* Number of perf_events counting hardware events */
1773 static atomic_t num_events;
1774 /* Used to avoid races in calling reserve/release_pmc_hardware */
1775 static DEFINE_MUTEX(pmc_reserve_mutex);
1778 * Release the PMU if this is the last perf_event.
1780 static void hw_perf_event_destroy(struct perf_event *event)
1782 if (!atomic_add_unless(&num_events, -1, 1)) {
1783 mutex_lock(&pmc_reserve_mutex);
1784 if (atomic_dec_return(&num_events) == 0)
1785 release_pmc_hardware();
1786 mutex_unlock(&pmc_reserve_mutex);
1791 * Translate a generic cache event_id config to a raw event_id code.
1793 static int hw_perf_cache_event(u64 config, u64 *eventp)
1795 unsigned long type, op, result;
1798 if (!ppmu->cache_events)
1802 type = config & 0xff;
1803 op = (config >> 8) & 0xff;
1804 result = (config >> 16) & 0xff;
1806 if (type >= PERF_COUNT_HW_CACHE_MAX ||
1807 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
1808 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1811 ev = (*ppmu->cache_events)[type][op][result];
1820 static bool is_event_blacklisted(u64 ev)
1824 for (i=0; i < ppmu->n_blacklist_ev; i++) {
1825 if (ppmu->blacklist_ev[i] == ev)
1832 static int power_pmu_event_init(struct perf_event *event)
1835 unsigned long flags;
1836 struct perf_event *ctrs[MAX_HWEVENTS];
1837 u64 events[MAX_HWEVENTS];
1838 unsigned int cflags[MAX_HWEVENTS];
1841 struct cpu_hw_events *cpuhw;
1847 if (has_branch_stack(event)) {
1848 /* PMU has BHRB enabled */
1849 if (!(ppmu->flags & PPMU_ARCH_207S))
1853 switch (event->attr.type) {
1854 case PERF_TYPE_HARDWARE:
1855 ev = event->attr.config;
1856 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
1859 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1861 ev = ppmu->generic_events[ev];
1863 case PERF_TYPE_HW_CACHE:
1864 err = hw_perf_cache_event(event->attr.config, &ev);
1868 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1872 ev = event->attr.config;
1874 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1881 event->hw.config_base = ev;
1885 * If we are not running on a hypervisor, force the
1886 * exclude_hv bit to 0 so that we don't care what
1887 * the user set it to.
1889 if (!firmware_has_feature(FW_FEATURE_LPAR))
1890 event->attr.exclude_hv = 0;
1893 * If this is a per-task event, then we can use
1894 * PM_RUN_* events interchangeably with their non RUN_*
1895 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1896 * XXX we should check if the task is an idle task.
1899 if (event->attach_state & PERF_ATTACH_TASK)
1900 flags |= PPMU_ONLY_COUNT_RUN;
1903 * If this machine has limited events, check whether this
1904 * event_id could go on a limited event.
1906 if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
1907 if (can_go_on_limited_pmc(event, ev, flags)) {
1908 flags |= PPMU_LIMITED_PMC_OK;
1909 } else if (ppmu->limited_pmc_event(ev)) {
1911 * The requested event_id is on a limited PMC,
1912 * but we can't use a limited PMC; see if any
1913 * alternative goes on a normal PMC.
1915 ev = normal_pmc_alternative(ev, flags);
1921 /* Extra checks for EBB */
1922 err = ebb_event_check(event);
1927 * If this is in a group, check if it can go on with all the
1928 * other hardware events in the group. We assume the event
1929 * hasn't been linked into its leader's sibling list at this point.
1932 if (event->group_leader != event) {
1933 n = collect_events(event->group_leader, ppmu->n_counter - 1,
1934 ctrs, events, cflags);
1941 if (check_excludes(ctrs, cflags, n, 1))
1944 cpuhw = &get_cpu_var(cpu_hw_events);
1945 err = power_check_constraints(cpuhw, events, cflags, n + 1);
1947 if (has_branch_stack(event)) {
1948 bhrb_filter = ppmu->bhrb_filter_map(
1949 event->attr.branch_sample_type);
1951 if (bhrb_filter == -1) {
1952 put_cpu_var(cpu_hw_events);
1955 cpuhw->bhrb_filter = bhrb_filter;
1958 put_cpu_var(cpu_hw_events);
1962 event->hw.config = events[n];
1963 event->hw.event_base = cflags[n];
1964 event->hw.last_period = event->hw.sample_period;
1965 local64_set(&event->hw.period_left, event->hw.last_period);
1968 * For EBB events we just context switch the PMC value, we don't do any
1969 * of the sample_period logic. We use hw.prev_count for this.
1971 if (is_ebb_event(event))
1972 local64_set(&event->hw.prev_count, 0);
1975 * See if we need to reserve the PMU.
1976 * If no events are currently in use, then we have to take a
1977 * mutex to ensure that we don't race with another task doing
1978 * reserve_pmc_hardware or release_pmc_hardware.
1981 if (!atomic_inc_not_zero(&num_events)) {
1982 mutex_lock(&pmc_reserve_mutex);
1983 if (atomic_read(&num_events) == 0 &&
1984 reserve_pmc_hardware(perf_event_interrupt))
1987 atomic_inc(&num_events);
1988 mutex_unlock(&pmc_reserve_mutex);
1990 event->destroy = hw_perf_event_destroy;
1995 static int power_pmu_event_idx(struct perf_event *event)
1997 return event->hw.idx;
2000 ssize_t power_events_sysfs_show(struct device *dev,
2001 struct device_attribute *attr, char *page)
2003 struct perf_pmu_events_attr *pmu_attr;
2005 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
2007 return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
2010 static struct pmu power_pmu = {
2011 .pmu_enable = power_pmu_enable,
2012 .pmu_disable = power_pmu_disable,
2013 .event_init = power_pmu_event_init,
2014 .add = power_pmu_add,
2015 .del = power_pmu_del,
2016 .start = power_pmu_start,
2017 .stop = power_pmu_stop,
2018 .read = power_pmu_read,
2019 .start_txn = power_pmu_start_txn,
2020 .cancel_txn = power_pmu_cancel_txn,
2021 .commit_txn = power_pmu_commit_txn,
2022 .event_idx = power_pmu_event_idx,
2023 .sched_task = power_pmu_sched_task,
2027 * A counter has overflowed; update its count and record
2028 * things if requested. Note that interrupts are hard-disabled
2029 * here so there is no possibility of being interrupted.
2031 static void record_and_restart(struct perf_event *event, unsigned long val,
2032 struct pt_regs *regs)
2034 u64 period = event->hw.sample_period;
2035 s64 prev, delta, left;
2038 if (event->hw.state & PERF_HES_STOPPED) {
2039 write_pmc(event->hw.idx, 0);
2043 /* we don't have to worry about interrupts here */
2044 prev = local64_read(&event->hw.prev_count);
2045 delta = check_and_compute_delta(prev, val);
2046 local64_add(delta, &event->count);
2049 * See if the total period for this event has expired,
2050 * and update for the next period.
2053 left = local64_read(&event->hw.period_left) - delta;
2061 record = siar_valid(regs);
2062 event->hw.last_period = event->hw.sample_period;
2064 if (left < 0x80000000LL)
2065 val = 0x80000000LL - left;
2068 write_pmc(event->hw.idx, val);
2069 local64_set(&event->hw.prev_count, val);
2070 local64_set(&event->hw.period_left, left);
2071 perf_event_update_userpage(event);
2074 * Finally record data if requested.
2077 struct perf_sample_data data;
2079 perf_sample_data_init(&data, ~0ULL, event->hw.last_period);
2081 if (event->attr.sample_type &
2082 (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR))
2083 perf_get_data_addr(event, regs, &data.addr);
2085 if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) {
2086 struct cpu_hw_events *cpuhw;
2087 cpuhw = this_cpu_ptr(&cpu_hw_events);
2088 power_pmu_bhrb_read(event, cpuhw);
2089 data.br_stack = &cpuhw->bhrb_stack;
2092 if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
2093 ppmu->get_mem_data_src)
2094 ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs);
2096 if (event->attr.sample_type & PERF_SAMPLE_WEIGHT &&
2097 ppmu->get_mem_weight)
2098 ppmu->get_mem_weight(&data.weight);
2100 if (perf_event_overflow(event, &data, regs))
2101 power_pmu_stop(event, 0);
2106 * Called from generic code to get the misc flags (i.e. processor mode)
2109 unsigned long perf_misc_flags(struct pt_regs *regs)
2111 u32 flags = perf_get_misc_flags(regs);
2115 return user_mode(regs) ? PERF_RECORD_MISC_USER :
2116 PERF_RECORD_MISC_KERNEL;
2120 * Called from generic code to get the instruction pointer
2123 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2125 bool use_siar = regs_use_siar(regs);
2127 if (use_siar && siar_valid(regs))
2128 return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
2130 return 0; // no valid instruction pointer
2135 static bool pmc_overflow_power7(unsigned long val)
2138 * Events on POWER7 can roll back if a speculative event doesn't
2139 * eventually complete. Unfortunately in some rare cases they will
2140 * raise a performance monitor exception. We need to catch this to
2141 * ensure we reset the PMC. In all cases the PMC will be 256 or less
2142 * cycles from overflow.
2144 * We only do this if the first pass fails to find any overflowing
2145 * PMCs because a user might set a period of less than 256 and we
2146 * don't want to mistakenly reset them.
2148 if ((0x80000000 - val) <= 256)
2154 static bool pmc_overflow(unsigned long val)
2163 * Performance monitor interrupt stuff
2165 static void __perf_event_interrupt(struct pt_regs *regs)
2168 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
2169 struct perf_event *event;
2170 unsigned long val[8];
2174 if (cpuhw->n_limited)
2175 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
2178 perf_read_regs(regs);
2180 nmi = perf_intr_is_nmi(regs);
2186 /* Read all the PMCs since we'll need them a bunch of times */
2187 for (i = 0; i < ppmu->n_counter; ++i)
2188 val[i] = read_pmc(i + 1);
2190 /* Try to find what caused the IRQ */
2192 for (i = 0; i < ppmu->n_counter; ++i) {
2193 if (!pmc_overflow(val[i]))
2195 if (is_limited_pmc(i + 1))
2196 continue; /* these won't generate IRQs */
2198 * We've found one that's overflowed. For active
2199 * counters we need to log this. For inactive
2200 * counters, we need to reset it anyway
2204 for (j = 0; j < cpuhw->n_events; ++j) {
2205 event = cpuhw->event[j];
2206 if (event->hw.idx == (i + 1)) {
2208 record_and_restart(event, val[i], regs);
2213 /* reset non active counters that have overflowed */
2214 write_pmc(i + 1, 0);
2216 if (!found && pvr_version_is(PVR_POWER7)) {
2217 /* check active counters for special buggy p7 overflow */
2218 for (i = 0; i < cpuhw->n_events; ++i) {
2219 event = cpuhw->event[i];
2220 if (!event->hw.idx || is_limited_pmc(event->hw.idx))
2222 if (pmc_overflow_power7(val[event->hw.idx - 1])) {
2223 /* event has overflowed in a buggy way*/
2225 record_and_restart(event,
2226 val[event->hw.idx - 1],
2231 if (!found && !nmi && printk_ratelimit())
2232 printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
2235 * Reset MMCR0 to its normal value. This will set PMXE and
2236 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
2237 * and thus allow interrupts to occur again.
2238 * XXX might want to use MSR.PM to keep the events frozen until
2239 * we get back out of this interrupt.
2241 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
2249 static void perf_event_interrupt(struct pt_regs *regs)
2251 u64 start_clock = sched_clock();
2253 __perf_event_interrupt(regs);
2254 perf_sample_event_took(sched_clock() - start_clock);
2257 static int power_pmu_prepare_cpu(unsigned int cpu)
2259 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
2262 memset(cpuhw, 0, sizeof(*cpuhw));
2263 cpuhw->mmcr[0] = MMCR0_FC;
2268 int register_power_pmu(struct power_pmu *pmu)
2271 return -EBUSY; /* something's already registered */
2274 pr_info("%s performance monitor hardware support registered\n",
2277 power_pmu.attr_groups = ppmu->attr_groups;
2281 * Use FCHV to ignore kernel events if MSR.HV is set.
2283 if (mfmsr() & MSR_HV)
2284 freeze_events_kernel = MMCR0_FCHV;
2285 #endif /* CONFIG_PPC64 */
2287 perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW);
2288 cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare",
2289 power_pmu_prepare_cpu, NULL);
2294 static int __init init_ppc64_pmu(void)
2296 /* run through all the pmu drivers one at a time */
2297 if (!init_power5_pmu())
2299 else if (!init_power5p_pmu())
2301 else if (!init_power6_pmu())
2303 else if (!init_power7_pmu())
2305 else if (!init_power8_pmu())
2307 else if (!init_power9_pmu())
2309 else if (!init_ppc970_pmu())
2312 return init_generic_compat_pmu();
2314 early_initcall(init_ppc64_pmu);