1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Performance event support - powerpc architecture code
5 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/perf_event.h>
11 #include <linux/percpu.h>
12 #include <linux/hardirq.h>
13 #include <linux/uaccess.h>
16 #include <asm/machdep.h>
17 #include <asm/firmware.h>
18 #include <asm/ptrace.h>
19 #include <asm/code-patching.h>
25 #define BHRB_MAX_ENTRIES 32
26 #define BHRB_TARGET 0x0000000000000002
27 #define BHRB_PREDICTION 0x0000000000000001
28 #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL
30 struct cpu_hw_events {
37 struct perf_event *event[MAX_HWEVENTS];
38 u64 events[MAX_HWEVENTS];
39 unsigned int flags[MAX_HWEVENTS];
41 * The order of the MMCR array is:
42 * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2
43 * - 32-bit, MMCR0, MMCR1, MMCR2
45 unsigned long mmcr[4];
46 struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
47 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
48 u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
49 unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
50 unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
52 unsigned int txn_flags;
56 u64 bhrb_filter; /* BHRB HW branch filter */
57 unsigned int bhrb_users;
59 struct perf_branch_stack bhrb_stack;
60 struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES];
64 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
66 static struct power_pmu *ppmu;
69 * Normally, to ignore kernel events we set the FCS (freeze counters
70 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
71 * hypervisor bit set in the MSR, or if we are running on a processor
72 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
73 * then we need to use the FCHV bit to ignore kernel events.
75 static unsigned int freeze_events_kernel = MMCR0_FCS;
78 * 32-bit doesn't have MMCRA but does have an MMCR2,
79 * and a few other names are different.
84 #define MMCR0_PMCjCE MMCR0_PMCnCE
90 #define MMCR0_PMCC_U6 0
92 #define SPRN_MMCRA SPRN_MMCR2
93 #define MMCRA_SAMPLE_ENABLE 0
95 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
99 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { }
100 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
104 static inline void perf_read_regs(struct pt_regs *regs)
108 static inline int perf_intr_is_nmi(struct pt_regs *regs)
113 static inline int siar_valid(struct pt_regs *regs)
118 static bool is_ebb_event(struct perf_event *event) { return false; }
119 static int ebb_event_check(struct perf_event *event) { return 0; }
120 static void ebb_event_add(struct perf_event *event) { }
121 static void ebb_switch_out(unsigned long mmcr0) { }
122 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
124 return cpuhw->mmcr[0];
127 static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
128 static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
129 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {}
130 static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {}
131 static void pmao_restore_workaround(bool ebb) { }
132 #endif /* CONFIG_PPC32 */
134 bool is_sier_available(void)
136 if (ppmu->flags & PPMU_HAS_SIER)
142 static bool regs_use_siar(struct pt_regs *regs)
145 * When we take a performance monitor exception the regs are setup
146 * using perf_read_regs() which overloads some fields, in particular
147 * regs->result to tell us whether to use SIAR.
149 * However if the regs are from another exception, eg. a syscall, then
150 * they have not been setup using perf_read_regs() and so regs->result
151 * is something random.
153 return ((TRAP(regs) == 0xf00) && regs->result);
157 * Things that are specific to 64-bit implementations.
161 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
163 unsigned long mmcra = regs->dsisr;
165 if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) {
166 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
168 return 4 * (slot - 1);
175 * The user wants a data address recorded.
176 * If we're not doing instruction sampling, give them the SDAR
177 * (sampled data address). If we are doing instruction sampling, then
178 * only give them the SDAR if it corresponds to the instruction
179 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the
180 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER.
182 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
184 unsigned long mmcra = regs->dsisr;
187 if (ppmu->flags & PPMU_HAS_SIER)
188 sdar_valid = regs->dar & SIER_SDAR_VALID;
190 unsigned long sdsync;
192 if (ppmu->flags & PPMU_SIAR_VALID)
193 sdsync = POWER7P_MMCRA_SDAR_VALID;
194 else if (ppmu->flags & PPMU_ALT_SIPR)
195 sdsync = POWER6_MMCRA_SDSYNC;
196 else if (ppmu->flags & PPMU_NO_SIAR)
197 sdsync = MMCRA_SAMPLE_ENABLE;
199 sdsync = MMCRA_SDSYNC;
201 sdar_valid = mmcra & sdsync;
204 if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid)
205 *addrp = mfspr(SPRN_SDAR);
207 if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN) &&
208 is_kernel_addr(mfspr(SPRN_SDAR)))
212 static bool regs_sihv(struct pt_regs *regs)
214 unsigned long sihv = MMCRA_SIHV;
216 if (ppmu->flags & PPMU_HAS_SIER)
217 return !!(regs->dar & SIER_SIHV);
219 if (ppmu->flags & PPMU_ALT_SIPR)
220 sihv = POWER6_MMCRA_SIHV;
222 return !!(regs->dsisr & sihv);
225 static bool regs_sipr(struct pt_regs *regs)
227 unsigned long sipr = MMCRA_SIPR;
229 if (ppmu->flags & PPMU_HAS_SIER)
230 return !!(regs->dar & SIER_SIPR);
232 if (ppmu->flags & PPMU_ALT_SIPR)
233 sipr = POWER6_MMCRA_SIPR;
235 return !!(regs->dsisr & sipr);
238 static inline u32 perf_flags_from_msr(struct pt_regs *regs)
240 if (regs->msr & MSR_PR)
241 return PERF_RECORD_MISC_USER;
242 if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV)
243 return PERF_RECORD_MISC_HYPERVISOR;
244 return PERF_RECORD_MISC_KERNEL;
247 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
249 bool use_siar = regs_use_siar(regs);
252 return perf_flags_from_msr(regs);
255 * If we don't have flags in MMCRA, rather than using
256 * the MSR, we intuit the flags from the address in
257 * SIAR which should give slightly more reliable
260 if (ppmu->flags & PPMU_NO_SIPR) {
261 unsigned long siar = mfspr(SPRN_SIAR);
262 if (is_kernel_addr(siar))
263 return PERF_RECORD_MISC_KERNEL;
264 return PERF_RECORD_MISC_USER;
267 /* PR has priority over HV, so order below is important */
269 return PERF_RECORD_MISC_USER;
271 if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV))
272 return PERF_RECORD_MISC_HYPERVISOR;
274 return PERF_RECORD_MISC_KERNEL;
278 * Overload regs->dsisr to store MMCRA so we only need to read it once
280 * Overload regs->dar to store SIER if we have it.
281 * Overload regs->result to specify whether we should use the MSR (result
282 * is zero) or the SIAR (result is non zero).
284 static inline void perf_read_regs(struct pt_regs *regs)
286 unsigned long mmcra = mfspr(SPRN_MMCRA);
287 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
292 if (ppmu->flags & PPMU_HAS_SIER)
293 regs->dar = mfspr(SPRN_SIER);
296 * If this isn't a PMU exception (eg a software event) the SIAR is
297 * not valid. Use pt_regs.
299 * If it is a marked event use the SIAR.
301 * If the PMU doesn't update the SIAR for non marked events use
304 * If the PMU has HV/PR flags then check to see if they
305 * place the exception in userspace. If so, use pt_regs. In
306 * continuous sampling mode the SIAR and the PMU exception are
307 * not synchronised, so they may be many instructions apart.
308 * This can result in confusing backtraces. We still want
309 * hypervisor samples as well as samples in the kernel with
310 * interrupts off hence the userspace check.
312 if (TRAP(regs) != 0xf00)
314 else if ((ppmu->flags & PPMU_NO_SIAR))
318 else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))
320 else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs))
325 regs->result = use_siar;
329 * If interrupts were soft-disabled when a PMU interrupt occurs, treat
332 static inline int perf_intr_is_nmi(struct pt_regs *regs)
334 return (regs->softe & IRQS_DISABLED);
338 * On processors like P7+ that have the SIAR-Valid bit, marked instructions
339 * must be sampled only if the SIAR-valid bit is set.
341 * For unmarked instructions and for processors that don't have the SIAR-Valid
342 * bit, assume that SIAR is valid.
344 static inline int siar_valid(struct pt_regs *regs)
346 unsigned long mmcra = regs->dsisr;
347 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
350 if (ppmu->flags & PPMU_HAS_SIER)
351 return regs->dar & SIER_SIAR_VALID;
353 if (ppmu->flags & PPMU_SIAR_VALID)
354 return mmcra & POWER7P_MMCRA_SIAR_VALID;
361 /* Reset all possible BHRB entries */
362 static void power_pmu_bhrb_reset(void)
364 asm volatile(PPC_CLRBHRB);
367 static void power_pmu_bhrb_enable(struct perf_event *event)
369 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
374 /* Clear BHRB if we changed task context to avoid data leaks */
375 if (event->ctx->task && cpuhw->bhrb_context != event->ctx) {
376 power_pmu_bhrb_reset();
377 cpuhw->bhrb_context = event->ctx;
380 perf_sched_cb_inc(event->ctx->pmu);
383 static void power_pmu_bhrb_disable(struct perf_event *event)
385 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
390 WARN_ON_ONCE(!cpuhw->bhrb_users);
392 perf_sched_cb_dec(event->ctx->pmu);
394 if (!cpuhw->disabled && !cpuhw->bhrb_users) {
395 /* BHRB cannot be turned off when other
396 * events are active on the PMU.
399 /* avoid stale pointer */
400 cpuhw->bhrb_context = NULL;
404 /* Called from ctxsw to prevent one process's branch entries to
405 * mingle with the other process's entries during context switch.
407 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
413 power_pmu_bhrb_reset();
415 /* Calculate the to address for a branch */
416 static __u64 power_pmu_bhrb_to(u64 addr)
422 if (is_kernel_addr(addr)) {
423 if (probe_kernel_read(&instr, (void *)addr, sizeof(instr)))
426 return branch_target(&instr);
429 /* Userspace: need copy instruction here then translate it */
431 ret = __get_user_inatomic(instr, (unsigned int __user *)addr);
438 target = branch_target(&instr);
439 if ((!target) || (instr & BRANCH_ABSOLUTE))
442 /* Translate relative branch target from kernel to user address */
443 return target - (unsigned long)&instr + addr;
446 /* Processing BHRB entries */
447 static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw)
451 int r_index, u_index, pred;
455 while (r_index < ppmu->bhrb_nr) {
456 /* Assembly read function */
457 val = read_bhrb(r_index++);
459 /* Terminal marker: End of valid BHRB entries */
462 addr = val & BHRB_EA;
463 pred = val & BHRB_PREDICTION;
470 * BHRB rolling buffer could very much contain the kernel
471 * addresses at this point. Check the privileges before
472 * exporting it to userspace (avoid exposure of regions
473 * where we could have speculative execution)
475 if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN) &&
476 is_kernel_addr(addr))
479 /* Branches are read most recent first (ie. mfbhrb 0 is
480 * the most recent branch).
481 * There are two types of valid entries:
482 * 1) a target entry which is the to address of a
483 * computed goto like a blr,bctr,btar. The next
484 * entry read from the bhrb will be branch
485 * corresponding to this target (ie. the actual
486 * blr/bctr/btar instruction).
487 * 2) a from address which is an actual branch. If a
488 * target entry proceeds this, then this is the
489 * matching branch for that target. If this is not
490 * following a target entry, then this is a branch
491 * where the target is given as an immediate field
492 * in the instruction (ie. an i or b form branch).
493 * In this case we need to read the instruction from
494 * memory to determine the target/to address.
497 if (val & BHRB_TARGET) {
498 /* Target branches use two entries
499 * (ie. computed gotos/XL form)
501 cpuhw->bhrb_entries[u_index].to = addr;
502 cpuhw->bhrb_entries[u_index].mispred = pred;
503 cpuhw->bhrb_entries[u_index].predicted = ~pred;
505 /* Get from address in next entry */
506 val = read_bhrb(r_index++);
507 addr = val & BHRB_EA;
508 if (val & BHRB_TARGET) {
509 /* Shouldn't have two targets in a
510 row.. Reset index and try again */
514 cpuhw->bhrb_entries[u_index].from = addr;
516 /* Branches to immediate field
518 cpuhw->bhrb_entries[u_index].from = addr;
519 cpuhw->bhrb_entries[u_index].to =
520 power_pmu_bhrb_to(addr);
521 cpuhw->bhrb_entries[u_index].mispred = pred;
522 cpuhw->bhrb_entries[u_index].predicted = ~pred;
528 cpuhw->bhrb_stack.nr = u_index;
532 static bool is_ebb_event(struct perf_event *event)
535 * This could be a per-PMU callback, but we'd rather avoid the cost. We
536 * check that the PMU supports EBB, meaning those that don't can still
537 * use bit 63 of the event code for something else if they wish.
539 return (ppmu->flags & PPMU_ARCH_207S) &&
540 ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1);
543 static int ebb_event_check(struct perf_event *event)
545 struct perf_event *leader = event->group_leader;
547 /* Event and group leader must agree on EBB */
548 if (is_ebb_event(leader) != is_ebb_event(event))
551 if (is_ebb_event(event)) {
552 if (!(event->attach_state & PERF_ATTACH_TASK))
555 if (!leader->attr.pinned || !leader->attr.exclusive)
558 if (event->attr.freq ||
559 event->attr.inherit ||
560 event->attr.sample_type ||
561 event->attr.sample_period ||
562 event->attr.enable_on_exec)
569 static void ebb_event_add(struct perf_event *event)
571 if (!is_ebb_event(event) || current->thread.used_ebb)
575 * IFF this is the first time we've added an EBB event, set
576 * PMXE in the user MMCR0 so we can detect when it's cleared by
577 * userspace. We need this so that we can context switch while
578 * userspace is in the EBB handler (where PMXE is 0).
580 current->thread.used_ebb = 1;
581 current->thread.mmcr0 |= MMCR0_PMXE;
584 static void ebb_switch_out(unsigned long mmcr0)
586 if (!(mmcr0 & MMCR0_EBE))
589 current->thread.siar = mfspr(SPRN_SIAR);
590 current->thread.sier = mfspr(SPRN_SIER);
591 current->thread.sdar = mfspr(SPRN_SDAR);
592 current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;
593 current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
596 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
598 unsigned long mmcr0 = cpuhw->mmcr[0];
603 /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */
604 mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6;
607 * Add any bits from the user MMCR0, FC or PMAO. This is compatible
608 * with pmao_restore_workaround() because we may add PMAO but we never
611 mmcr0 |= current->thread.mmcr0;
614 * Be careful not to set PMXE if userspace had it cleared. This is also
615 * compatible with pmao_restore_workaround() because it has already
616 * cleared PMXE and we leave PMAO alone.
618 if (!(current->thread.mmcr0 & MMCR0_PMXE))
619 mmcr0 &= ~MMCR0_PMXE;
621 mtspr(SPRN_SIAR, current->thread.siar);
622 mtspr(SPRN_SIER, current->thread.sier);
623 mtspr(SPRN_SDAR, current->thread.sdar);
626 * Merge the kernel & user values of MMCR2. The semantics we implement
627 * are that the user MMCR2 can set bits, ie. cause counters to freeze,
628 * but not clear bits. If a task wants to be able to clear bits, ie.
629 * unfreeze counters, it should not set exclude_xxx in its events and
630 * instead manage the MMCR2 entirely by itself.
632 mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2);
637 static void pmao_restore_workaround(bool ebb)
641 if (!cpu_has_feature(CPU_FTR_PMAO_BUG))
645 * On POWER8E there is a hardware defect which affects the PMU context
646 * switch logic, ie. power_pmu_disable/enable().
648 * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0
649 * by the hardware. Sometime later the actual PMU exception is
652 * If we context switch, or simply disable/enable, the PMU prior to the
653 * exception arriving, the exception will be lost when we clear PMAO.
655 * When we reenable the PMU, we will write the saved MMCR0 with PMAO
656 * set, and this _should_ generate an exception. However because of the
657 * defect no exception is generated when we write PMAO, and we get
658 * stuck with no counters counting but no exception delivered.
660 * The workaround is to detect this case and tweak the hardware to
661 * create another pending PMU exception.
663 * We do that by setting up PMC6 (cycles) for an imminent overflow and
664 * enabling the PMU. That causes a new exception to be generated in the
665 * chip, but we don't take it yet because we have interrupts hard
666 * disabled. We then write back the PMU state as we want it to be seen
667 * by the exception handler. When we reenable interrupts the exception
668 * handler will be called and see the correct state.
670 * The logic is the same for EBB, except that the exception is gated by
671 * us having interrupts hard disabled as well as the fact that we are
672 * not in userspace. The exception is finally delivered when we return
676 /* Only if PMAO is set and PMAO_SYNC is clear */
677 if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO)
680 /* If we're doing EBB, only if BESCR[GE] is set */
681 if (ebb && !(current->thread.bescr & BESCR_GE))
685 * We are already soft-disabled in power_pmu_enable(). We need to hard
686 * disable to actually prevent the PMU exception from firing.
691 * This is a bit gross, but we know we're on POWER8E and have 6 PMCs.
692 * Using read/write_pmc() in a for loop adds 12 function calls and
693 * almost doubles our code size.
695 pmcs[0] = mfspr(SPRN_PMC1);
696 pmcs[1] = mfspr(SPRN_PMC2);
697 pmcs[2] = mfspr(SPRN_PMC3);
698 pmcs[3] = mfspr(SPRN_PMC4);
699 pmcs[4] = mfspr(SPRN_PMC5);
700 pmcs[5] = mfspr(SPRN_PMC6);
702 /* Ensure all freeze bits are unset */
703 mtspr(SPRN_MMCR2, 0);
705 /* Set up PMC6 to overflow in one cycle */
706 mtspr(SPRN_PMC6, 0x7FFFFFFE);
708 /* Enable exceptions and unfreeze PMC6 */
709 mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO);
711 /* Now we need to refreeze and restore the PMCs */
712 mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO);
714 mtspr(SPRN_PMC1, pmcs[0]);
715 mtspr(SPRN_PMC2, pmcs[1]);
716 mtspr(SPRN_PMC3, pmcs[2]);
717 mtspr(SPRN_PMC4, pmcs[3]);
718 mtspr(SPRN_PMC5, pmcs[4]);
719 mtspr(SPRN_PMC6, pmcs[5]);
722 #endif /* CONFIG_PPC64 */
724 static void perf_event_interrupt(struct pt_regs *regs);
727 * Read one performance monitor counter (PMC).
729 static unsigned long read_pmc(int idx)
735 val = mfspr(SPRN_PMC1);
738 val = mfspr(SPRN_PMC2);
741 val = mfspr(SPRN_PMC3);
744 val = mfspr(SPRN_PMC4);
747 val = mfspr(SPRN_PMC5);
750 val = mfspr(SPRN_PMC6);
754 val = mfspr(SPRN_PMC7);
757 val = mfspr(SPRN_PMC8);
759 #endif /* CONFIG_PPC64 */
761 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
770 static void write_pmc(int idx, unsigned long val)
774 mtspr(SPRN_PMC1, val);
777 mtspr(SPRN_PMC2, val);
780 mtspr(SPRN_PMC3, val);
783 mtspr(SPRN_PMC4, val);
786 mtspr(SPRN_PMC5, val);
789 mtspr(SPRN_PMC6, val);
793 mtspr(SPRN_PMC7, val);
796 mtspr(SPRN_PMC8, val);
798 #endif /* CONFIG_PPC64 */
800 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
804 /* Called from sysrq_handle_showregs() */
805 void perf_event_print_debug(void)
807 unsigned long sdar, sier, flags;
808 u32 pmcs[MAX_HWEVENTS];
812 pr_info("Performance monitor hardware not registered.\n");
816 if (!ppmu->n_counter)
819 local_irq_save(flags);
821 pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d",
822 smp_processor_id(), ppmu->name, ppmu->n_counter);
824 for (i = 0; i < ppmu->n_counter; i++)
825 pmcs[i] = read_pmc(i + 1);
827 for (; i < MAX_HWEVENTS; i++)
828 pmcs[i] = 0xdeadbeef;
830 pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n",
831 pmcs[0], pmcs[1], pmcs[2], pmcs[3]);
833 if (ppmu->n_counter > 4)
834 pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n",
835 pmcs[4], pmcs[5], pmcs[6], pmcs[7]);
837 pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n",
838 mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA));
842 sdar = mfspr(SPRN_SDAR);
844 if (ppmu->flags & PPMU_HAS_SIER)
845 sier = mfspr(SPRN_SIER);
847 if (ppmu->flags & PPMU_ARCH_207S) {
848 pr_info("MMCR2: %016lx EBBHR: %016lx\n",
849 mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR));
850 pr_info("EBBRR: %016lx BESCR: %016lx\n",
851 mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR));
854 pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n",
855 mfspr(SPRN_SIAR), sdar, sier);
857 local_irq_restore(flags);
861 * Check if a set of events can all go on the PMU at once.
862 * If they can't, this will look at alternative codes for the events
863 * and see if any combination of alternative codes is feasible.
864 * The feasible set is returned in event_id[].
866 static int power_check_constraints(struct cpu_hw_events *cpuhw,
867 u64 event_id[], unsigned int cflags[],
870 unsigned long mask, value, nv;
871 unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS];
872 int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS];
874 unsigned long addf = ppmu->add_fields;
875 unsigned long tadd = ppmu->test_adder;
876 unsigned long grp_mask = ppmu->group_constraint_mask;
877 unsigned long grp_val = ppmu->group_constraint_val;
879 if (n_ev > ppmu->n_counter)
882 /* First see if the events will go on as-is */
883 for (i = 0; i < n_ev; ++i) {
884 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
885 && !ppmu->limited_pmc_event(event_id[i])) {
886 ppmu->get_alternatives(event_id[i], cflags[i],
887 cpuhw->alternatives[i]);
888 event_id[i] = cpuhw->alternatives[i][0];
890 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
891 &cpuhw->avalues[i][0]))
895 for (i = 0; i < n_ev; ++i) {
896 nv = (value | cpuhw->avalues[i][0]) +
897 (value & cpuhw->avalues[i][0] & addf);
899 if (((((nv + tadd) ^ value) & mask) & (~grp_mask)) != 0)
902 if (((((nv + tadd) ^ cpuhw->avalues[i][0]) & cpuhw->amasks[i][0])
907 mask |= cpuhw->amasks[i][0];
910 if ((value & mask & grp_mask) != (mask & grp_val))
913 return 0; /* all OK */
916 /* doesn't work, gather alternatives... */
917 if (!ppmu->get_alternatives)
919 for (i = 0; i < n_ev; ++i) {
921 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i],
922 cpuhw->alternatives[i]);
923 for (j = 1; j < n_alt[i]; ++j)
924 ppmu->get_constraint(cpuhw->alternatives[i][j],
925 &cpuhw->amasks[i][j],
926 &cpuhw->avalues[i][j]);
929 /* enumerate all possibilities and see if any will work */
932 value = mask = nv = 0;
935 /* we're backtracking, restore context */
941 * See if any alternative k for event_id i,
942 * where k > j, will satisfy the constraints.
944 while (++j < n_alt[i]) {
945 nv = (value | cpuhw->avalues[i][j]) +
946 (value & cpuhw->avalues[i][j] & addf);
947 if ((((nv + tadd) ^ value) & mask) == 0 &&
948 (((nv + tadd) ^ cpuhw->avalues[i][j])
949 & cpuhw->amasks[i][j]) == 0)
954 * No feasible alternative, backtrack
955 * to event_id i-1 and continue enumerating its
956 * alternatives from where we got up to.
962 * Found a feasible alternative for event_id i,
963 * remember where we got up to with this event_id,
964 * go on to the next event_id, and start with
965 * the first alternative for it.
971 mask |= cpuhw->amasks[i][j];
977 /* OK, we have a feasible combination, tell the caller the solution */
978 for (i = 0; i < n_ev; ++i)
979 event_id[i] = cpuhw->alternatives[i][choice[i]];
984 * Check if newly-added events have consistent settings for
985 * exclude_{user,kernel,hv} with each other and any previously
988 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
989 int n_prev, int n_new)
991 int eu = 0, ek = 0, eh = 0;
993 struct perf_event *event;
996 * If the PMU we're on supports per event exclude settings then we
997 * don't need to do any of this logic. NB. This assumes no PMU has both
998 * per event exclude and limited PMCs.
1000 if (ppmu->flags & PPMU_ARCH_207S)
1008 for (i = 0; i < n; ++i) {
1009 if (cflags[i] & PPMU_LIMITED_PMC_OK) {
1010 cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
1015 eu = event->attr.exclude_user;
1016 ek = event->attr.exclude_kernel;
1017 eh = event->attr.exclude_hv;
1019 } else if (event->attr.exclude_user != eu ||
1020 event->attr.exclude_kernel != ek ||
1021 event->attr.exclude_hv != eh) {
1027 for (i = 0; i < n; ++i)
1028 if (cflags[i] & PPMU_LIMITED_PMC_OK)
1029 cflags[i] |= PPMU_LIMITED_PMC_REQD;
1034 static u64 check_and_compute_delta(u64 prev, u64 val)
1036 u64 delta = (val - prev) & 0xfffffffful;
1039 * POWER7 can roll back counter values, if the new value is smaller
1040 * than the previous value it will cause the delta and the counter to
1041 * have bogus values unless we rolled a counter over. If a coutner is
1042 * rolled back, it will be smaller, but within 256, which is the maximum
1043 * number of events to rollback at once. If we detect a rollback
1044 * return 0. This can lead to a small lack of precision in the
1047 if (prev > val && (prev - val) < 256)
1053 static void power_pmu_read(struct perf_event *event)
1055 s64 val, delta, prev;
1057 if (event->hw.state & PERF_HES_STOPPED)
1063 if (is_ebb_event(event)) {
1064 val = read_pmc(event->hw.idx);
1065 local64_set(&event->hw.prev_count, val);
1070 * Performance monitor interrupts come even when interrupts
1071 * are soft-disabled, as long as interrupts are hard-enabled.
1072 * Therefore we treat them like NMIs.
1075 prev = local64_read(&event->hw.prev_count);
1077 val = read_pmc(event->hw.idx);
1078 delta = check_and_compute_delta(prev, val);
1081 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
1083 local64_add(delta, &event->count);
1086 * A number of places program the PMC with (0x80000000 - period_left).
1087 * We never want period_left to be less than 1 because we will program
1088 * the PMC with a value >= 0x800000000 and an edge detected PMC will
1089 * roll around to 0 before taking an exception. We have seen this
1092 * To fix this, clamp the minimum value of period_left to 1.
1095 prev = local64_read(&event->hw.period_left);
1099 } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev);
1103 * On some machines, PMC5 and PMC6 can't be written, don't respect
1104 * the freeze conditions, and don't generate interrupts. This tells
1105 * us if `event' is using such a PMC.
1107 static int is_limited_pmc(int pmcnum)
1109 return (ppmu->flags & PPMU_LIMITED_PMC5_6)
1110 && (pmcnum == 5 || pmcnum == 6);
1113 static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
1114 unsigned long pmc5, unsigned long pmc6)
1116 struct perf_event *event;
1117 u64 val, prev, delta;
1120 for (i = 0; i < cpuhw->n_limited; ++i) {
1121 event = cpuhw->limited_counter[i];
1124 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1125 prev = local64_read(&event->hw.prev_count);
1127 delta = check_and_compute_delta(prev, val);
1129 local64_add(delta, &event->count);
1133 static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
1134 unsigned long pmc5, unsigned long pmc6)
1136 struct perf_event *event;
1140 for (i = 0; i < cpuhw->n_limited; ++i) {
1141 event = cpuhw->limited_counter[i];
1142 event->hw.idx = cpuhw->limited_hwidx[i];
1143 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1144 prev = local64_read(&event->hw.prev_count);
1145 if (check_and_compute_delta(prev, val))
1146 local64_set(&event->hw.prev_count, val);
1147 perf_event_update_userpage(event);
1152 * Since limited events don't respect the freeze conditions, we
1153 * have to read them immediately after freezing or unfreezing the
1154 * other events. We try to keep the values from the limited
1155 * events as consistent as possible by keeping the delay (in
1156 * cycles and instructions) between freezing/unfreezing and reading
1157 * the limited events as small and consistent as possible.
1158 * Therefore, if any limited events are in use, we read them
1159 * both, and always in the same order, to minimize variability,
1160 * and do it inside the same asm that writes MMCR0.
1162 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
1164 unsigned long pmc5, pmc6;
1166 if (!cpuhw->n_limited) {
1167 mtspr(SPRN_MMCR0, mmcr0);
1172 * Write MMCR0, then read PMC5 and PMC6 immediately.
1173 * To ensure we don't get a performance monitor interrupt
1174 * between writing MMCR0 and freezing/thawing the limited
1175 * events, we first write MMCR0 with the event overflow
1176 * interrupt enable bits turned off.
1178 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
1179 : "=&r" (pmc5), "=&r" (pmc6)
1180 : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
1182 "i" (SPRN_PMC5), "i" (SPRN_PMC6));
1184 if (mmcr0 & MMCR0_FC)
1185 freeze_limited_counters(cpuhw, pmc5, pmc6);
1187 thaw_limited_counters(cpuhw, pmc5, pmc6);
1190 * Write the full MMCR0 including the event overflow interrupt
1191 * enable bits, if necessary.
1193 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
1194 mtspr(SPRN_MMCR0, mmcr0);
1198 * Disable all events to prevent PMU interrupts and to allow
1199 * events to be added or removed.
1201 static void power_pmu_disable(struct pmu *pmu)
1203 struct cpu_hw_events *cpuhw;
1204 unsigned long flags, mmcr0, val;
1208 local_irq_save(flags);
1209 cpuhw = this_cpu_ptr(&cpu_hw_events);
1211 if (!cpuhw->disabled) {
1213 * Check if we ever enabled the PMU on this cpu.
1215 if (!cpuhw->pmcs_enabled) {
1217 cpuhw->pmcs_enabled = 1;
1221 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56
1223 val = mmcr0 = mfspr(SPRN_MMCR0);
1225 val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
1229 * The barrier is to make sure the mtspr has been
1230 * executed and the PMU has frozen the events etc.
1233 write_mmcr0(cpuhw, val);
1238 * Disable instruction sampling if it was enabled
1240 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1242 cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1247 cpuhw->disabled = 1;
1250 ebb_switch_out(mmcr0);
1254 * These are readable by userspace, may contain kernel
1255 * addresses and are not switched by context switch, so clear
1256 * them now to avoid leaking anything to userspace in general
1257 * including to another process.
1259 if (ppmu->flags & PPMU_ARCH_207S) {
1260 mtspr(SPRN_SDAR, 0);
1261 mtspr(SPRN_SIAR, 0);
1266 local_irq_restore(flags);
1270 * Re-enable all events if disable == 0.
1271 * If we were previously disabled and events were added, then
1272 * put the new config on the PMU.
1274 static void power_pmu_enable(struct pmu *pmu)
1276 struct perf_event *event;
1277 struct cpu_hw_events *cpuhw;
1278 unsigned long flags;
1280 unsigned long val, mmcr0;
1282 unsigned int hwc_index[MAX_HWEVENTS];
1289 local_irq_save(flags);
1291 cpuhw = this_cpu_ptr(&cpu_hw_events);
1292 if (!cpuhw->disabled)
1295 if (cpuhw->n_events == 0) {
1296 ppc_set_pmu_inuse(0);
1300 cpuhw->disabled = 0;
1303 * EBB requires an exclusive group and all events must have the EBB
1304 * flag set, or not set, so we can just check a single event. Also we
1305 * know we have at least one event.
1307 ebb = is_ebb_event(cpuhw->event[0]);
1310 * If we didn't change anything, or only removed events,
1311 * no need to recalculate MMCR* settings and reset the PMCs.
1312 * Just reenable the PMU with the current MMCR* settings
1313 * (possibly updated for removal of events).
1315 if (!cpuhw->n_added) {
1316 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1317 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1322 * Clear all MMCR settings and recompute them for the new set of events.
1324 memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr));
1326 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
1327 cpuhw->mmcr, cpuhw->event)) {
1328 /* shouldn't ever get here */
1329 printk(KERN_ERR "oops compute_mmcr failed\n");
1333 if (!(ppmu->flags & PPMU_ARCH_207S)) {
1335 * Add in MMCR0 freeze bits corresponding to the attr.exclude_*
1336 * bits for the first event. We have already checked that all
1337 * events have the same value for these bits as the first event.
1339 event = cpuhw->event[0];
1340 if (event->attr.exclude_user)
1341 cpuhw->mmcr[0] |= MMCR0_FCP;
1342 if (event->attr.exclude_kernel)
1343 cpuhw->mmcr[0] |= freeze_events_kernel;
1344 if (event->attr.exclude_hv)
1345 cpuhw->mmcr[0] |= MMCR0_FCHV;
1349 * Write the new configuration to MMCR* with the freeze
1350 * bit set and set the hardware events to their initial values.
1351 * Then unfreeze the events.
1353 ppc_set_pmu_inuse(1);
1354 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1355 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1356 mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
1358 if (ppmu->flags & PPMU_ARCH_207S)
1359 mtspr(SPRN_MMCR2, cpuhw->mmcr[3]);
1362 * Read off any pre-existing events that need to move
1365 for (i = 0; i < cpuhw->n_events; ++i) {
1366 event = cpuhw->event[i];
1367 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
1368 power_pmu_read(event);
1369 write_pmc(event->hw.idx, 0);
1375 * Initialize the PMCs for all the new and moved events.
1377 cpuhw->n_limited = n_lim = 0;
1378 for (i = 0; i < cpuhw->n_events; ++i) {
1379 event = cpuhw->event[i];
1382 idx = hwc_index[i] + 1;
1383 if (is_limited_pmc(idx)) {
1384 cpuhw->limited_counter[n_lim] = event;
1385 cpuhw->limited_hwidx[n_lim] = idx;
1391 val = local64_read(&event->hw.prev_count);
1394 if (event->hw.sample_period) {
1395 left = local64_read(&event->hw.period_left);
1396 if (left < 0x80000000L)
1397 val = 0x80000000L - left;
1399 local64_set(&event->hw.prev_count, val);
1402 event->hw.idx = idx;
1403 if (event->hw.state & PERF_HES_STOPPED)
1405 write_pmc(idx, val);
1407 perf_event_update_userpage(event);
1409 cpuhw->n_limited = n_lim;
1410 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
1413 pmao_restore_workaround(ebb);
1415 mmcr0 = ebb_switch_in(ebb, cpuhw);
1418 if (cpuhw->bhrb_users)
1419 ppmu->config_bhrb(cpuhw->bhrb_filter);
1421 write_mmcr0(cpuhw, mmcr0);
1424 * Enable instruction sampling if necessary
1426 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1428 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
1433 local_irq_restore(flags);
1436 static int collect_events(struct perf_event *group, int max_count,
1437 struct perf_event *ctrs[], u64 *events,
1438 unsigned int *flags)
1441 struct perf_event *event;
1443 if (group->pmu->task_ctx_nr == perf_hw_context) {
1447 flags[n] = group->hw.event_base;
1448 events[n++] = group->hw.config;
1450 for_each_sibling_event(event, group) {
1451 if (event->pmu->task_ctx_nr == perf_hw_context &&
1452 event->state != PERF_EVENT_STATE_OFF) {
1456 flags[n] = event->hw.event_base;
1457 events[n++] = event->hw.config;
1464 * Add an event to the PMU.
1465 * If all events are not already frozen, then we disable and
1466 * re-enable the PMU in order to get hw_perf_enable to do the
1467 * actual work of reconfiguring the PMU.
1469 static int power_pmu_add(struct perf_event *event, int ef_flags)
1471 struct cpu_hw_events *cpuhw;
1472 unsigned long flags;
1476 local_irq_save(flags);
1477 perf_pmu_disable(event->pmu);
1480 * Add the event to the list (if there is room)
1481 * and check whether the total set is still feasible.
1483 cpuhw = this_cpu_ptr(&cpu_hw_events);
1484 n0 = cpuhw->n_events;
1485 if (n0 >= ppmu->n_counter)
1487 cpuhw->event[n0] = event;
1488 cpuhw->events[n0] = event->hw.config;
1489 cpuhw->flags[n0] = event->hw.event_base;
1492 * This event may have been disabled/stopped in record_and_restart()
1493 * because we exceeded the ->event_limit. If re-starting the event,
1494 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user
1495 * notification is re-enabled.
1497 if (!(ef_flags & PERF_EF_START))
1498 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
1500 event->hw.state = 0;
1503 * If group events scheduling transaction was started,
1504 * skip the schedulability test here, it will be performed
1505 * at commit time(->commit_txn) as a whole
1507 if (cpuhw->txn_flags & PERF_PMU_TXN_ADD)
1510 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
1512 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
1514 event->hw.config = cpuhw->events[n0];
1517 ebb_event_add(event);
1524 if (has_branch_stack(event)) {
1525 power_pmu_bhrb_enable(event);
1526 cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1527 event->attr.branch_sample_type);
1530 perf_pmu_enable(event->pmu);
1531 local_irq_restore(flags);
1536 * Remove an event from the PMU.
1538 static void power_pmu_del(struct perf_event *event, int ef_flags)
1540 struct cpu_hw_events *cpuhw;
1542 unsigned long flags;
1544 local_irq_save(flags);
1545 perf_pmu_disable(event->pmu);
1547 power_pmu_read(event);
1549 cpuhw = this_cpu_ptr(&cpu_hw_events);
1550 for (i = 0; i < cpuhw->n_events; ++i) {
1551 if (event == cpuhw->event[i]) {
1552 while (++i < cpuhw->n_events) {
1553 cpuhw->event[i-1] = cpuhw->event[i];
1554 cpuhw->events[i-1] = cpuhw->events[i];
1555 cpuhw->flags[i-1] = cpuhw->flags[i];
1558 ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr);
1559 if (event->hw.idx) {
1560 write_pmc(event->hw.idx, 0);
1563 perf_event_update_userpage(event);
1567 for (i = 0; i < cpuhw->n_limited; ++i)
1568 if (event == cpuhw->limited_counter[i])
1570 if (i < cpuhw->n_limited) {
1571 while (++i < cpuhw->n_limited) {
1572 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
1573 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
1577 if (cpuhw->n_events == 0) {
1578 /* disable exceptions if no events are running */
1579 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
1582 if (has_branch_stack(event))
1583 power_pmu_bhrb_disable(event);
1585 perf_pmu_enable(event->pmu);
1586 local_irq_restore(flags);
1590 * POWER-PMU does not support disabling individual counters, hence
1591 * program their cycle counter to their max value and ignore the interrupts.
1594 static void power_pmu_start(struct perf_event *event, int ef_flags)
1596 unsigned long flags;
1600 if (!event->hw.idx || !event->hw.sample_period)
1603 if (!(event->hw.state & PERF_HES_STOPPED))
1606 if (ef_flags & PERF_EF_RELOAD)
1607 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1609 local_irq_save(flags);
1610 perf_pmu_disable(event->pmu);
1612 event->hw.state = 0;
1613 left = local64_read(&event->hw.period_left);
1616 if (left < 0x80000000L)
1617 val = 0x80000000L - left;
1619 write_pmc(event->hw.idx, val);
1621 perf_event_update_userpage(event);
1622 perf_pmu_enable(event->pmu);
1623 local_irq_restore(flags);
1626 static void power_pmu_stop(struct perf_event *event, int ef_flags)
1628 unsigned long flags;
1630 if (!event->hw.idx || !event->hw.sample_period)
1633 if (event->hw.state & PERF_HES_STOPPED)
1636 local_irq_save(flags);
1637 perf_pmu_disable(event->pmu);
1639 power_pmu_read(event);
1640 event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
1641 write_pmc(event->hw.idx, 0);
1643 perf_event_update_userpage(event);
1644 perf_pmu_enable(event->pmu);
1645 local_irq_restore(flags);
1649 * Start group events scheduling transaction
1650 * Set the flag to make pmu::enable() not perform the
1651 * schedulability test, it will be performed at commit time
1653 * We only support PERF_PMU_TXN_ADD transactions. Save the
1654 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1657 static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1659 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1661 WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */
1663 cpuhw->txn_flags = txn_flags;
1664 if (txn_flags & ~PERF_PMU_TXN_ADD)
1667 perf_pmu_disable(pmu);
1668 cpuhw->n_txn_start = cpuhw->n_events;
1672 * Stop group events scheduling transaction
1673 * Clear the flag and pmu::enable() will perform the
1674 * schedulability test.
1676 static void power_pmu_cancel_txn(struct pmu *pmu)
1678 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1679 unsigned int txn_flags;
1681 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1683 txn_flags = cpuhw->txn_flags;
1684 cpuhw->txn_flags = 0;
1685 if (txn_flags & ~PERF_PMU_TXN_ADD)
1688 perf_pmu_enable(pmu);
1692 * Commit group events scheduling transaction
1693 * Perform the group schedulability test as a whole
1694 * Return 0 if success
1696 static int power_pmu_commit_txn(struct pmu *pmu)
1698 struct cpu_hw_events *cpuhw;
1704 cpuhw = this_cpu_ptr(&cpu_hw_events);
1705 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1707 if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) {
1708 cpuhw->txn_flags = 0;
1712 n = cpuhw->n_events;
1713 if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
1715 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n);
1719 for (i = cpuhw->n_txn_start; i < n; ++i)
1720 cpuhw->event[i]->hw.config = cpuhw->events[i];
1722 cpuhw->txn_flags = 0;
1723 perf_pmu_enable(pmu);
1728 * Return 1 if we might be able to put event on a limited PMC,
1730 * An event can only go on a limited PMC if it counts something
1731 * that a limited PMC can count, doesn't require interrupts, and
1732 * doesn't exclude any processor mode.
1734 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev,
1738 u64 alt[MAX_EVENT_ALTERNATIVES];
1740 if (event->attr.exclude_user
1741 || event->attr.exclude_kernel
1742 || event->attr.exclude_hv
1743 || event->attr.sample_period)
1746 if (ppmu->limited_pmc_event(ev))
1750 * The requested event_id isn't on a limited PMC already;
1751 * see if any alternative code goes on a limited PMC.
1753 if (!ppmu->get_alternatives)
1756 flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
1757 n = ppmu->get_alternatives(ev, flags, alt);
1763 * Find an alternative event_id that goes on a normal PMC, if possible,
1764 * and return the event_id code, or 0 if there is no such alternative.
1765 * (Note: event_id code 0 is "don't count" on all machines.)
1767 static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
1769 u64 alt[MAX_EVENT_ALTERNATIVES];
1772 flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
1773 n = ppmu->get_alternatives(ev, flags, alt);
1779 /* Number of perf_events counting hardware events */
1780 static atomic_t num_events;
1781 /* Used to avoid races in calling reserve/release_pmc_hardware */
1782 static DEFINE_MUTEX(pmc_reserve_mutex);
1785 * Release the PMU if this is the last perf_event.
1787 static void hw_perf_event_destroy(struct perf_event *event)
1789 if (!atomic_add_unless(&num_events, -1, 1)) {
1790 mutex_lock(&pmc_reserve_mutex);
1791 if (atomic_dec_return(&num_events) == 0)
1792 release_pmc_hardware();
1793 mutex_unlock(&pmc_reserve_mutex);
1798 * Translate a generic cache event_id config to a raw event_id code.
1800 static int hw_perf_cache_event(u64 config, u64 *eventp)
1802 unsigned long type, op, result;
1805 if (!ppmu->cache_events)
1809 type = config & 0xff;
1810 op = (config >> 8) & 0xff;
1811 result = (config >> 16) & 0xff;
1813 if (type >= PERF_COUNT_HW_CACHE_MAX ||
1814 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
1815 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1818 ev = (*ppmu->cache_events)[type][op][result];
1827 static bool is_event_blacklisted(u64 ev)
1831 for (i=0; i < ppmu->n_blacklist_ev; i++) {
1832 if (ppmu->blacklist_ev[i] == ev)
1839 static int power_pmu_event_init(struct perf_event *event)
1842 unsigned long flags;
1843 struct perf_event *ctrs[MAX_HWEVENTS];
1844 u64 events[MAX_HWEVENTS];
1845 unsigned int cflags[MAX_HWEVENTS];
1848 struct cpu_hw_events *cpuhw;
1854 if (has_branch_stack(event)) {
1855 /* PMU has BHRB enabled */
1856 if (!(ppmu->flags & PPMU_ARCH_207S))
1860 switch (event->attr.type) {
1861 case PERF_TYPE_HARDWARE:
1862 ev = event->attr.config;
1863 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
1866 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1868 ev = ppmu->generic_events[ev];
1870 case PERF_TYPE_HW_CACHE:
1871 err = hw_perf_cache_event(event->attr.config, &ev);
1875 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1879 ev = event->attr.config;
1881 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1888 event->hw.config_base = ev;
1892 * If we are not running on a hypervisor, force the
1893 * exclude_hv bit to 0 so that we don't care what
1894 * the user set it to.
1896 if (!firmware_has_feature(FW_FEATURE_LPAR))
1897 event->attr.exclude_hv = 0;
1900 * If this is a per-task event, then we can use
1901 * PM_RUN_* events interchangeably with their non RUN_*
1902 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1903 * XXX we should check if the task is an idle task.
1906 if (event->attach_state & PERF_ATTACH_TASK)
1907 flags |= PPMU_ONLY_COUNT_RUN;
1910 * If this machine has limited events, check whether this
1911 * event_id could go on a limited event.
1913 if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
1914 if (can_go_on_limited_pmc(event, ev, flags)) {
1915 flags |= PPMU_LIMITED_PMC_OK;
1916 } else if (ppmu->limited_pmc_event(ev)) {
1918 * The requested event_id is on a limited PMC,
1919 * but we can't use a limited PMC; see if any
1920 * alternative goes on a normal PMC.
1922 ev = normal_pmc_alternative(ev, flags);
1928 /* Extra checks for EBB */
1929 err = ebb_event_check(event);
1934 * If this is in a group, check if it can go on with all the
1935 * other hardware events in the group. We assume the event
1936 * hasn't been linked into its leader's sibling list at this point.
1939 if (event->group_leader != event) {
1940 n = collect_events(event->group_leader, ppmu->n_counter - 1,
1941 ctrs, events, cflags);
1948 if (check_excludes(ctrs, cflags, n, 1))
1951 cpuhw = &get_cpu_var(cpu_hw_events);
1952 err = power_check_constraints(cpuhw, events, cflags, n + 1);
1954 if (has_branch_stack(event)) {
1955 bhrb_filter = ppmu->bhrb_filter_map(
1956 event->attr.branch_sample_type);
1958 if (bhrb_filter == -1) {
1959 put_cpu_var(cpu_hw_events);
1962 cpuhw->bhrb_filter = bhrb_filter;
1965 put_cpu_var(cpu_hw_events);
1969 event->hw.config = events[n];
1970 event->hw.event_base = cflags[n];
1971 event->hw.last_period = event->hw.sample_period;
1972 local64_set(&event->hw.period_left, event->hw.last_period);
1975 * For EBB events we just context switch the PMC value, we don't do any
1976 * of the sample_period logic. We use hw.prev_count for this.
1978 if (is_ebb_event(event))
1979 local64_set(&event->hw.prev_count, 0);
1982 * See if we need to reserve the PMU.
1983 * If no events are currently in use, then we have to take a
1984 * mutex to ensure that we don't race with another task doing
1985 * reserve_pmc_hardware or release_pmc_hardware.
1988 if (!atomic_inc_not_zero(&num_events)) {
1989 mutex_lock(&pmc_reserve_mutex);
1990 if (atomic_read(&num_events) == 0 &&
1991 reserve_pmc_hardware(perf_event_interrupt))
1994 atomic_inc(&num_events);
1995 mutex_unlock(&pmc_reserve_mutex);
1997 event->destroy = hw_perf_event_destroy;
2002 static int power_pmu_event_idx(struct perf_event *event)
2004 return event->hw.idx;
2007 ssize_t power_events_sysfs_show(struct device *dev,
2008 struct device_attribute *attr, char *page)
2010 struct perf_pmu_events_attr *pmu_attr;
2012 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
2014 return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
2017 static struct pmu power_pmu = {
2018 .pmu_enable = power_pmu_enable,
2019 .pmu_disable = power_pmu_disable,
2020 .event_init = power_pmu_event_init,
2021 .add = power_pmu_add,
2022 .del = power_pmu_del,
2023 .start = power_pmu_start,
2024 .stop = power_pmu_stop,
2025 .read = power_pmu_read,
2026 .start_txn = power_pmu_start_txn,
2027 .cancel_txn = power_pmu_cancel_txn,
2028 .commit_txn = power_pmu_commit_txn,
2029 .event_idx = power_pmu_event_idx,
2030 .sched_task = power_pmu_sched_task,
2034 * A counter has overflowed; update its count and record
2035 * things if requested. Note that interrupts are hard-disabled
2036 * here so there is no possibility of being interrupted.
2038 static void record_and_restart(struct perf_event *event, unsigned long val,
2039 struct pt_regs *regs)
2041 u64 period = event->hw.sample_period;
2042 s64 prev, delta, left;
2045 if (event->hw.state & PERF_HES_STOPPED) {
2046 write_pmc(event->hw.idx, 0);
2050 /* we don't have to worry about interrupts here */
2051 prev = local64_read(&event->hw.prev_count);
2052 delta = check_and_compute_delta(prev, val);
2053 local64_add(delta, &event->count);
2056 * See if the total period for this event has expired,
2057 * and update for the next period.
2060 left = local64_read(&event->hw.period_left) - delta;
2068 record = siar_valid(regs);
2069 event->hw.last_period = event->hw.sample_period;
2071 if (left < 0x80000000LL)
2072 val = 0x80000000LL - left;
2075 write_pmc(event->hw.idx, val);
2076 local64_set(&event->hw.prev_count, val);
2077 local64_set(&event->hw.period_left, left);
2078 perf_event_update_userpage(event);
2081 * Finally record data if requested.
2084 struct perf_sample_data data;
2086 perf_sample_data_init(&data, ~0ULL, event->hw.last_period);
2088 if (event->attr.sample_type &
2089 (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR))
2090 perf_get_data_addr(regs, &data.addr);
2092 if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) {
2093 struct cpu_hw_events *cpuhw;
2094 cpuhw = this_cpu_ptr(&cpu_hw_events);
2095 power_pmu_bhrb_read(cpuhw);
2096 data.br_stack = &cpuhw->bhrb_stack;
2099 if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
2100 ppmu->get_mem_data_src)
2101 ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs);
2103 if (event->attr.sample_type & PERF_SAMPLE_WEIGHT &&
2104 ppmu->get_mem_weight)
2105 ppmu->get_mem_weight(&data.weight);
2107 if (perf_event_overflow(event, &data, regs))
2108 power_pmu_stop(event, 0);
2113 * Called from generic code to get the misc flags (i.e. processor mode)
2116 unsigned long perf_misc_flags(struct pt_regs *regs)
2118 u32 flags = perf_get_misc_flags(regs);
2122 return user_mode(regs) ? PERF_RECORD_MISC_USER :
2123 PERF_RECORD_MISC_KERNEL;
2127 * Called from generic code to get the instruction pointer
2130 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2132 bool use_siar = regs_use_siar(regs);
2134 if (use_siar && siar_valid(regs))
2135 return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
2137 return 0; // no valid instruction pointer
2142 static bool pmc_overflow_power7(unsigned long val)
2145 * Events on POWER7 can roll back if a speculative event doesn't
2146 * eventually complete. Unfortunately in some rare cases they will
2147 * raise a performance monitor exception. We need to catch this to
2148 * ensure we reset the PMC. In all cases the PMC will be 256 or less
2149 * cycles from overflow.
2151 * We only do this if the first pass fails to find any overflowing
2152 * PMCs because a user might set a period of less than 256 and we
2153 * don't want to mistakenly reset them.
2155 if ((0x80000000 - val) <= 256)
2161 static bool pmc_overflow(unsigned long val)
2170 * Performance monitor interrupt stuff
2172 static void __perf_event_interrupt(struct pt_regs *regs)
2175 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
2176 struct perf_event *event;
2177 unsigned long val[8];
2181 if (cpuhw->n_limited)
2182 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
2185 perf_read_regs(regs);
2187 nmi = perf_intr_is_nmi(regs);
2193 /* Read all the PMCs since we'll need them a bunch of times */
2194 for (i = 0; i < ppmu->n_counter; ++i)
2195 val[i] = read_pmc(i + 1);
2197 /* Try to find what caused the IRQ */
2199 for (i = 0; i < ppmu->n_counter; ++i) {
2200 if (!pmc_overflow(val[i]))
2202 if (is_limited_pmc(i + 1))
2203 continue; /* these won't generate IRQs */
2205 * We've found one that's overflowed. For active
2206 * counters we need to log this. For inactive
2207 * counters, we need to reset it anyway
2211 for (j = 0; j < cpuhw->n_events; ++j) {
2212 event = cpuhw->event[j];
2213 if (event->hw.idx == (i + 1)) {
2215 record_and_restart(event, val[i], regs);
2220 /* reset non active counters that have overflowed */
2221 write_pmc(i + 1, 0);
2223 if (!found && pvr_version_is(PVR_POWER7)) {
2224 /* check active counters for special buggy p7 overflow */
2225 for (i = 0; i < cpuhw->n_events; ++i) {
2226 event = cpuhw->event[i];
2227 if (!event->hw.idx || is_limited_pmc(event->hw.idx))
2229 if (pmc_overflow_power7(val[event->hw.idx - 1])) {
2230 /* event has overflowed in a buggy way*/
2232 record_and_restart(event,
2233 val[event->hw.idx - 1],
2238 if (!found && !nmi && printk_ratelimit())
2239 printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
2242 * Reset MMCR0 to its normal value. This will set PMXE and
2243 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
2244 * and thus allow interrupts to occur again.
2245 * XXX might want to use MSR.PM to keep the events frozen until
2246 * we get back out of this interrupt.
2248 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
2256 static void perf_event_interrupt(struct pt_regs *regs)
2258 u64 start_clock = sched_clock();
2260 __perf_event_interrupt(regs);
2261 perf_sample_event_took(sched_clock() - start_clock);
2264 static int power_pmu_prepare_cpu(unsigned int cpu)
2266 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
2269 memset(cpuhw, 0, sizeof(*cpuhw));
2270 cpuhw->mmcr[0] = MMCR0_FC;
2275 int register_power_pmu(struct power_pmu *pmu)
2278 return -EBUSY; /* something's already registered */
2281 pr_info("%s performance monitor hardware support registered\n",
2284 power_pmu.attr_groups = ppmu->attr_groups;
2288 * Use FCHV to ignore kernel events if MSR.HV is set.
2290 if (mfmsr() & MSR_HV)
2291 freeze_events_kernel = MMCR0_FCHV;
2292 #endif /* CONFIG_PPC64 */
2294 perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW);
2295 cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare",
2296 power_pmu_prepare_cpu, NULL);
2301 static int __init init_ppc64_pmu(void)
2303 /* run through all the pmu drivers one at a time */
2304 if (!init_power5_pmu())
2306 else if (!init_power5p_pmu())
2308 else if (!init_power6_pmu())
2310 else if (!init_power7_pmu())
2312 else if (!init_power8_pmu())
2314 else if (!init_power9_pmu())
2316 else if (!init_ppc970_pmu())
2319 return init_generic_compat_pmu();
2321 early_initcall(init_ppc64_pmu);