1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Performance event support - powerpc architecture code
5 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/perf_event.h>
11 #include <linux/percpu.h>
12 #include <linux/hardirq.h>
13 #include <linux/uaccess.h>
16 #include <asm/machdep.h>
17 #include <asm/firmware.h>
18 #include <asm/ptrace.h>
19 #include <asm/code-patching.h>
20 #include <asm/interrupt.h>
26 #define BHRB_MAX_ENTRIES 32
27 #define BHRB_TARGET 0x0000000000000002
28 #define BHRB_PREDICTION 0x0000000000000001
29 #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL
31 struct cpu_hw_events {
38 struct perf_event *event[MAX_HWEVENTS];
39 u64 events[MAX_HWEVENTS];
40 unsigned int flags[MAX_HWEVENTS];
41 struct mmcr_regs mmcr;
42 struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
43 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
44 u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
45 unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
46 unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
48 unsigned int txn_flags;
52 u64 bhrb_filter; /* BHRB HW branch filter */
53 unsigned int bhrb_users;
55 struct perf_branch_stack bhrb_stack;
56 struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES];
59 /* Store the PMC values */
60 unsigned long pmcs[MAX_HWEVENTS];
63 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
65 static struct power_pmu *ppmu;
68 * Normally, to ignore kernel events we set the FCS (freeze counters
69 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
70 * hypervisor bit set in the MSR, or if we are running on a processor
71 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
72 * then we need to use the FCHV bit to ignore kernel events.
74 static unsigned int freeze_events_kernel = MMCR0_FCS;
77 * 32-bit doesn't have MMCRA but does have an MMCR2,
78 * and a few other names are different.
79 * Also 32-bit doesn't have MMCR3, SIER2 and SIER3.
80 * Define them as zero knowing that any code path accessing
81 * these registers (via mtspr/mfspr) are done under ppmu flag
82 * check for PPMU_ARCH_31 and we will not enter that code path
88 #define MMCR0_PMCjCE MMCR0_PMCnCE
94 #define MMCR0_PMCC_U6 0
96 #define SPRN_MMCRA SPRN_MMCR2
100 #define MMCRA_SAMPLE_ENABLE 0
101 #define MMCRA_BHRB_DISABLE 0
102 #define MMCR0_PMCCEXT 0
104 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
108 static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp) { }
109 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
113 static inline void perf_read_regs(struct pt_regs *regs)
118 static inline int siar_valid(struct pt_regs *regs)
123 static bool is_ebb_event(struct perf_event *event) { return false; }
124 static int ebb_event_check(struct perf_event *event) { return 0; }
125 static void ebb_event_add(struct perf_event *event) { }
126 static void ebb_switch_out(unsigned long mmcr0) { }
127 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
129 return cpuhw->mmcr.mmcr0;
132 static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
133 static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
134 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {}
135 static inline void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw) {}
136 static void pmao_restore_workaround(bool ebb) { }
137 #endif /* CONFIG_PPC32 */
139 bool is_sier_available(void)
144 if (ppmu->flags & PPMU_HAS_SIER)
151 * Return PMC value corresponding to the
154 unsigned long get_pmcs_ext_regs(int idx)
156 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
158 return cpuhw->pmcs[idx];
161 static bool regs_use_siar(struct pt_regs *regs)
164 * When we take a performance monitor exception the regs are setup
165 * using perf_read_regs() which overloads some fields, in particular
166 * regs->result to tell us whether to use SIAR.
168 * However if the regs are from another exception, eg. a syscall, then
169 * they have not been setup using perf_read_regs() and so regs->result
170 * is something random.
172 return ((TRAP(regs) == INTERRUPT_PERFMON) && regs->result);
176 * Things that are specific to 64-bit implementations.
180 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
182 unsigned long mmcra = regs->dsisr;
184 if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) {
185 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
187 return 4 * (slot - 1);
194 * The user wants a data address recorded.
195 * If we're not doing instruction sampling, give them the SDAR
196 * (sampled data address). If we are doing instruction sampling, then
197 * only give them the SDAR if it corresponds to the instruction
198 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the
199 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER.
201 static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp)
203 unsigned long mmcra = regs->dsisr;
206 if (ppmu->flags & PPMU_HAS_SIER)
207 sdar_valid = regs->dar & SIER_SDAR_VALID;
209 unsigned long sdsync;
211 if (ppmu->flags & PPMU_SIAR_VALID)
212 sdsync = POWER7P_MMCRA_SDAR_VALID;
213 else if (ppmu->flags & PPMU_ALT_SIPR)
214 sdsync = POWER6_MMCRA_SDSYNC;
215 else if (ppmu->flags & PPMU_NO_SIAR)
216 sdsync = MMCRA_SAMPLE_ENABLE;
218 sdsync = MMCRA_SDSYNC;
220 sdar_valid = mmcra & sdsync;
223 if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid)
224 *addrp = mfspr(SPRN_SDAR);
226 if (is_kernel_addr(mfspr(SPRN_SDAR)) && event->attr.exclude_kernel)
230 static bool regs_sihv(struct pt_regs *regs)
232 unsigned long sihv = MMCRA_SIHV;
234 if (ppmu->flags & PPMU_HAS_SIER)
235 return !!(regs->dar & SIER_SIHV);
237 if (ppmu->flags & PPMU_ALT_SIPR)
238 sihv = POWER6_MMCRA_SIHV;
240 return !!(regs->dsisr & sihv);
243 static bool regs_sipr(struct pt_regs *regs)
245 unsigned long sipr = MMCRA_SIPR;
247 if (ppmu->flags & PPMU_HAS_SIER)
248 return !!(regs->dar & SIER_SIPR);
250 if (ppmu->flags & PPMU_ALT_SIPR)
251 sipr = POWER6_MMCRA_SIPR;
253 return !!(regs->dsisr & sipr);
256 static inline u32 perf_flags_from_msr(struct pt_regs *regs)
258 if (regs->msr & MSR_PR)
259 return PERF_RECORD_MISC_USER;
260 if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV)
261 return PERF_RECORD_MISC_HYPERVISOR;
262 return PERF_RECORD_MISC_KERNEL;
265 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
267 bool use_siar = regs_use_siar(regs);
268 unsigned long mmcra = regs->dsisr;
269 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
272 return perf_flags_from_msr(regs);
275 * Check the address in SIAR to identify the
276 * privilege levels since the SIER[MSR_HV, MSR_PR]
277 * bits are not set for marked events in power10
280 if (marked && (ppmu->flags & PPMU_P10_DD1)) {
281 unsigned long siar = mfspr(SPRN_SIAR);
283 if (is_kernel_addr(siar))
284 return PERF_RECORD_MISC_KERNEL;
285 return PERF_RECORD_MISC_USER;
287 if (is_kernel_addr(regs->nip))
288 return PERF_RECORD_MISC_KERNEL;
289 return PERF_RECORD_MISC_USER;
294 * If we don't have flags in MMCRA, rather than using
295 * the MSR, we intuit the flags from the address in
296 * SIAR which should give slightly more reliable
299 if (ppmu->flags & PPMU_NO_SIPR) {
300 unsigned long siar = mfspr(SPRN_SIAR);
301 if (is_kernel_addr(siar))
302 return PERF_RECORD_MISC_KERNEL;
303 return PERF_RECORD_MISC_USER;
306 /* PR has priority over HV, so order below is important */
308 return PERF_RECORD_MISC_USER;
310 if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV))
311 return PERF_RECORD_MISC_HYPERVISOR;
313 return PERF_RECORD_MISC_KERNEL;
317 * Overload regs->dsisr to store MMCRA so we only need to read it once
319 * Overload regs->dar to store SIER if we have it.
320 * Overload regs->result to specify whether we should use the MSR (result
321 * is zero) or the SIAR (result is non zero).
323 static inline void perf_read_regs(struct pt_regs *regs)
325 unsigned long mmcra = mfspr(SPRN_MMCRA);
326 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
331 if (ppmu->flags & PPMU_HAS_SIER)
332 regs->dar = mfspr(SPRN_SIER);
335 * If this isn't a PMU exception (eg a software event) the SIAR is
336 * not valid. Use pt_regs.
338 * If it is a marked event use the SIAR.
340 * If the PMU doesn't update the SIAR for non marked events use
343 * If regs is a kernel interrupt, always use SIAR. Some PMUs have an
344 * issue with regs_sipr not being in synch with SIAR in interrupt entry
345 * and return sequences, which can result in regs_sipr being true for
346 * kernel interrupts and SIAR, which has the effect of causing samples
347 * to pile up at mtmsrd MSR[EE] 0->1 or pending irq replay around
348 * interrupt entry/exit.
350 * If the PMU has HV/PR flags then check to see if they
351 * place the exception in userspace. If so, use pt_regs. In
352 * continuous sampling mode the SIAR and the PMU exception are
353 * not synchronised, so they may be many instructions apart.
354 * This can result in confusing backtraces. We still want
355 * hypervisor samples as well as samples in the kernel with
356 * interrupts off hence the userspace check.
358 if (TRAP(regs) != INTERRUPT_PERFMON)
360 else if ((ppmu->flags & PPMU_NO_SIAR))
364 else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))
366 else if (!user_mode(regs))
368 else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs))
373 regs->result = use_siar;
377 * On processors like P7+ that have the SIAR-Valid bit, marked instructions
378 * must be sampled only if the SIAR-valid bit is set.
380 * For unmarked instructions and for processors that don't have the SIAR-Valid
381 * bit, assume that SIAR is valid.
383 static inline int siar_valid(struct pt_regs *regs)
385 unsigned long mmcra = regs->dsisr;
386 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
390 * SIER[SIAR_VALID] is not set for some
391 * marked events on power10 DD1, so drop
392 * the check for SIER[SIAR_VALID] and return true.
394 if (ppmu->flags & PPMU_P10_DD1)
396 else if (ppmu->flags & PPMU_HAS_SIER)
397 return regs->dar & SIER_SIAR_VALID;
399 if (ppmu->flags & PPMU_SIAR_VALID)
400 return mmcra & POWER7P_MMCRA_SIAR_VALID;
407 /* Reset all possible BHRB entries */
408 static void power_pmu_bhrb_reset(void)
410 asm volatile(PPC_CLRBHRB);
413 static void power_pmu_bhrb_enable(struct perf_event *event)
415 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
420 /* Clear BHRB if we changed task context to avoid data leaks */
421 if (event->ctx->task && cpuhw->bhrb_context != event->ctx) {
422 power_pmu_bhrb_reset();
423 cpuhw->bhrb_context = event->ctx;
426 perf_sched_cb_inc(event->ctx->pmu);
429 static void power_pmu_bhrb_disable(struct perf_event *event)
431 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
436 WARN_ON_ONCE(!cpuhw->bhrb_users);
438 perf_sched_cb_dec(event->ctx->pmu);
440 if (!cpuhw->disabled && !cpuhw->bhrb_users) {
441 /* BHRB cannot be turned off when other
442 * events are active on the PMU.
445 /* avoid stale pointer */
446 cpuhw->bhrb_context = NULL;
450 /* Called from ctxsw to prevent one process's branch entries to
451 * mingle with the other process's entries during context switch.
453 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
459 power_pmu_bhrb_reset();
461 /* Calculate the to address for a branch */
462 static __u64 power_pmu_bhrb_to(u64 addr)
467 if (is_kernel_addr(addr)) {
468 if (copy_from_kernel_nofault(&instr, (void *)addr,
472 return branch_target(&instr);
475 /* Userspace: need copy instruction here then translate it */
476 if (copy_from_user_nofault(&instr, (unsigned int __user *)addr,
480 target = branch_target(&instr);
481 if ((!target) || (instr & BRANCH_ABSOLUTE))
484 /* Translate relative branch target from kernel to user address */
485 return target - (unsigned long)&instr + addr;
488 /* Processing BHRB entries */
489 static void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw)
493 int r_index, u_index, pred;
497 while (r_index < ppmu->bhrb_nr) {
498 /* Assembly read function */
499 val = read_bhrb(r_index++);
501 /* Terminal marker: End of valid BHRB entries */
504 addr = val & BHRB_EA;
505 pred = val & BHRB_PREDICTION;
512 * BHRB rolling buffer could very much contain the kernel
513 * addresses at this point. Check the privileges before
514 * exporting it to userspace (avoid exposure of regions
515 * where we could have speculative execution)
516 * Incase of ISA v3.1, BHRB will capture only user-space
517 * addresses, hence include a check before filtering code
519 if (!(ppmu->flags & PPMU_ARCH_31) &&
520 is_kernel_addr(addr) && event->attr.exclude_kernel)
523 /* Branches are read most recent first (ie. mfbhrb 0 is
524 * the most recent branch).
525 * There are two types of valid entries:
526 * 1) a target entry which is the to address of a
527 * computed goto like a blr,bctr,btar. The next
528 * entry read from the bhrb will be branch
529 * corresponding to this target (ie. the actual
530 * blr/bctr/btar instruction).
531 * 2) a from address which is an actual branch. If a
532 * target entry proceeds this, then this is the
533 * matching branch for that target. If this is not
534 * following a target entry, then this is a branch
535 * where the target is given as an immediate field
536 * in the instruction (ie. an i or b form branch).
537 * In this case we need to read the instruction from
538 * memory to determine the target/to address.
541 if (val & BHRB_TARGET) {
542 /* Target branches use two entries
543 * (ie. computed gotos/XL form)
545 cpuhw->bhrb_entries[u_index].to = addr;
546 cpuhw->bhrb_entries[u_index].mispred = pred;
547 cpuhw->bhrb_entries[u_index].predicted = ~pred;
549 /* Get from address in next entry */
550 val = read_bhrb(r_index++);
551 addr = val & BHRB_EA;
552 if (val & BHRB_TARGET) {
553 /* Shouldn't have two targets in a
554 row.. Reset index and try again */
558 cpuhw->bhrb_entries[u_index].from = addr;
560 /* Branches to immediate field
562 cpuhw->bhrb_entries[u_index].from = addr;
563 cpuhw->bhrb_entries[u_index].to =
564 power_pmu_bhrb_to(addr);
565 cpuhw->bhrb_entries[u_index].mispred = pred;
566 cpuhw->bhrb_entries[u_index].predicted = ~pred;
572 cpuhw->bhrb_stack.nr = u_index;
573 cpuhw->bhrb_stack.hw_idx = -1ULL;
577 static bool is_ebb_event(struct perf_event *event)
580 * This could be a per-PMU callback, but we'd rather avoid the cost. We
581 * check that the PMU supports EBB, meaning those that don't can still
582 * use bit 63 of the event code for something else if they wish.
584 return (ppmu->flags & PPMU_ARCH_207S) &&
585 ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1);
588 static int ebb_event_check(struct perf_event *event)
590 struct perf_event *leader = event->group_leader;
592 /* Event and group leader must agree on EBB */
593 if (is_ebb_event(leader) != is_ebb_event(event))
596 if (is_ebb_event(event)) {
597 if (!(event->attach_state & PERF_ATTACH_TASK))
600 if (!leader->attr.pinned || !leader->attr.exclusive)
603 if (event->attr.freq ||
604 event->attr.inherit ||
605 event->attr.sample_type ||
606 event->attr.sample_period ||
607 event->attr.enable_on_exec)
614 static void ebb_event_add(struct perf_event *event)
616 if (!is_ebb_event(event) || current->thread.used_ebb)
620 * IFF this is the first time we've added an EBB event, set
621 * PMXE in the user MMCR0 so we can detect when it's cleared by
622 * userspace. We need this so that we can context switch while
623 * userspace is in the EBB handler (where PMXE is 0).
625 current->thread.used_ebb = 1;
626 current->thread.mmcr0 |= MMCR0_PMXE;
629 static void ebb_switch_out(unsigned long mmcr0)
631 if (!(mmcr0 & MMCR0_EBE))
634 current->thread.siar = mfspr(SPRN_SIAR);
635 current->thread.sier = mfspr(SPRN_SIER);
636 current->thread.sdar = mfspr(SPRN_SDAR);
637 current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;
638 current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
639 if (ppmu->flags & PPMU_ARCH_31) {
640 current->thread.mmcr3 = mfspr(SPRN_MMCR3);
641 current->thread.sier2 = mfspr(SPRN_SIER2);
642 current->thread.sier3 = mfspr(SPRN_SIER3);
646 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
648 unsigned long mmcr0 = cpuhw->mmcr.mmcr0;
653 /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */
654 mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6;
657 * Add any bits from the user MMCR0, FC or PMAO. This is compatible
658 * with pmao_restore_workaround() because we may add PMAO but we never
661 mmcr0 |= current->thread.mmcr0;
664 * Be careful not to set PMXE if userspace had it cleared. This is also
665 * compatible with pmao_restore_workaround() because it has already
666 * cleared PMXE and we leave PMAO alone.
668 if (!(current->thread.mmcr0 & MMCR0_PMXE))
669 mmcr0 &= ~MMCR0_PMXE;
671 mtspr(SPRN_SIAR, current->thread.siar);
672 mtspr(SPRN_SIER, current->thread.sier);
673 mtspr(SPRN_SDAR, current->thread.sdar);
676 * Merge the kernel & user values of MMCR2. The semantics we implement
677 * are that the user MMCR2 can set bits, ie. cause counters to freeze,
678 * but not clear bits. If a task wants to be able to clear bits, ie.
679 * unfreeze counters, it should not set exclude_xxx in its events and
680 * instead manage the MMCR2 entirely by itself.
682 mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2 | current->thread.mmcr2);
684 if (ppmu->flags & PPMU_ARCH_31) {
685 mtspr(SPRN_MMCR3, current->thread.mmcr3);
686 mtspr(SPRN_SIER2, current->thread.sier2);
687 mtspr(SPRN_SIER3, current->thread.sier3);
693 static void pmao_restore_workaround(bool ebb)
697 if (!cpu_has_feature(CPU_FTR_PMAO_BUG))
701 * On POWER8E there is a hardware defect which affects the PMU context
702 * switch logic, ie. power_pmu_disable/enable().
704 * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0
705 * by the hardware. Sometime later the actual PMU exception is
708 * If we context switch, or simply disable/enable, the PMU prior to the
709 * exception arriving, the exception will be lost when we clear PMAO.
711 * When we reenable the PMU, we will write the saved MMCR0 with PMAO
712 * set, and this _should_ generate an exception. However because of the
713 * defect no exception is generated when we write PMAO, and we get
714 * stuck with no counters counting but no exception delivered.
716 * The workaround is to detect this case and tweak the hardware to
717 * create another pending PMU exception.
719 * We do that by setting up PMC6 (cycles) for an imminent overflow and
720 * enabling the PMU. That causes a new exception to be generated in the
721 * chip, but we don't take it yet because we have interrupts hard
722 * disabled. We then write back the PMU state as we want it to be seen
723 * by the exception handler. When we reenable interrupts the exception
724 * handler will be called and see the correct state.
726 * The logic is the same for EBB, except that the exception is gated by
727 * us having interrupts hard disabled as well as the fact that we are
728 * not in userspace. The exception is finally delivered when we return
732 /* Only if PMAO is set and PMAO_SYNC is clear */
733 if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO)
736 /* If we're doing EBB, only if BESCR[GE] is set */
737 if (ebb && !(current->thread.bescr & BESCR_GE))
741 * We are already soft-disabled in power_pmu_enable(). We need to hard
742 * disable to actually prevent the PMU exception from firing.
747 * This is a bit gross, but we know we're on POWER8E and have 6 PMCs.
748 * Using read/write_pmc() in a for loop adds 12 function calls and
749 * almost doubles our code size.
751 pmcs[0] = mfspr(SPRN_PMC1);
752 pmcs[1] = mfspr(SPRN_PMC2);
753 pmcs[2] = mfspr(SPRN_PMC3);
754 pmcs[3] = mfspr(SPRN_PMC4);
755 pmcs[4] = mfspr(SPRN_PMC5);
756 pmcs[5] = mfspr(SPRN_PMC6);
758 /* Ensure all freeze bits are unset */
759 mtspr(SPRN_MMCR2, 0);
761 /* Set up PMC6 to overflow in one cycle */
762 mtspr(SPRN_PMC6, 0x7FFFFFFE);
764 /* Enable exceptions and unfreeze PMC6 */
765 mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO);
767 /* Now we need to refreeze and restore the PMCs */
768 mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO);
770 mtspr(SPRN_PMC1, pmcs[0]);
771 mtspr(SPRN_PMC2, pmcs[1]);
772 mtspr(SPRN_PMC3, pmcs[2]);
773 mtspr(SPRN_PMC4, pmcs[3]);
774 mtspr(SPRN_PMC5, pmcs[4]);
775 mtspr(SPRN_PMC6, pmcs[5]);
778 #endif /* CONFIG_PPC64 */
780 static void perf_event_interrupt(struct pt_regs *regs);
783 * Read one performance monitor counter (PMC).
785 static unsigned long read_pmc(int idx)
791 val = mfspr(SPRN_PMC1);
794 val = mfspr(SPRN_PMC2);
797 val = mfspr(SPRN_PMC3);
800 val = mfspr(SPRN_PMC4);
803 val = mfspr(SPRN_PMC5);
806 val = mfspr(SPRN_PMC6);
810 val = mfspr(SPRN_PMC7);
813 val = mfspr(SPRN_PMC8);
815 #endif /* CONFIG_PPC64 */
817 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
826 static void write_pmc(int idx, unsigned long val)
830 mtspr(SPRN_PMC1, val);
833 mtspr(SPRN_PMC2, val);
836 mtspr(SPRN_PMC3, val);
839 mtspr(SPRN_PMC4, val);
842 mtspr(SPRN_PMC5, val);
845 mtspr(SPRN_PMC6, val);
849 mtspr(SPRN_PMC7, val);
852 mtspr(SPRN_PMC8, val);
854 #endif /* CONFIG_PPC64 */
856 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
860 /* Called from sysrq_handle_showregs() */
861 void perf_event_print_debug(void)
863 unsigned long sdar, sier, flags;
864 u32 pmcs[MAX_HWEVENTS];
868 pr_info("Performance monitor hardware not registered.\n");
872 if (!ppmu->n_counter)
875 local_irq_save(flags);
877 pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d",
878 smp_processor_id(), ppmu->name, ppmu->n_counter);
880 for (i = 0; i < ppmu->n_counter; i++)
881 pmcs[i] = read_pmc(i + 1);
883 for (; i < MAX_HWEVENTS; i++)
884 pmcs[i] = 0xdeadbeef;
886 pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n",
887 pmcs[0], pmcs[1], pmcs[2], pmcs[3]);
889 if (ppmu->n_counter > 4)
890 pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n",
891 pmcs[4], pmcs[5], pmcs[6], pmcs[7]);
893 pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n",
894 mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA));
898 sdar = mfspr(SPRN_SDAR);
900 if (ppmu->flags & PPMU_HAS_SIER)
901 sier = mfspr(SPRN_SIER);
903 if (ppmu->flags & PPMU_ARCH_207S) {
904 pr_info("MMCR2: %016lx EBBHR: %016lx\n",
905 mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR));
906 pr_info("EBBRR: %016lx BESCR: %016lx\n",
907 mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR));
910 if (ppmu->flags & PPMU_ARCH_31) {
911 pr_info("MMCR3: %016lx SIER2: %016lx SIER3: %016lx\n",
912 mfspr(SPRN_MMCR3), mfspr(SPRN_SIER2), mfspr(SPRN_SIER3));
915 pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n",
916 mfspr(SPRN_SIAR), sdar, sier);
918 local_irq_restore(flags);
922 * Check if a set of events can all go on the PMU at once.
923 * If they can't, this will look at alternative codes for the events
924 * and see if any combination of alternative codes is feasible.
925 * The feasible set is returned in event_id[].
927 static int power_check_constraints(struct cpu_hw_events *cpuhw,
928 u64 event_id[], unsigned int cflags[],
929 int n_ev, struct perf_event **event)
931 unsigned long mask, value, nv;
932 unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS];
933 int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS];
935 unsigned long addf = ppmu->add_fields;
936 unsigned long tadd = ppmu->test_adder;
937 unsigned long grp_mask = ppmu->group_constraint_mask;
938 unsigned long grp_val = ppmu->group_constraint_val;
940 if (n_ev > ppmu->n_counter)
943 /* First see if the events will go on as-is */
944 for (i = 0; i < n_ev; ++i) {
945 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
946 && !ppmu->limited_pmc_event(event_id[i])) {
947 ppmu->get_alternatives(event_id[i], cflags[i],
948 cpuhw->alternatives[i]);
949 event_id[i] = cpuhw->alternatives[i][0];
951 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
952 &cpuhw->avalues[i][0], event[i]->attr.config1))
956 for (i = 0; i < n_ev; ++i) {
957 nv = (value | cpuhw->avalues[i][0]) +
958 (value & cpuhw->avalues[i][0] & addf);
960 if (((((nv + tadd) ^ value) & mask) & (~grp_mask)) != 0)
963 if (((((nv + tadd) ^ cpuhw->avalues[i][0]) & cpuhw->amasks[i][0])
968 mask |= cpuhw->amasks[i][0];
971 if ((value & mask & grp_mask) != (mask & grp_val))
974 return 0; /* all OK */
977 /* doesn't work, gather alternatives... */
978 if (!ppmu->get_alternatives)
980 for (i = 0; i < n_ev; ++i) {
982 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i],
983 cpuhw->alternatives[i]);
984 for (j = 1; j < n_alt[i]; ++j)
985 ppmu->get_constraint(cpuhw->alternatives[i][j],
986 &cpuhw->amasks[i][j],
987 &cpuhw->avalues[i][j],
988 event[i]->attr.config1);
991 /* enumerate all possibilities and see if any will work */
994 value = mask = nv = 0;
997 /* we're backtracking, restore context */
1003 * See if any alternative k for event_id i,
1004 * where k > j, will satisfy the constraints.
1006 while (++j < n_alt[i]) {
1007 nv = (value | cpuhw->avalues[i][j]) +
1008 (value & cpuhw->avalues[i][j] & addf);
1009 if ((((nv + tadd) ^ value) & mask) == 0 &&
1010 (((nv + tadd) ^ cpuhw->avalues[i][j])
1011 & cpuhw->amasks[i][j]) == 0)
1014 if (j >= n_alt[i]) {
1016 * No feasible alternative, backtrack
1017 * to event_id i-1 and continue enumerating its
1018 * alternatives from where we got up to.
1024 * Found a feasible alternative for event_id i,
1025 * remember where we got up to with this event_id,
1026 * go on to the next event_id, and start with
1027 * the first alternative for it.
1033 mask |= cpuhw->amasks[i][j];
1039 /* OK, we have a feasible combination, tell the caller the solution */
1040 for (i = 0; i < n_ev; ++i)
1041 event_id[i] = cpuhw->alternatives[i][choice[i]];
1046 * Check if newly-added events have consistent settings for
1047 * exclude_{user,kernel,hv} with each other and any previously
1050 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
1051 int n_prev, int n_new)
1053 int eu = 0, ek = 0, eh = 0;
1055 struct perf_event *event;
1058 * If the PMU we're on supports per event exclude settings then we
1059 * don't need to do any of this logic. NB. This assumes no PMU has both
1060 * per event exclude and limited PMCs.
1062 if (ppmu->flags & PPMU_ARCH_207S)
1070 for (i = 0; i < n; ++i) {
1071 if (cflags[i] & PPMU_LIMITED_PMC_OK) {
1072 cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
1077 eu = event->attr.exclude_user;
1078 ek = event->attr.exclude_kernel;
1079 eh = event->attr.exclude_hv;
1081 } else if (event->attr.exclude_user != eu ||
1082 event->attr.exclude_kernel != ek ||
1083 event->attr.exclude_hv != eh) {
1089 for (i = 0; i < n; ++i)
1090 if (cflags[i] & PPMU_LIMITED_PMC_OK)
1091 cflags[i] |= PPMU_LIMITED_PMC_REQD;
1096 static u64 check_and_compute_delta(u64 prev, u64 val)
1098 u64 delta = (val - prev) & 0xfffffffful;
1101 * POWER7 can roll back counter values, if the new value is smaller
1102 * than the previous value it will cause the delta and the counter to
1103 * have bogus values unless we rolled a counter over. If a coutner is
1104 * rolled back, it will be smaller, but within 256, which is the maximum
1105 * number of events to rollback at once. If we detect a rollback
1106 * return 0. This can lead to a small lack of precision in the
1109 if (prev > val && (prev - val) < 256)
1115 static void power_pmu_read(struct perf_event *event)
1117 s64 val, delta, prev;
1119 if (event->hw.state & PERF_HES_STOPPED)
1125 if (is_ebb_event(event)) {
1126 val = read_pmc(event->hw.idx);
1127 local64_set(&event->hw.prev_count, val);
1132 * Performance monitor interrupts come even when interrupts
1133 * are soft-disabled, as long as interrupts are hard-enabled.
1134 * Therefore we treat them like NMIs.
1137 prev = local64_read(&event->hw.prev_count);
1139 val = read_pmc(event->hw.idx);
1140 delta = check_and_compute_delta(prev, val);
1143 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
1145 local64_add(delta, &event->count);
1148 * A number of places program the PMC with (0x80000000 - period_left).
1149 * We never want period_left to be less than 1 because we will program
1150 * the PMC with a value >= 0x800000000 and an edge detected PMC will
1151 * roll around to 0 before taking an exception. We have seen this
1154 * To fix this, clamp the minimum value of period_left to 1.
1157 prev = local64_read(&event->hw.period_left);
1161 } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev);
1165 * On some machines, PMC5 and PMC6 can't be written, don't respect
1166 * the freeze conditions, and don't generate interrupts. This tells
1167 * us if `event' is using such a PMC.
1169 static int is_limited_pmc(int pmcnum)
1171 return (ppmu->flags & PPMU_LIMITED_PMC5_6)
1172 && (pmcnum == 5 || pmcnum == 6);
1175 static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
1176 unsigned long pmc5, unsigned long pmc6)
1178 struct perf_event *event;
1179 u64 val, prev, delta;
1182 for (i = 0; i < cpuhw->n_limited; ++i) {
1183 event = cpuhw->limited_counter[i];
1186 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1187 prev = local64_read(&event->hw.prev_count);
1189 delta = check_and_compute_delta(prev, val);
1191 local64_add(delta, &event->count);
1195 static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
1196 unsigned long pmc5, unsigned long pmc6)
1198 struct perf_event *event;
1202 for (i = 0; i < cpuhw->n_limited; ++i) {
1203 event = cpuhw->limited_counter[i];
1204 event->hw.idx = cpuhw->limited_hwidx[i];
1205 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1206 prev = local64_read(&event->hw.prev_count);
1207 if (check_and_compute_delta(prev, val))
1208 local64_set(&event->hw.prev_count, val);
1209 perf_event_update_userpage(event);
1214 * Since limited events don't respect the freeze conditions, we
1215 * have to read them immediately after freezing or unfreezing the
1216 * other events. We try to keep the values from the limited
1217 * events as consistent as possible by keeping the delay (in
1218 * cycles and instructions) between freezing/unfreezing and reading
1219 * the limited events as small and consistent as possible.
1220 * Therefore, if any limited events are in use, we read them
1221 * both, and always in the same order, to minimize variability,
1222 * and do it inside the same asm that writes MMCR0.
1224 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
1226 unsigned long pmc5, pmc6;
1228 if (!cpuhw->n_limited) {
1229 mtspr(SPRN_MMCR0, mmcr0);
1234 * Write MMCR0, then read PMC5 and PMC6 immediately.
1235 * To ensure we don't get a performance monitor interrupt
1236 * between writing MMCR0 and freezing/thawing the limited
1237 * events, we first write MMCR0 with the event overflow
1238 * interrupt enable bits turned off.
1240 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
1241 : "=&r" (pmc5), "=&r" (pmc6)
1242 : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
1244 "i" (SPRN_PMC5), "i" (SPRN_PMC6));
1246 if (mmcr0 & MMCR0_FC)
1247 freeze_limited_counters(cpuhw, pmc5, pmc6);
1249 thaw_limited_counters(cpuhw, pmc5, pmc6);
1252 * Write the full MMCR0 including the event overflow interrupt
1253 * enable bits, if necessary.
1255 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
1256 mtspr(SPRN_MMCR0, mmcr0);
1260 * Disable all events to prevent PMU interrupts and to allow
1261 * events to be added or removed.
1263 static void power_pmu_disable(struct pmu *pmu)
1265 struct cpu_hw_events *cpuhw;
1266 unsigned long flags, mmcr0, val, mmcra;
1270 local_irq_save(flags);
1271 cpuhw = this_cpu_ptr(&cpu_hw_events);
1273 if (!cpuhw->disabled) {
1275 * Check if we ever enabled the PMU on this cpu.
1277 if (!cpuhw->pmcs_enabled) {
1279 cpuhw->pmcs_enabled = 1;
1283 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56
1285 val = mmcr0 = mfspr(SPRN_MMCR0);
1287 val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
1289 /* Set mmcr0 PMCCEXT for p10 */
1290 if (ppmu->flags & PPMU_ARCH_31)
1291 val |= MMCR0_PMCCEXT;
1294 * The barrier is to make sure the mtspr has been
1295 * executed and the PMU has frozen the events etc.
1298 write_mmcr0(cpuhw, val);
1302 val = mmcra = cpuhw->mmcr.mmcra;
1305 * Disable instruction sampling if it was enabled
1307 if (cpuhw->mmcr.mmcra & MMCRA_SAMPLE_ENABLE)
1308 val &= ~MMCRA_SAMPLE_ENABLE;
1310 /* Disable BHRB via mmcra (BHRBRD) for p10 */
1311 if (ppmu->flags & PPMU_ARCH_31)
1312 val |= MMCRA_BHRB_DISABLE;
1315 * Write SPRN_MMCRA if mmcra has either disabled
1316 * instruction sampling or BHRB.
1319 mtspr(SPRN_MMCRA, mmcra);
1324 cpuhw->disabled = 1;
1327 ebb_switch_out(mmcr0);
1331 * These are readable by userspace, may contain kernel
1332 * addresses and are not switched by context switch, so clear
1333 * them now to avoid leaking anything to userspace in general
1334 * including to another process.
1336 if (ppmu->flags & PPMU_ARCH_207S) {
1337 mtspr(SPRN_SDAR, 0);
1338 mtspr(SPRN_SIAR, 0);
1343 local_irq_restore(flags);
1347 * Re-enable all events if disable == 0.
1348 * If we were previously disabled and events were added, then
1349 * put the new config on the PMU.
1351 static void power_pmu_enable(struct pmu *pmu)
1353 struct perf_event *event;
1354 struct cpu_hw_events *cpuhw;
1355 unsigned long flags;
1357 unsigned long val, mmcr0;
1359 unsigned int hwc_index[MAX_HWEVENTS];
1366 local_irq_save(flags);
1368 cpuhw = this_cpu_ptr(&cpu_hw_events);
1369 if (!cpuhw->disabled)
1372 if (cpuhw->n_events == 0) {
1373 ppc_set_pmu_inuse(0);
1377 cpuhw->disabled = 0;
1380 * EBB requires an exclusive group and all events must have the EBB
1381 * flag set, or not set, so we can just check a single event. Also we
1382 * know we have at least one event.
1384 ebb = is_ebb_event(cpuhw->event[0]);
1387 * If we didn't change anything, or only removed events,
1388 * no need to recalculate MMCR* settings and reset the PMCs.
1389 * Just reenable the PMU with the current MMCR* settings
1390 * (possibly updated for removal of events).
1392 if (!cpuhw->n_added) {
1393 mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE);
1394 mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1);
1395 if (ppmu->flags & PPMU_ARCH_31)
1396 mtspr(SPRN_MMCR3, cpuhw->mmcr.mmcr3);
1401 * Clear all MMCR settings and recompute them for the new set of events.
1403 memset(&cpuhw->mmcr, 0, sizeof(cpuhw->mmcr));
1405 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
1406 &cpuhw->mmcr, cpuhw->event, ppmu->flags)) {
1407 /* shouldn't ever get here */
1408 printk(KERN_ERR "oops compute_mmcr failed\n");
1412 if (!(ppmu->flags & PPMU_ARCH_207S)) {
1414 * Add in MMCR0 freeze bits corresponding to the attr.exclude_*
1415 * bits for the first event. We have already checked that all
1416 * events have the same value for these bits as the first event.
1418 event = cpuhw->event[0];
1419 if (event->attr.exclude_user)
1420 cpuhw->mmcr.mmcr0 |= MMCR0_FCP;
1421 if (event->attr.exclude_kernel)
1422 cpuhw->mmcr.mmcr0 |= freeze_events_kernel;
1423 if (event->attr.exclude_hv)
1424 cpuhw->mmcr.mmcr0 |= MMCR0_FCHV;
1428 * Write the new configuration to MMCR* with the freeze
1429 * bit set and set the hardware events to their initial values.
1430 * Then unfreeze the events.
1432 ppc_set_pmu_inuse(1);
1433 mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE);
1434 mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1);
1435 mtspr(SPRN_MMCR0, (cpuhw->mmcr.mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
1437 if (ppmu->flags & PPMU_ARCH_207S)
1438 mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2);
1440 if (ppmu->flags & PPMU_ARCH_31)
1441 mtspr(SPRN_MMCR3, cpuhw->mmcr.mmcr3);
1444 * Read off any pre-existing events that need to move
1447 for (i = 0; i < cpuhw->n_events; ++i) {
1448 event = cpuhw->event[i];
1449 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
1450 power_pmu_read(event);
1451 write_pmc(event->hw.idx, 0);
1457 * Initialize the PMCs for all the new and moved events.
1459 cpuhw->n_limited = n_lim = 0;
1460 for (i = 0; i < cpuhw->n_events; ++i) {
1461 event = cpuhw->event[i];
1464 idx = hwc_index[i] + 1;
1465 if (is_limited_pmc(idx)) {
1466 cpuhw->limited_counter[n_lim] = event;
1467 cpuhw->limited_hwidx[n_lim] = idx;
1473 val = local64_read(&event->hw.prev_count);
1476 if (event->hw.sample_period) {
1477 left = local64_read(&event->hw.period_left);
1478 if (left < 0x80000000L)
1479 val = 0x80000000L - left;
1481 local64_set(&event->hw.prev_count, val);
1484 event->hw.idx = idx;
1485 if (event->hw.state & PERF_HES_STOPPED)
1487 write_pmc(idx, val);
1489 perf_event_update_userpage(event);
1491 cpuhw->n_limited = n_lim;
1492 cpuhw->mmcr.mmcr0 |= MMCR0_PMXE | MMCR0_FCECE;
1495 pmao_restore_workaround(ebb);
1497 mmcr0 = ebb_switch_in(ebb, cpuhw);
1500 if (cpuhw->bhrb_users)
1501 ppmu->config_bhrb(cpuhw->bhrb_filter);
1503 write_mmcr0(cpuhw, mmcr0);
1506 * Enable instruction sampling if necessary
1508 if (cpuhw->mmcr.mmcra & MMCRA_SAMPLE_ENABLE) {
1510 mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra);
1515 local_irq_restore(flags);
1518 static int collect_events(struct perf_event *group, int max_count,
1519 struct perf_event *ctrs[], u64 *events,
1520 unsigned int *flags)
1523 struct perf_event *event;
1525 if (group->pmu->task_ctx_nr == perf_hw_context) {
1529 flags[n] = group->hw.event_base;
1530 events[n++] = group->hw.config;
1532 for_each_sibling_event(event, group) {
1533 if (event->pmu->task_ctx_nr == perf_hw_context &&
1534 event->state != PERF_EVENT_STATE_OFF) {
1538 flags[n] = event->hw.event_base;
1539 events[n++] = event->hw.config;
1546 * Add an event to the PMU.
1547 * If all events are not already frozen, then we disable and
1548 * re-enable the PMU in order to get hw_perf_enable to do the
1549 * actual work of reconfiguring the PMU.
1551 static int power_pmu_add(struct perf_event *event, int ef_flags)
1553 struct cpu_hw_events *cpuhw;
1554 unsigned long flags;
1558 local_irq_save(flags);
1559 perf_pmu_disable(event->pmu);
1562 * Add the event to the list (if there is room)
1563 * and check whether the total set is still feasible.
1565 cpuhw = this_cpu_ptr(&cpu_hw_events);
1566 n0 = cpuhw->n_events;
1567 if (n0 >= ppmu->n_counter)
1569 cpuhw->event[n0] = event;
1570 cpuhw->events[n0] = event->hw.config;
1571 cpuhw->flags[n0] = event->hw.event_base;
1574 * This event may have been disabled/stopped in record_and_restart()
1575 * because we exceeded the ->event_limit. If re-starting the event,
1576 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user
1577 * notification is re-enabled.
1579 if (!(ef_flags & PERF_EF_START))
1580 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
1582 event->hw.state = 0;
1585 * If group events scheduling transaction was started,
1586 * skip the schedulability test here, it will be performed
1587 * at commit time(->commit_txn) as a whole
1589 if (cpuhw->txn_flags & PERF_PMU_TXN_ADD)
1592 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
1594 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1, cpuhw->event))
1596 event->hw.config = cpuhw->events[n0];
1599 ebb_event_add(event);
1606 if (has_branch_stack(event)) {
1607 u64 bhrb_filter = -1;
1609 if (ppmu->bhrb_filter_map)
1610 bhrb_filter = ppmu->bhrb_filter_map(
1611 event->attr.branch_sample_type);
1613 if (bhrb_filter != -1) {
1614 cpuhw->bhrb_filter = bhrb_filter;
1615 power_pmu_bhrb_enable(event);
1619 perf_pmu_enable(event->pmu);
1620 local_irq_restore(flags);
1625 * Remove an event from the PMU.
1627 static void power_pmu_del(struct perf_event *event, int ef_flags)
1629 struct cpu_hw_events *cpuhw;
1631 unsigned long flags;
1633 local_irq_save(flags);
1634 perf_pmu_disable(event->pmu);
1636 power_pmu_read(event);
1638 cpuhw = this_cpu_ptr(&cpu_hw_events);
1639 for (i = 0; i < cpuhw->n_events; ++i) {
1640 if (event == cpuhw->event[i]) {
1641 while (++i < cpuhw->n_events) {
1642 cpuhw->event[i-1] = cpuhw->event[i];
1643 cpuhw->events[i-1] = cpuhw->events[i];
1644 cpuhw->flags[i-1] = cpuhw->flags[i];
1647 ppmu->disable_pmc(event->hw.idx - 1, &cpuhw->mmcr);
1648 if (event->hw.idx) {
1649 write_pmc(event->hw.idx, 0);
1652 perf_event_update_userpage(event);
1656 for (i = 0; i < cpuhw->n_limited; ++i)
1657 if (event == cpuhw->limited_counter[i])
1659 if (i < cpuhw->n_limited) {
1660 while (++i < cpuhw->n_limited) {
1661 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
1662 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
1666 if (cpuhw->n_events == 0) {
1667 /* disable exceptions if no events are running */
1668 cpuhw->mmcr.mmcr0 &= ~(MMCR0_PMXE | MMCR0_FCECE);
1671 if (has_branch_stack(event))
1672 power_pmu_bhrb_disable(event);
1674 perf_pmu_enable(event->pmu);
1675 local_irq_restore(flags);
1679 * POWER-PMU does not support disabling individual counters, hence
1680 * program their cycle counter to their max value and ignore the interrupts.
1683 static void power_pmu_start(struct perf_event *event, int ef_flags)
1685 unsigned long flags;
1689 if (!event->hw.idx || !event->hw.sample_period)
1692 if (!(event->hw.state & PERF_HES_STOPPED))
1695 if (ef_flags & PERF_EF_RELOAD)
1696 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1698 local_irq_save(flags);
1699 perf_pmu_disable(event->pmu);
1701 event->hw.state = 0;
1702 left = local64_read(&event->hw.period_left);
1705 if (left < 0x80000000L)
1706 val = 0x80000000L - left;
1708 write_pmc(event->hw.idx, val);
1710 perf_event_update_userpage(event);
1711 perf_pmu_enable(event->pmu);
1712 local_irq_restore(flags);
1715 static void power_pmu_stop(struct perf_event *event, int ef_flags)
1717 unsigned long flags;
1719 if (!event->hw.idx || !event->hw.sample_period)
1722 if (event->hw.state & PERF_HES_STOPPED)
1725 local_irq_save(flags);
1726 perf_pmu_disable(event->pmu);
1728 power_pmu_read(event);
1729 event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
1730 write_pmc(event->hw.idx, 0);
1732 perf_event_update_userpage(event);
1733 perf_pmu_enable(event->pmu);
1734 local_irq_restore(flags);
1738 * Start group events scheduling transaction
1739 * Set the flag to make pmu::enable() not perform the
1740 * schedulability test, it will be performed at commit time
1742 * We only support PERF_PMU_TXN_ADD transactions. Save the
1743 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1746 static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1748 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1750 WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */
1752 cpuhw->txn_flags = txn_flags;
1753 if (txn_flags & ~PERF_PMU_TXN_ADD)
1756 perf_pmu_disable(pmu);
1757 cpuhw->n_txn_start = cpuhw->n_events;
1761 * Stop group events scheduling transaction
1762 * Clear the flag and pmu::enable() will perform the
1763 * schedulability test.
1765 static void power_pmu_cancel_txn(struct pmu *pmu)
1767 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1768 unsigned int txn_flags;
1770 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1772 txn_flags = cpuhw->txn_flags;
1773 cpuhw->txn_flags = 0;
1774 if (txn_flags & ~PERF_PMU_TXN_ADD)
1777 perf_pmu_enable(pmu);
1781 * Commit group events scheduling transaction
1782 * Perform the group schedulability test as a whole
1783 * Return 0 if success
1785 static int power_pmu_commit_txn(struct pmu *pmu)
1787 struct cpu_hw_events *cpuhw;
1793 cpuhw = this_cpu_ptr(&cpu_hw_events);
1794 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1796 if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) {
1797 cpuhw->txn_flags = 0;
1801 n = cpuhw->n_events;
1802 if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
1804 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n, cpuhw->event);
1808 for (i = cpuhw->n_txn_start; i < n; ++i)
1809 cpuhw->event[i]->hw.config = cpuhw->events[i];
1811 cpuhw->txn_flags = 0;
1812 perf_pmu_enable(pmu);
1817 * Return 1 if we might be able to put event on a limited PMC,
1819 * An event can only go on a limited PMC if it counts something
1820 * that a limited PMC can count, doesn't require interrupts, and
1821 * doesn't exclude any processor mode.
1823 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev,
1827 u64 alt[MAX_EVENT_ALTERNATIVES];
1829 if (event->attr.exclude_user
1830 || event->attr.exclude_kernel
1831 || event->attr.exclude_hv
1832 || event->attr.sample_period)
1835 if (ppmu->limited_pmc_event(ev))
1839 * The requested event_id isn't on a limited PMC already;
1840 * see if any alternative code goes on a limited PMC.
1842 if (!ppmu->get_alternatives)
1845 flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
1846 n = ppmu->get_alternatives(ev, flags, alt);
1852 * Find an alternative event_id that goes on a normal PMC, if possible,
1853 * and return the event_id code, or 0 if there is no such alternative.
1854 * (Note: event_id code 0 is "don't count" on all machines.)
1856 static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
1858 u64 alt[MAX_EVENT_ALTERNATIVES];
1861 flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
1862 n = ppmu->get_alternatives(ev, flags, alt);
1868 /* Number of perf_events counting hardware events */
1869 static atomic_t num_events;
1870 /* Used to avoid races in calling reserve/release_pmc_hardware */
1871 static DEFINE_MUTEX(pmc_reserve_mutex);
1874 * Release the PMU if this is the last perf_event.
1876 static void hw_perf_event_destroy(struct perf_event *event)
1878 if (!atomic_add_unless(&num_events, -1, 1)) {
1879 mutex_lock(&pmc_reserve_mutex);
1880 if (atomic_dec_return(&num_events) == 0)
1881 release_pmc_hardware();
1882 mutex_unlock(&pmc_reserve_mutex);
1887 * Translate a generic cache event_id config to a raw event_id code.
1889 static int hw_perf_cache_event(u64 config, u64 *eventp)
1891 unsigned long type, op, result;
1894 if (!ppmu->cache_events)
1898 type = config & 0xff;
1899 op = (config >> 8) & 0xff;
1900 result = (config >> 16) & 0xff;
1902 if (type >= PERF_COUNT_HW_CACHE_MAX ||
1903 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
1904 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1907 ev = (*ppmu->cache_events)[type][op][result];
1916 static bool is_event_blacklisted(u64 ev)
1920 for (i=0; i < ppmu->n_blacklist_ev; i++) {
1921 if (ppmu->blacklist_ev[i] == ev)
1928 static int power_pmu_event_init(struct perf_event *event)
1931 unsigned long flags, irq_flags;
1932 struct perf_event *ctrs[MAX_HWEVENTS];
1933 u64 events[MAX_HWEVENTS];
1934 unsigned int cflags[MAX_HWEVENTS];
1937 struct cpu_hw_events *cpuhw;
1942 if (has_branch_stack(event)) {
1943 /* PMU has BHRB enabled */
1944 if (!(ppmu->flags & PPMU_ARCH_207S))
1948 switch (event->attr.type) {
1949 case PERF_TYPE_HARDWARE:
1950 ev = event->attr.config;
1951 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
1954 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1956 ev = ppmu->generic_events[ev];
1958 case PERF_TYPE_HW_CACHE:
1959 err = hw_perf_cache_event(event->attr.config, &ev);
1963 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1967 ev = event->attr.config;
1969 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1977 * PMU config registers have fields that are
1978 * reserved and some specific values for bit fields are reserved.
1979 * For ex., MMCRA[61:62] is Randome Sampling Mode (SM)
1980 * and value of 0b11 to this field is reserved.
1981 * Check for invalid values in attr.config.
1983 if (ppmu->check_attr_config &&
1984 ppmu->check_attr_config(event))
1987 event->hw.config_base = ev;
1991 * If we are not running on a hypervisor, force the
1992 * exclude_hv bit to 0 so that we don't care what
1993 * the user set it to.
1995 if (!firmware_has_feature(FW_FEATURE_LPAR))
1996 event->attr.exclude_hv = 0;
1999 * If this is a per-task event, then we can use
2000 * PM_RUN_* events interchangeably with their non RUN_*
2001 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
2002 * XXX we should check if the task is an idle task.
2005 if (event->attach_state & PERF_ATTACH_TASK)
2006 flags |= PPMU_ONLY_COUNT_RUN;
2009 * If this machine has limited events, check whether this
2010 * event_id could go on a limited event.
2012 if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
2013 if (can_go_on_limited_pmc(event, ev, flags)) {
2014 flags |= PPMU_LIMITED_PMC_OK;
2015 } else if (ppmu->limited_pmc_event(ev)) {
2017 * The requested event_id is on a limited PMC,
2018 * but we can't use a limited PMC; see if any
2019 * alternative goes on a normal PMC.
2021 ev = normal_pmc_alternative(ev, flags);
2027 /* Extra checks for EBB */
2028 err = ebb_event_check(event);
2033 * If this is in a group, check if it can go on with all the
2034 * other hardware events in the group. We assume the event
2035 * hasn't been linked into its leader's sibling list at this point.
2038 if (event->group_leader != event) {
2039 n = collect_events(event->group_leader, ppmu->n_counter - 1,
2040 ctrs, events, cflags);
2047 if (check_excludes(ctrs, cflags, n, 1))
2050 local_irq_save(irq_flags);
2051 cpuhw = this_cpu_ptr(&cpu_hw_events);
2053 err = power_check_constraints(cpuhw, events, cflags, n + 1, ctrs);
2055 if (has_branch_stack(event)) {
2056 u64 bhrb_filter = -1;
2058 if (ppmu->bhrb_filter_map)
2059 bhrb_filter = ppmu->bhrb_filter_map(
2060 event->attr.branch_sample_type);
2062 if (bhrb_filter == -1) {
2063 local_irq_restore(irq_flags);
2066 cpuhw->bhrb_filter = bhrb_filter;
2069 local_irq_restore(irq_flags);
2073 event->hw.config = events[n];
2074 event->hw.event_base = cflags[n];
2075 event->hw.last_period = event->hw.sample_period;
2076 local64_set(&event->hw.period_left, event->hw.last_period);
2079 * For EBB events we just context switch the PMC value, we don't do any
2080 * of the sample_period logic. We use hw.prev_count for this.
2082 if (is_ebb_event(event))
2083 local64_set(&event->hw.prev_count, 0);
2086 * See if we need to reserve the PMU.
2087 * If no events are currently in use, then we have to take a
2088 * mutex to ensure that we don't race with another task doing
2089 * reserve_pmc_hardware or release_pmc_hardware.
2092 if (!atomic_inc_not_zero(&num_events)) {
2093 mutex_lock(&pmc_reserve_mutex);
2094 if (atomic_read(&num_events) == 0 &&
2095 reserve_pmc_hardware(perf_event_interrupt))
2098 atomic_inc(&num_events);
2099 mutex_unlock(&pmc_reserve_mutex);
2101 event->destroy = hw_perf_event_destroy;
2106 static int power_pmu_event_idx(struct perf_event *event)
2108 return event->hw.idx;
2111 ssize_t power_events_sysfs_show(struct device *dev,
2112 struct device_attribute *attr, char *page)
2114 struct perf_pmu_events_attr *pmu_attr;
2116 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
2118 return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
2121 static struct pmu power_pmu = {
2122 .pmu_enable = power_pmu_enable,
2123 .pmu_disable = power_pmu_disable,
2124 .event_init = power_pmu_event_init,
2125 .add = power_pmu_add,
2126 .del = power_pmu_del,
2127 .start = power_pmu_start,
2128 .stop = power_pmu_stop,
2129 .read = power_pmu_read,
2130 .start_txn = power_pmu_start_txn,
2131 .cancel_txn = power_pmu_cancel_txn,
2132 .commit_txn = power_pmu_commit_txn,
2133 .event_idx = power_pmu_event_idx,
2134 .sched_task = power_pmu_sched_task,
2137 #define PERF_SAMPLE_ADDR_TYPE (PERF_SAMPLE_ADDR | \
2138 PERF_SAMPLE_PHYS_ADDR | \
2139 PERF_SAMPLE_DATA_PAGE_SIZE)
2141 * A counter has overflowed; update its count and record
2142 * things if requested. Note that interrupts are hard-disabled
2143 * here so there is no possibility of being interrupted.
2145 static void record_and_restart(struct perf_event *event, unsigned long val,
2146 struct pt_regs *regs)
2148 u64 period = event->hw.sample_period;
2149 s64 prev, delta, left;
2152 if (event->hw.state & PERF_HES_STOPPED) {
2153 write_pmc(event->hw.idx, 0);
2157 /* we don't have to worry about interrupts here */
2158 prev = local64_read(&event->hw.prev_count);
2159 delta = check_and_compute_delta(prev, val);
2160 local64_add(delta, &event->count);
2163 * See if the total period for this event has expired,
2164 * and update for the next period.
2167 left = local64_read(&event->hw.period_left) - delta;
2177 * If address is not requested in the sample via
2178 * PERF_SAMPLE_IP, just record that sample irrespective
2179 * of SIAR valid check.
2181 if (event->attr.sample_type & PERF_SAMPLE_IP)
2182 record = siar_valid(regs);
2186 event->hw.last_period = event->hw.sample_period;
2188 if (left < 0x80000000LL)
2189 val = 0x80000000LL - left;
2192 write_pmc(event->hw.idx, val);
2193 local64_set(&event->hw.prev_count, val);
2194 local64_set(&event->hw.period_left, left);
2195 perf_event_update_userpage(event);
2198 * Due to hardware limitation, sometimes SIAR could sample a kernel
2199 * address even when freeze on supervisor state (kernel) is set in
2200 * MMCR2. Check attr.exclude_kernel and address to drop the sample in
2203 if (event->attr.exclude_kernel &&
2204 (event->attr.sample_type & PERF_SAMPLE_IP) &&
2205 is_kernel_addr(mfspr(SPRN_SIAR)))
2209 * Finally record data if requested.
2212 struct perf_sample_data data;
2214 perf_sample_data_init(&data, ~0ULL, event->hw.last_period);
2216 if (event->attr.sample_type & PERF_SAMPLE_ADDR_TYPE)
2217 perf_get_data_addr(event, regs, &data.addr);
2219 if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) {
2220 struct cpu_hw_events *cpuhw;
2221 cpuhw = this_cpu_ptr(&cpu_hw_events);
2222 power_pmu_bhrb_read(event, cpuhw);
2223 data.br_stack = &cpuhw->bhrb_stack;
2226 if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
2227 ppmu->get_mem_data_src)
2228 ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs);
2230 if (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE &&
2231 ppmu->get_mem_weight)
2232 ppmu->get_mem_weight(&data.weight.full, event->attr.sample_type);
2234 if (perf_event_overflow(event, &data, regs))
2235 power_pmu_stop(event, 0);
2236 } else if (period) {
2237 /* Account for interrupt in case of invalid SIAR */
2238 if (perf_event_account_interrupt(event))
2239 power_pmu_stop(event, 0);
2244 * Called from generic code to get the misc flags (i.e. processor mode)
2247 unsigned long perf_misc_flags(struct pt_regs *regs)
2249 u32 flags = perf_get_misc_flags(regs);
2253 return user_mode(regs) ? PERF_RECORD_MISC_USER :
2254 PERF_RECORD_MISC_KERNEL;
2258 * Called from generic code to get the instruction pointer
2261 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2263 unsigned long siar = mfspr(SPRN_SIAR);
2265 if (regs_use_siar(regs) && siar_valid(regs) && siar)
2266 return siar + perf_ip_adjust(regs);
2271 static bool pmc_overflow_power7(unsigned long val)
2274 * Events on POWER7 can roll back if a speculative event doesn't
2275 * eventually complete. Unfortunately in some rare cases they will
2276 * raise a performance monitor exception. We need to catch this to
2277 * ensure we reset the PMC. In all cases the PMC will be 256 or less
2278 * cycles from overflow.
2280 * We only do this if the first pass fails to find any overflowing
2281 * PMCs because a user might set a period of less than 256 and we
2282 * don't want to mistakenly reset them.
2284 if ((0x80000000 - val) <= 256)
2290 static bool pmc_overflow(unsigned long val)
2299 * Performance monitor interrupt stuff
2301 static void __perf_event_interrupt(struct pt_regs *regs)
2304 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
2305 struct perf_event *event;
2308 if (cpuhw->n_limited)
2309 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
2312 perf_read_regs(regs);
2314 /* Read all the PMCs since we'll need them a bunch of times */
2315 for (i = 0; i < ppmu->n_counter; ++i)
2316 cpuhw->pmcs[i] = read_pmc(i + 1);
2318 /* Try to find what caused the IRQ */
2320 for (i = 0; i < ppmu->n_counter; ++i) {
2321 if (!pmc_overflow(cpuhw->pmcs[i]))
2323 if (is_limited_pmc(i + 1))
2324 continue; /* these won't generate IRQs */
2326 * We've found one that's overflowed. For active
2327 * counters we need to log this. For inactive
2328 * counters, we need to reset it anyway
2332 for (j = 0; j < cpuhw->n_events; ++j) {
2333 event = cpuhw->event[j];
2334 if (event->hw.idx == (i + 1)) {
2336 record_and_restart(event, cpuhw->pmcs[i], regs);
2341 /* reset non active counters that have overflowed */
2342 write_pmc(i + 1, 0);
2344 if (!found && pvr_version_is(PVR_POWER7)) {
2345 /* check active counters for special buggy p7 overflow */
2346 for (i = 0; i < cpuhw->n_events; ++i) {
2347 event = cpuhw->event[i];
2348 if (!event->hw.idx || is_limited_pmc(event->hw.idx))
2350 if (pmc_overflow_power7(cpuhw->pmcs[event->hw.idx - 1])) {
2351 /* event has overflowed in a buggy way*/
2353 record_and_restart(event,
2354 cpuhw->pmcs[event->hw.idx - 1],
2359 if (unlikely(!found) && !arch_irq_disabled_regs(regs))
2360 printk_ratelimited(KERN_WARNING "Can't find PMC that caused IRQ\n");
2363 * Reset MMCR0 to its normal value. This will set PMXE and
2364 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
2365 * and thus allow interrupts to occur again.
2366 * XXX might want to use MSR.PM to keep the events frozen until
2367 * we get back out of this interrupt.
2369 write_mmcr0(cpuhw, cpuhw->mmcr.mmcr0);
2371 /* Clear the cpuhw->pmcs */
2372 memset(&cpuhw->pmcs, 0, sizeof(cpuhw->pmcs));
2376 static void perf_event_interrupt(struct pt_regs *regs)
2378 u64 start_clock = sched_clock();
2380 __perf_event_interrupt(regs);
2381 perf_sample_event_took(sched_clock() - start_clock);
2384 static int power_pmu_prepare_cpu(unsigned int cpu)
2386 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
2389 memset(cpuhw, 0, sizeof(*cpuhw));
2390 cpuhw->mmcr.mmcr0 = MMCR0_FC;
2395 int register_power_pmu(struct power_pmu *pmu)
2398 return -EBUSY; /* something's already registered */
2401 pr_info("%s performance monitor hardware support registered\n",
2404 power_pmu.attr_groups = ppmu->attr_groups;
2405 power_pmu.capabilities |= (ppmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS);
2409 * Use FCHV to ignore kernel events if MSR.HV is set.
2411 if (mfmsr() & MSR_HV)
2412 freeze_events_kernel = MMCR0_FCHV;
2413 #endif /* CONFIG_PPC64 */
2415 perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW);
2416 cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare",
2417 power_pmu_prepare_cpu, NULL);
2422 static int __init init_ppc64_pmu(void)
2424 /* run through all the pmu drivers one at a time */
2425 if (!init_power5_pmu())
2427 else if (!init_power5p_pmu())
2429 else if (!init_power6_pmu())
2431 else if (!init_power7_pmu())
2433 else if (!init_power8_pmu())
2435 else if (!init_power9_pmu())
2437 else if (!init_power10_pmu())
2439 else if (!init_ppc970_pmu())
2442 return init_generic_compat_pmu();
2444 early_initcall(init_ppc64_pmu);